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Merge pull request #5921 from phsauter/peepopt-shiftpow2
peepopt: add shiftpow2 pattern
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nella
GitHub
commit
8125af88d6
4 changed files with 253 additions and 5 deletions
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@ -32,6 +32,7 @@ $(eval $(call add_extra_objs,passes/opt/peepopt_pm.h))
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PEEPOPT_PATTERN = passes/opt/peepopt_shiftmul_right.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftmul_left.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftadd.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftpow2.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv_c.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
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@ -68,6 +68,12 @@ struct PeepoptPass : public Pass {
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log(" limits the amount of padding to a multiple of the data, \n");
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log(" to avoid high resource usage from large temporary MUX trees.\n");
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log("\n");
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log(" * shiftpow2 - Replace A>>(B<<K) with a $bmux word multiplexer when\n");
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log(" the output width is at most the stride 1<<K. This handles\n");
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log(" power-of-two aligned word selects.\n");
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log(" Scratchpad: 'peepopt.shiftpow2.max_data_multiple' (default: 2)\n");
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log(" limits padding for out-of-range select values.\n");
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log("\n");
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log("If -formalclk is specified it instead employs the following rules:\n");
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log("\n");
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log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n");
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@ -115,6 +121,7 @@ struct PeepoptPass : public Pass {
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pm.run_shiftadd();
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pm.run_shiftmul_right();
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pm.run_shiftmul_left();
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pm.run_shiftpow2();
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pm.run_muldiv();
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pm.run_muldiv_c();
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}
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87
passes/opt/peepopt_shiftpow2.pmg
Normal file
87
passes/opt/peepopt_shiftpow2.pmg
Normal file
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@ -0,0 +1,87 @@
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pattern shiftpow2
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//
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// Optimize shifts that result from expressions such as foo[s*W+:W]
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// when W is a power of two and the multiply has been folded away.
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//
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match shift
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select shift->type.in($shift, $shiftx, $shr)
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filter !port(shift, \B).empty()
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endmatch
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code
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{
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// make sure the shift amount cannot be negative
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SigSpec amount = port(shift, \B);
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bool b_signed = shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool();
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if (!b_signed)
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amount.append(State::S0);
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if (amount.bits().back() != State::S0)
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reject;
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while (GetSize(amount) > 1 && amount.bits().back() == State::S0)
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amount.remove(GetSize(amount) - 1);
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// low zero bits encode the power-of-two scale
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int log2scale = 0;
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while (!amount.empty() && amount[0] == State::S0) {
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amount.remove(0);
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log2scale++;
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}
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if (log2scale < 1)
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reject;
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if (amount.empty() || amount.is_fully_const())
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reject;
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SigSpec sel = amount;
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int sel_width = GetSize(sel);
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int width = param(shift, \Y_WIDTH).as_int();
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if (log2scale >= 8 * (int)sizeof(int) - 1)
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reject;
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int stride = 1 << log2scale;
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// avoid overlapping selections
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if (width > stride)
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reject;
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if (sel_width > 20)
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reject;
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long long ways = 1LL << sel_width;
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SigSpec A = port(shift, \A);
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int a_width = GetSize(A);
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bool a_signed = !shift->type.in($shiftx) && param(shift, \A_SIGNED).as_bool();
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int extended_a_width = a_signed ? std::max(a_width, width) : a_width;
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// limit padding for out-of-range select values
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int max_ratio = module->design->scratchpad_get_int("peepopt.shiftpow2.max_data_multiple", 2);
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if (ways * (long long)width > (long long)max_ratio * std::max(a_width, width))
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reject;
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did_something = true;
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log("shiftpow2 pattern in %s: shift=%s, index=%s, stride=%d, width=%d, ways=%lld\n",
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module, shift, log_signal(sel), stride, width, ways);
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// way m holds A[m*stride +: width], way 0 in the LSBs
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State fill = shift->type.in($shiftx) ? State::Sx : State::S0;
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SigSpec bmux_a;
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for (long long m = 0; m < ways; m++) {
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long long base = m * (long long)stride;
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for (int b = 0; b < width; b++) {
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long long idx = base + b;
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if (idx < a_width)
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bmux_a.append(A[idx]);
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else if (idx < extended_a_width)
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bmux_a.append(A.back());
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else
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bmux_a.append(fill);
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}
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}
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module->addBmux(NEW_ID, bmux_a, sel, port(shift, \Y));
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autoremove(shift);
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accept;
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}
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endcode
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@ -8,8 +8,8 @@ prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shiftx
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select -assert-count 0 t:$shiftx t:* %D
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$bmux t:* %D
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####################
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@ -72,9 +72,10 @@ design -import gate -as gate peepopt_shiftmul_3
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -verify -show-public -enable_undef -prove-asserts miter
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cd gate
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$shr
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select -assert-count 0 t:$mul
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####################
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@ -92,3 +93,155 @@ equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 0 t:*
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####################
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# shiftpow2: a power-of-two part-select i[s*W+:W] becomes a $bmux word mux
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_0 #(parameter M=8, parameter W=4) (input [M*W-1:0] i, input [$clog2(M)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$bmux t:* %D
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####################
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# shiftpow2: explicit aligned right shift D >> (S*8), checked by SAT miter
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_1 (input [63:0] D, input [2:0] S, output [7:0] Y);
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assign Y = D >> (S*8);
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endmodule
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EOT
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prep
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftpow2_1
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design -import gate -as gate peepopt_shiftpow2_1
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -verify -show-public -enable_undef -prove-asserts miter
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cd gate
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$shr
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####################
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# shiftpow2: width smaller than stride is non-overlapping
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_narrow (input [31:0] D, input [2:0] S, output [3:0] Y);
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assign Y = D >> (S*8);
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endmodule
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EOT
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prep
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftpow2_narrow
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design -import gate -as gate peepopt_shiftpow2_narrow
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -verify -show-public -enable_undef -prove-asserts miter
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cd gate
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$shr
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####################
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# shiftpow2: signed part-select with out-of-range padding
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_signed (input signed [15:0] i, input [2:0] s, output [3:0] o);
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assign o = i[s*4 +: 4];
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endmodule
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EOT
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prep
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# drive wreduce to a fixed point before checking for the reduced shift
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wreduce
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftpow2_signed
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design -import gate -as gate peepopt_shiftpow2_signed
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miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
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sat -verify -show-public -enable_undef -prove-asserts miter
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cd gate
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$shiftx
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####################
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# shiftpow2: signed $shr extends A to Y_WIDTH
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_signed_shr (input signed [3:0] D, input S, output [7:0] Y);
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assign Y = D >> (S*8);
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endmodule
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EOT
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prep
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design -save gold
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peepopt
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design -stash gate
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design -import gold -as gold peepopt_shiftpow2_signed_shr
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design -import gate -as gate peepopt_shiftpow2_signed_shr
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miter -equiv -make_assert -make_outputs -flatten gold gate miter
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sat -verify -show-public -prove-asserts miter
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cd gate
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$shr
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####################
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# shiftpow2 must NOT fire for overlapping selections
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_overlap (input [31:0] D, input [1:0] S, output [7:0] Y);
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assign Y = D >> (S*4);
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endmodule
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EOT
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prep -nokeepdc
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peepopt
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clean
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select -assert-count 0 t:$bmux
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select -assert-count 1 t:$shr
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####################
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# shiftpow2: shiftmul can expose a non-overlapping power-of-two stride
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design -reset
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read_verilog <<EOT
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module peepopt_shiftpow2_shiftmul #(parameter M=8, parameter W=3) (input [M*W-1:0] i, input [2:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$bmux
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select -assert-count 0 t:$bmux t:* %D
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