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Handle $shift and Y_WIDTH > 1 as per @cliffordwolf

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This commit is contained in:
Eddie Hung 2019-08-22 08:22:23 -07:00
parent 9e31f01b34
commit 379f33af54
2 changed files with 51 additions and 5 deletions
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44
tests/opt/opt_expr.ys
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@ -226,7 +226,7 @@ select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -icells <<EOT
module opt_expr_shiftx(input [2:0] a, input [1:0] b, output y);
module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y);
\$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
endmodule
EOT
@ -235,3 +235,45 @@ check
equiv_opt opt_expr
design -load postopt
select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
###########
design -reset
read_verilog -icells <<EOT
module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
\$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y));
endmodule
EOT
check
equiv_opt opt_expr
design -load postopt
select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
###########
design -reset
read_verilog -icells <<EOT
module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y);
\$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y));
endmodule
EOT
check
equiv_opt opt_expr
design -load postopt
select -assert-count 1 t:$shift r:A_WIDTH=3 %i
###########
design -reset
read_verilog -icells <<EOT
module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
\$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
endmodule
EOT
check
equiv_opt opt_expr
design -load postopt
select -assert-count 1 t:$shift r:A_WIDTH=10 %i