Merge remote-tracking branch 'upstream' into merge3

tests/techmap/bmuxmap_pmux.ys

@@ -41,5 +41,3 @@ EOT
 
 hierarchy -auto-top
 equiv_opt -assert bmuxmap -pmux
-
-

tests/techmap/bug5495.sh

@@ -9,4 +9,3 @@ if ! timeout 10 ${YOSYS} bug5495.v -p 'hierarchy; techmap; abc -script bug5495.a
     echo "Yosys failed to complete"
     exit 1
 fi
-

tests/techmap/clockgate.lib

@@ -110,4 +110,4 @@ library(test) {
             direction : input;
         }
     }
-}
+}

tests/techmap/clockgate.v

@@ -41,4 +41,4 @@ module dffe_wide_11( input clk, en,
 		if ( en )
 			q1 <= d1;
 	end
-endmodule
+endmodule

tests/techmap/clockgate_bad.il

@@ -28,4 +28,4 @@ module \bad2
     connect \EN \en
     connect \Q \q1
   end
-end
+end

tests/techmap/clockgate_neg.lib

@@ -52,4 +52,4 @@ library(test) {
             direction : input;
         }
     }
-}
+}

tests/techmap/clockgate_pos.lib

@@ -52,4 +52,4 @@ library(test) {
             direction : input;
         }
     }
-}
+}

tests/techmap/clockgate_wide.v

@@ -5,4 +5,4 @@ module dffe_wide_11( input clk, input [1:0] en,
 		if ( en[0] )
 			q1 <= d1;
 	end
-endmodule
+endmodule

tests/techmap/dfflegalize_dlatch_emu.ys

@@ -0,0 +1,25 @@
+read_verilog -icells <<EOT
+
+module top(input E, S, R, D, output [5:0] Q);
+$_DLATCH_PP0_  ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
+$_DLATCH_PN0_  ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
+$_DLATCH_PP1_  ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
+$_DLATCH_PN1_  ff3 (.E(E), .R(R), .D(D), .Q(Q[3]));
+$_DLATCHSR_PPP_ ff4 (.E(E), .S(S), .R(R), .D(D), .Q(Q[4]));
+$_DLATCHSR_PNP_ ff5 (.E(E), .S(S), .R(R), .D(D), .Q(Q[5]));
+endmodule
+EOT
+
+design -save orig
+
+logger -expect warning "Emulating async reset latch with a plain D latch" 4
+logger -expect warning "Emulating async set \+ reset latch with a plain D latch" 2
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
+logger -check-expected
+
+design -load orig
+dfflegalize -cell $_DLATCH_P_ x
+select -assert-count 6 t:$_DLATCH_P_
+select -assert-count 0 t:$_DLATCHSR_???_
+select -assert-count 0 t:$_DLATCH_??0_
+select -assert-count 0 t:$_DLATCH_??1_

tests/techmap/dfflibmap_dffn_dffe.lib

@@ -4,7 +4,7 @@ library(test) {
     ff("IQ", "IQN") {
       next_state : "D";
       clocked_on : "!CLK";
-    } 
+    }
     pin(D) {
       direction : input;
     }
@@ -18,7 +18,7 @@ library(test) {
     pin(QN) {
       direction: output;
       function : "IQN";
-    } 
+    }
   }
   cell (dffe) {
     area : 6;

tests/techmap/dfflibmap_dffsr_not_next.lib

@@ -25,4 +25,4 @@ library (test_not_next) {
       preset : "!RN";
     }
   }
-}
+}

tests/techmap/dfflibmap_formal.ys

@@ -265,4 +265,4 @@ flatten
 opt_clean -purge
 equiv_make top top_unmapped equiv
 equiv_induct -set-assumes equiv
-equiv_status -assert equiv
+equiv_status -assert equiv

tests/techmap/mem_simple_4x1_map.v

@@ -149,4 +149,3 @@ module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
 	  end
 	endgenerate
 endmodule
-