From cdc728b6f009ba9faa9829e26332f428896a0b77 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 20 Feb 2026 09:33:51 -0800 Subject: [PATCH 01/82] Suggest use of YW when possible --- passes/sat/sim.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 27d6d12c1..5392cd9e5 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2624,6 +2624,7 @@ struct SimPass : public Pass { log(" -r \n"); log(" read simulation or formal results file\n"); log(" File formats supported: FST, VCD, AIW, WIT and .yw\n"); + log(" Yosys witness (.yw) replay is preferred when possible.\n"); log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -width \n"); From b454582f540753343524d33e7d2e3ad8ca95972b Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 20 Feb 2026 11:00:59 -0800 Subject: [PATCH 02/82] Detect undriven and error/warn --- passes/sat/sim.cc | 81 ++++++++++++++++++++++++++++++++--- tests/sim/undriven_replay.v | 7 +++ tests/sim/undriven_replay.vcd | 15 +++++++ tests/sim/undriven_replay.ys | 10 +++++ 4 files changed, 108 insertions(+), 5 deletions(-) create mode 100644 tests/sim/undriven_replay.v create mode 100644 tests/sim/undriven_replay.vcd create mode 100644 tests/sim/undriven_replay.ys diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 5392cd9e5..bd723f5f1 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -26,6 +26,7 @@ #include "kernel/yw.h" #include "kernel/json.h" #include "kernel/fmt.h" +#include "kernel/drivertools.h" #include @@ -125,6 +126,8 @@ struct SimShared bool serious_asserts = false; bool fst_noinit = false; bool initstate = true; + bool undriven_check = true; + bool undriven_warning = false; }; void zinit(Const &v) @@ -426,7 +429,7 @@ struct SimInstance Const value = builder.build(); if (shared->debug) - log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value)); + log("[%s] get %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); return value; } @@ -445,7 +448,7 @@ struct SimInstance } if (shared->debug) - log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value)); + log("[%s] set %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); return did_something; } @@ -1192,6 +1195,54 @@ struct SimInstance child.second->addAdditionalInputs(); } + // Preconditions / assumptions: + // 1) fst_handles is populated for this instance (0 handle means not in trace). + // 2) fst_inputs is finalized (top-level inputs + addAdditionalInputs() for $anyseq). + // 3) module has no processes (sim enforces proc-lowered input before this point). + // 4) sigmap is valid for per-bit queries on this instance. + // 5) shared->fst is active, i.e. this is called from FST/VCD replay flow. + int checkUndrivenReplaySignals() + { + int issue_count = 0; + bool has_replay_candidates = false; + + for (auto &item : fst_handles) + if (item.second != 0 && !fst_inputs.count(item.first)) { + has_replay_candidates = true; + break; + } + + if (has_replay_candidates) { + DriverMap drivermap(module->design); + drivermap.add(module); + + for (auto &item : fst_handles) { + Wire *wire = item.first; + if (item.second == 0 || fst_inputs.count(wire)) + continue; + + SigSpec undriven; + for (auto bit : sigmap(wire)) + if (bit.wire != nullptr && drivermap(DriveBit(bit)).is_none()) + undriven.append(bit); + + undriven.sort_and_unify(); + if (undriven.empty()) + continue; + + issue_count++; + std::string wire_name = scope + "." + RTLIL::unescape_id(wire->name); + log_warning("Input trace contains undriven signal `%s` (%s); values for this signal are not replayed from FST/VCD input.\n", + wire_name.c_str(), log_signal(undriven, true)); + } + } + + for (auto child : children) + issue_count += child.second->checkUndrivenReplaySignals(); + + return issue_count; + } + bool setInputs() { bool did_something = false; @@ -1248,7 +1299,7 @@ struct SimInstance } else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X for(int i=0;isim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X for(int i=0;iaddAdditionalInputs(); + if (undriven_check) { + int issue_count = top->checkUndrivenReplaySignals(); + if (issue_count > 0 && !undriven_warning) + log_cmd_error("Found %d undriven signal%s in the replay trace. Use -undriven-warn to continue or -no-undriven-check to disable this check.\n", + issue_count, issue_count == 1 ? "" : "s"); + } uint64_t startCount = 0; uint64_t stopCount = 0; @@ -2627,6 +2684,12 @@ struct SimPass : public Pass { log(" Yosys witness (.yw) replay is preferred when possible.\n"); log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); + log(" -no-undriven-check\n"); + log(" skip undriven-signal checks for FST/VCD replay\n"); + log("\n"); + log(" -undriven-warn\n"); + log(" downgrade undriven-signal replay errors to warnings\n"); + log("\n"); log(" -width \n"); log(" cycle width in generated simulation output (must be divisible by 2).\n"); log("\n"); @@ -2844,6 +2907,14 @@ struct SimPass : public Pass { worker.fst_noinit = true; continue; } + if (args[argidx] == "-no-undriven-check") { + worker.undriven_check = false; + continue; + } + if (args[argidx] == "-undriven-warn") { + worker.undriven_warning = true; + continue; + } if (args[argidx] == "-x") { worker.ignore_x = true; continue; diff --git a/tests/sim/undriven_replay.v b/tests/sim/undriven_replay.v new file mode 100644 index 000000000..501f438a1 --- /dev/null +++ b/tests/sim/undriven_replay.v @@ -0,0 +1,7 @@ +module undriven_replay ( + input wire in, + output wire out, + output wire undrv +); + assign out = in; +endmodule diff --git a/tests/sim/undriven_replay.vcd b/tests/sim/undriven_replay.vcd new file mode 100644 index 000000000..e9cc35ae5 --- /dev/null +++ b/tests/sim/undriven_replay.vcd @@ -0,0 +1,15 @@ +$version Yosys $end +$scope module undriven_replay $end +$var wire 1 ! in $end +$var wire 1 " out $end +$var wire 1 # undrv $end +$upscope $end +$enddefinitions $end +#0 +b0 ! +b0 " +b1 # +#10 +b1 ! +b1 " +b0 # diff --git a/tests/sim/undriven_replay.ys b/tests/sim/undriven_replay.ys new file mode 100644 index 000000000..9766a8d60 --- /dev/null +++ b/tests/sim/undriven_replay.ys @@ -0,0 +1,10 @@ +read_verilog undriven_replay.v +prep -top undriven_replay + +logger -expect error "Found 1 undriven signal in the replay trace" 1 +sim -r undriven_replay.vcd -scope undriven_replay -q + +logger -expect warning "Input trace contains undriven signal" 1 +sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn + +sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check From c0f1654028736cd88d2fa7cae5b0335371e8e866 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 23 Feb 2026 10:27:36 -0800 Subject: [PATCH 03/82] Expand test into three tests for three cases (1) no check, (2) check with warning, (3) check with error. Previously the single test was not testing all cases, as it was exiting after the first error. --- tests/sim/undriven_replay.ys | 5 ----- tests/sim/undriven_replay_nocheck.ys | 4 ++++ tests/sim/undriven_replay_warn.ys | 5 +++++ 3 files changed, 9 insertions(+), 5 deletions(-) create mode 100644 tests/sim/undriven_replay_nocheck.ys create mode 100644 tests/sim/undriven_replay_warn.ys diff --git a/tests/sim/undriven_replay.ys b/tests/sim/undriven_replay.ys index 9766a8d60..854a40049 100644 --- a/tests/sim/undriven_replay.ys +++ b/tests/sim/undriven_replay.ys @@ -3,8 +3,3 @@ prep -top undriven_replay logger -expect error "Found 1 undriven signal in the replay trace" 1 sim -r undriven_replay.vcd -scope undriven_replay -q - -logger -expect warning "Input trace contains undriven signal" 1 -sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn - -sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check diff --git a/tests/sim/undriven_replay_nocheck.ys b/tests/sim/undriven_replay_nocheck.ys new file mode 100644 index 000000000..dcb1cfc92 --- /dev/null +++ b/tests/sim/undriven_replay_nocheck.ys @@ -0,0 +1,4 @@ +read_verilog undriven_replay.v +prep -top undriven_replay + +sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check diff --git a/tests/sim/undriven_replay_warn.ys b/tests/sim/undriven_replay_warn.ys new file mode 100644 index 000000000..ca3b1937c --- /dev/null +++ b/tests/sim/undriven_replay_warn.ys @@ -0,0 +1,5 @@ +read_verilog undriven_replay.v +prep -top undriven_replay + +logger -expect warning "Input trace contains undriven signal" 1 +sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn From 366f98ae25bf45be94a6ea8118abe431eb676bdf Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 23 Feb 2026 11:51:54 -0800 Subject: [PATCH 04/82] ADd clarification --- passes/sat/sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index bd723f5f1..ddc256384 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2685,7 +2685,7 @@ struct SimPass : public Pass { log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -no-undriven-check\n"); - log(" skip undriven-signal checks for FST/VCD replay\n"); + log(" skip undriven-signal checks for FST/VCD replay (can be expensive for large designs)\n"); log("\n"); log(" -undriven-warn\n"); log(" downgrade undriven-signal replay errors to warnings\n"); From 7d3e56523bf93fb3c63fc19de843278f38e43012 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 13 May 2026 16:25:15 +0200 Subject: [PATCH 05/82] Preserve param signedness across overrides. --- kernel/rtlil.cc | 9 +++++++++ kernel/rtlil.h | 2 ++ passes/cmds/setattr.cc | 1 + passes/hierarchy/hierarchy.cc | 8 ++++++-- tests/verilog/issue5745.ys | 18 ++++++++++++++++++ 5 files changed, 36 insertions(+), 2 deletions(-) create mode 100644 tests/verilog/issue5745.ys diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a99f0803e..1a7dc6b41 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -615,6 +615,15 @@ int RTLIL::Const::as_int_saturating(bool is_signed) const return as_int(is_signed); } +void RTLIL::Const::tag_bare_integer_const(const std::string &value) +{ + if (value.empty() || value.find('\'') != std::string::npos) + return; + size_t start = (value[0] == '-' || value[0] == '+') ? 1 : 0; + if (start < value.size() && std::all_of(value.begin() + start, value.end(), ::isdigit)) + flags |= RTLIL::CONST_FLAG_SIGNED; +} + int RTLIL::Const::get_min_size(bool is_signed) const { if (empty()) return 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b32f9ea76..e55caf35a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1091,6 +1091,8 @@ public: // over/underflow, otherwise the max/min value for int depending on the sign. int as_int_saturating(bool is_signed = false) const; + void tag_bare_integer_const(const std::string &value); + std::string as_string(const char* any = "-") const; static Const from_string(const std::string &str); std::vector to_bits() const; diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 25d8fd34c..ef9bd0d34 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -41,6 +41,7 @@ struct setunset_t if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value)) log_cmd_error("Can't decode value '%s'!\n", set_value); value = sig_value.as_const(); + value.tag_bare_integer_const(set_value); } } }; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 416997bee..34cedfd34 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -985,7 +985,9 @@ struct HierarchyPass : public Pass { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) log_cmd_error("Can't decode value '%s'!\n", para.second); - top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + RTLIL::Const c = sig_value.as_const(); + c.tag_bare_integer_const(para.second); + top_parameters[RTLIL::escape_id(para.first)] = c; } } @@ -1073,7 +1075,9 @@ struct HierarchyPass : public Pass { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) log_cmd_error("Can't decode value '%s'!\n", para.second); - top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + RTLIL::Const c = sig_value.as_const(); + c.tag_bare_integer_const(para.second); + top_parameters[RTLIL::escape_id(para.first)] = c; } top_mod = design->module(top_mod->derive(design, top_parameters)); diff --git a/tests/verilog/issue5745.ys b/tests/verilog/issue5745.ys new file mode 100644 index 000000000..938ead63a --- /dev/null +++ b/tests/verilog/issue5745.ys @@ -0,0 +1,18 @@ +# Issue #5745: chparam values are unsigned when using read_verilog frontend +# +# When chparam overrides a parameter value, the signed attribute is lost, +# causing signed comparisons to silently use unsigned logic. +# +# m = -32 (signed 9-bit), p2 = 11. Correct signed semantics: -32 < 11, so k = 1. +# Bug: chparam strips the signed attribute from p2. The $lt cell gets A_SIGNED=0, +# B_SIGNED=0, so the comparison treats m as unsigned (480 > 11), giving k = 0. + +read_verilog < Date: Wed, 13 May 2026 16:52:07 +0200 Subject: [PATCH 06/82] Make sure to apply correct signedness to loop vars. --- backends/verilog/verilog_backend.cc | 11 ++--- frontends/ast/simplify.cc | 29 ++++++++----- tests/verilog/for_loop_signed_index.ys | 56 ++++++++++++++++++++++++++ tests/verilog/issue4402.ys | 32 +++++++++++++++ 4 files changed, 112 insertions(+), 16 deletions(-) create mode 100644 tests/verilog/for_loop_signed_index.ys create mode 100644 tests/verilog/issue4402.ys diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 73ffcbf3e..d5f83aefc 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -456,21 +456,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) if (wire->attributes.count(ID::single_bit_vector)) range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset); } + std::string sign = wire->is_signed ? " signed" : ""; if (wire->port_input && !wire->port_output) - f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name)); if (!wire->port_input && wire->port_output) - f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name)); if (wire->port_input && wire->port_output) - f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name)); if (reg_wires.count(wire->name)) { - f << stringf("%s" "reg%s %s", indent, range, id(wire->name)); + f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name)); if (wire->attributes.count(ID::init)) { f << stringf(" = "); dump_const(f, wire->attributes.at(ID::init)); } f << stringf(";\n"); } else - f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name)); #endif } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 48a4291d2..3012a4ccf 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2619,21 +2619,27 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str); auto resolved = current_scope.at(init_ast->children[0]->str); - if (resolved->range_valid) { - int const_size = varbuf->range_left - varbuf->range_right; - int resolved_size = resolved->range_left - resolved->range_right; - if (const_size < resolved_size) { - for (int i = const_size; i < resolved_size; i++) - varbuf->bits.push_back(resolved->is_signed ? varbuf->bits.back() : State::S0); - varbuf->range_left = resolved->range_left; - varbuf->range_right = resolved->range_right; - varbuf->range_swapped = resolved->range_swapped; - varbuf->range_valid = resolved->range_valid; + auto apply_loop_var_type = [&resolved](std::unique_ptr &value) { + if (resolved->range_valid) { + int const_size = value->range_left - value->range_right; + int resolved_size = resolved->range_left - resolved->range_right; + if (const_size < resolved_size) { + for (int i = const_size; i < resolved_size; i++) + value->bits.push_back(resolved->is_signed ? value->bits.back() : State::S0); + value->range_left = resolved->range_left; + value->range_right = resolved->range_right; + value->range_swapped = resolved->range_swapped; + value->range_valid = resolved->range_valid; + } } - } + value->is_signed = resolved->is_signed; + }; + + apply_loop_var_type(varbuf); varbuf = std::make_unique(location, AST_LOCALPARAM, std::move(varbuf)); varbuf->str = init_ast->children[0]->str; + varbuf->is_signed = resolved->is_signed; AstNode *backup_scope_varbuf = current_scope[varbuf->str]; current_scope[varbuf->str] = varbuf.get(); @@ -2708,6 +2714,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (buf->type != AST_CONSTANT) input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type)); + apply_loop_var_type(buf); varbuf->children[0] = std::move(buf); } diff --git a/tests/verilog/for_loop_signed_index.ys b/tests/verilog/for_loop_signed_index.ys new file mode 100644 index 000000000..a2bde3395 --- /dev/null +++ b/tests/verilog/for_loop_signed_index.ys @@ -0,0 +1,56 @@ +# Regression test: when procedural for-loops are unrolled, the constant +# replacement for the loop variable must keep the variable's declared +# signedness. + +read_verilog < y=0 +# Post-synthesis (unfixed): wire0 loses signed, 1<=0 false -> y=1 (BUG) +# Post-synthesis (fixed): wire0 retains signed, -1<=0 true -> y=0 + +! mkdir -p temp + +read_verilog < Date: Sun, 17 May 2026 02:27:55 +0000 Subject: [PATCH 07/82] smt2: use canonical SMT names in memory metadata --- backends/smt2/smt2.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index a9030e18a..66ae4d51c 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -788,7 +788,7 @@ struct Smt2Worker if (has_async_wr && has_sync_wr) log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", cell, module); - decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", mem->memid.unescape(), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync")); + decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync")); decls.push_back(witness_memory(get_id(mem->memid), cell, mem)); string memstate; From 44a1abdadeabf9a9a3d30ccb468ae7a9b14e6864 Mon Sep 17 00:00:00 2001 From: nella Date: Tue, 19 May 2026 12:16:29 +0200 Subject: [PATCH 08/82] Don't repeat VCD warnings + fixups. --- passes/sat/sim.cc | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index ddc256384..2b2982ceb 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -429,7 +429,7 @@ struct SimInstance Const value = builder.build(); if (shared->debug) - log("[%s] get %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); + log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value, true)); return value; } @@ -448,7 +448,7 @@ struct SimInstance } if (shared->debug) - log("[%s] set %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); + log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value, true)); return did_something; } @@ -1201,7 +1201,7 @@ struct SimInstance // 3) module has no processes (sim enforces proc-lowered input before this point). // 4) sigmap is valid for per-bit queries on this instance. // 5) shared->fst is active, i.e. this is called from FST/VCD replay flow. - int checkUndrivenReplaySignals() + int checkUndrivenReplaySignals(bool &any_undriven_found) { int issue_count = 0; bool has_replay_candidates = false; @@ -1231,14 +1231,14 @@ struct SimInstance continue; issue_count++; + any_undriven_found = true; std::string wire_name = scope + "." + RTLIL::unescape_id(wire->name); - log_warning("Input trace contains undriven signal `%s` (%s); values for this signal are not replayed from FST/VCD input.\n", - wire_name.c_str(), log_signal(undriven, true)); + log_warning("Input trace contains undriven signal `%s` (%s).\n", wire_name.c_str(), log_signal(undriven)); } } for (auto child : children) - issue_count += child.second->checkUndrivenReplaySignals(); + issue_count += child.second->checkUndrivenReplaySignals(any_undriven_found); return issue_count; } @@ -1550,7 +1550,10 @@ struct SimWorker : SimShared top->addAdditionalInputs(); if (undriven_check) { - int issue_count = top->checkUndrivenReplaySignals(); + bool any_undriven_found = false; + int issue_count = top->checkUndrivenReplaySignals(any_undriven_found); + if (any_undriven_found) + log_warning("Values for the undriven signal(s) listed above are not replayed from FST/VCD input.\n"); if (issue_count > 0 && !undriven_warning) log_cmd_error("Found %d undriven signal%s in the replay trace. Use -undriven-warn to continue or -no-undriven-check to disable this check.\n", issue_count, issue_count == 1 ? "" : "s"); From 5f2456ac03ee82e45fdda6369dbd0f6c8209cee6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 Jun 2026 09:18:00 +0200 Subject: [PATCH 09/82] WASI now support filesystem --- frontends/verific/verific.cc | 4 ---- frontends/verilog/verilog_frontend.cc | 6 ------ 2 files changed, 10 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f3e49142e..20a23ef8f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -4621,11 +4621,7 @@ struct ReadPass : public Pass { if (use_verific) { args[0] = "verific"; } else { -#if !defined(__wasm) args[0] = "read_verilog_file_list"; -#else - cmd_error(args, 1, "Command files are not supported on this platform.\n"); -#endif } Pass::call(design, args); return; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 29a739f81..2c35b42d5 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -26,9 +26,7 @@ * */ -#if !defined(__wasm) #include -#endif #include "verilog_frontend.h" #include "verilog_lexer.h" @@ -709,8 +707,6 @@ struct VerilogDefines : public Pass { } } VerilogDefines; -#if !defined(__wasm) - static void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path) { std::ifstream flist(file_list_path); @@ -790,6 +786,4 @@ struct VerilogFileList : public Pass { } } VerilogFilelist; -#endif - YOSYS_NAMESPACE_END From 4b5fb15579520cdf74fffdcdf27242d383ad9d9c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 Jun 2026 09:18:05 +0200 Subject: [PATCH 10/82] use env for bash --- libs/fst/00_UPDATE.sh | 2 +- libs/minisat/00_UPDATE.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/fst/00_UPDATE.sh b/libs/fst/00_UPDATE.sh index 91dcd84ff..4fa604b9a 100755 --- a/libs/fst/00_UPDATE.sh +++ b/libs/fst/00_UPDATE.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash mv config.h config.h.bak rm -f *.txt *.cc *.h diff --git a/libs/minisat/00_UPDATE.sh b/libs/minisat/00_UPDATE.sh index 6f3eadfe7..44b652f84 100755 --- a/libs/minisat/00_UPDATE.sh +++ b/libs/minisat/00_UPDATE.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash rm -f LICENSE *.cc *.h git clone --depth 1 https://github.com/niklasso/minisat minisat_upstream From d4ac3b1e7d0c457285cbbcb71a1ec2a3c0997c87 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 Jun 2026 09:24:19 +0200 Subject: [PATCH 11/82] No need for script when CMake is used --- misc/create_vcxsrc.sh | 71 ------------------------------------------- 1 file changed, 71 deletions(-) delete mode 100644 misc/create_vcxsrc.sh diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh deleted file mode 100644 index dccc31fac..000000000 --- a/misc/create_vcxsrc.sh +++ /dev/null @@ -1,71 +0,0 @@ -#!/usr/bin/env bash - -set -ex -vcxsrc="$1" -yosysver="$2" - -rm -rf YosysVS-Tpl-v2.zip YosysVS -wget https://github.com/YosysHQ/yosys/releases/download/resources/YosysVS-Tpl-v2.zip -wget https://github.com/YosysHQ/yosys/releases/download/resources/zlib-1.2.11.tar.gz - -unzip YosysVS-Tpl-v2.zip -rm -f YosysVS-Tpl-v2.zip -tar xvfz zlib-1.2.11.tar.gz - -mv YosysVS "$vcxsrc" -mkdir -p "$vcxsrc"/yosys -mkdir -p "$vcxsrc"/yosys/libs/zlib -mv zlib-1.2.11/* "$vcxsrc"/yosys/libs/zlib/. -rm -rf zlib-1.2.11 -pushd "$vcxsrc"/yosys -ls libs/zlib/*.c | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' >> ../../srcfiles.txt - -if [ -f "/usr/include/FlexLexer.h" ] ; then - mkdir -p libs/flex - cp /usr/include/FlexLexer.h libs/flex/FlexLexer.h - ls libs/flex/*.h >> ../../srcfiles.txt -fi -sed -i '\#libs/../kernel/yosys.h#d' ../../srcfiles.txt - -popd -{ - n=$(grep -B999 '' "$vcxsrc"/YosysVS/YosysVS.vcxproj | wc -l) - head -n$n "$vcxsrc"/YosysVS/YosysVS.vcxproj - egrep '\.(h|hh|hpp|inc)$' srcfiles.txt | sed 's,.*,,' - egrep -v '\.(h|hh|hpp|inc)$' srcfiles.txt | sed 's,.*,,' - tail -n +$((n+1)) "$vcxsrc"/YosysVS/YosysVS.vcxproj -} > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new - -sed -i 's,,\n stdcpp20\n /Zc:__cplusplus %(AdditionalOptions),g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new -sed -i 's,,YOSYS_ENABLE_THREADS;,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new -if [ -f "/usr/include/FlexLexer.h" ] ; then - sed -i 's,,;..\\yosys\\libs\\flex,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new -fi -mv "$vcxsrc"/YosysVS/YosysVS.vcxproj.new "$vcxsrc"/YosysVS/YosysVS.vcxproj - -mkdir -p "$vcxsrc"/yosys -tar -cf - -T srcfiles.txt | tar -xf - -C "$vcxsrc"/yosys -cp -r share "$vcxsrc"/ - -cat > "$vcxsrc"/readme-git.txt << EOT -Want to use a git working copy for the yosys source code? -Open "Git Bash" in this directory and run: - - mv yosys yosys.bak - git clone https://github.com/YosysHQ/yosys.git yosys - cd yosys - git checkout -B main $(git rev-parse HEAD | cut -c1-10) - unzip ../genfiles.zip -EOT - -cat > "$vcxsrc"/readme-abc.txt << EOT -Yosys is using "ABC" for gate-level optimizations and technology -mapping. Download yosys-win32-mxebin-$yosysver.zip and copy the -following files from it into this directory: - - pthreadVC2.dll - yosys-abc.exe -EOT - -sed -i 's/$/\r/; s/\r\r*/\r/g;' "$vcxsrc"/YosysVS/YosysVS.vcxproj "$vcxsrc"/readme-git.txt "$vcxsrc"/readme-abc.txt - From 102f0081940d0438834e20f9b8b946ad4c0b9db5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 Jun 2026 10:03:27 +0200 Subject: [PATCH 12/82] Remove EMSCRIPTEN leftovers --- frontends/ast/ast.cc | 4 --- kernel/driver.cc | 71 -------------------------------------------- kernel/log.cc | 12 ++------ kernel/yosys.cc | 4 +-- passes/cmds/exec.cc | 2 -- 5 files changed, 4 insertions(+), 89 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index f5a601c3a..7e7c7e615 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1079,11 +1079,7 @@ RTLIL::Const AstNode::realAsConst(int width) { double v = round(realvalue); RTLIL::Const result; -#ifdef EMSCRIPTEN - if (!isfinite(v)) { -#else if (!std::isfinite(v)) { -#endif result = std::vector(width, RTLIL::State::Sx); } else { bool is_negative = v < 0; diff --git a/kernel/driver.cc b/kernel/driver.cc index 73b687f80..2a4ad1295 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -70,75 +70,6 @@ namespace py = pybind11; USING_YOSYS_NAMESPACE -#ifdef EMSCRIPTEN -# include -# include -# include - -extern "C" int main(int, char**); -extern "C" void run(const char*); -extern "C" const char *errmsg(); -extern "C" const char *prompt(); - -int main(int argc, char **argv) -{ - EM_ASM( - if (ENVIRONMENT_IS_NODE) - { - FS.mkdir('/hostcwd'); - FS.mount(NODEFS, { root: '.' }, '/hostcwd'); - FS.mkdir('/hostfs'); - FS.mount(NODEFS, { root: '/' }, '/hostfs'); - } - ); - - mkdir("/work", 0777); - chdir("/work"); - log_files.push_back(stdout); - log_error_stderr = true; - yosys_banner(); - yosys_setup(); -#ifdef YOSYS_ENABLE_PYTHON - py::object sys = py::module_::import("sys"); - sys.attr("path").attr("append")(proc_self_dirname()); - sys.attr("path").attr("append")(proc_share_dirname()); -#endif - - if (argc == 2) - { - // Run the first argument as a script file - run_frontend(argv[1], "script"); - } -} - -void run(const char *command) -{ - int selSize = GetSize(yosys_get_design()->selection_stack); - try { - log_last_error = "Internal error (see JavaScript console for details)"; - run_pass(command); - log_last_error = ""; - } catch (...) { - while (GetSize(yosys_get_design()->selection_stack) > selSize) - yosys_get_design()->pop_selection(); - throw; - } -} - -const char *errmsg() -{ - return log_last_error.c_str(); -} - -const char *prompt() -{ - const char *p = create_prompt(yosys_get_design(), 0); - while (*p == '\n') p++; - return p; -} - -#else /* EMSCRIPTEN */ - #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) int yosys_history_offset = 0; std::string yosys_history_file; @@ -781,5 +712,3 @@ int main(int argc, char **argv) return 0; } - -#endif /* EMSCRIPTEN */ diff --git a/kernel/log.cc b/kernel/log.cc index 2121143a2..2f5a6350b 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -335,9 +335,6 @@ void log_suppressed() { [[noreturn]] static void log_error_with_prefix(std::string_view prefix, std::string str) { -#ifdef EMSCRIPTEN - auto backup_log_files = log_files; -#endif int bak_log_make_debug = log_make_debug; log_make_debug = 0; log_suppressed(); @@ -378,10 +375,7 @@ static void log_error_with_prefix(std::string_view prefix, std::string str) if (e && atoi(e)) abort(); -#ifdef EMSCRIPTEN - log_files = backup_log_files; - throw 0; -#elif defined(_MSC_VER) +#if defined(_MSC_VER) _exit(1); #else _Exit(1); @@ -679,9 +673,7 @@ void log_check_expected() log_warn_regexes.clear(); log("Expected %s pattern '%s' found !!!\n", kind, pattern); yosys_shutdown(); - #ifdef EMSCRIPTEN - throw 0; - #elif defined(_MSC_VER) + #if defined(_MSC_VER) _exit(0); #else _Exit(0); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 1a0da4774..167052340 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -550,7 +550,7 @@ std::string proc_self_dirname() shortpath[--i] = 0; return shortpath; } -#elif defined(EMSCRIPTEN) || defined(__wasm) +#elif defined(__wasm) std::string proc_self_dirname() { return "/"; @@ -588,7 +588,7 @@ std::string proc_self_dirname(void) #error "Don't know how to determine process executable base path!" #endif -#if defined(EMSCRIPTEN) || defined(__wasm) +#if defined(__wasm) void init_share_dirname() { yosys_share_dirname = "/share/"; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index ea82ff908..f7a5bf8f7 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -158,7 +158,6 @@ struct ExecPass : public Pass { int status = 0; int retval = 0; -#ifndef EMSCRIPTEN FILE *f = popen(cmd.c_str(), "r"); if (f == nullptr) log_cmd_error("errno %d after popen() returned NULL.\n", errno); @@ -183,7 +182,6 @@ struct ExecPass : public Pass { } } status = pclose(f); -#endif if(WIFEXITED(status)) { retval = WEXITSTATUS(status); From 6a2ed9075fc7b3d212289a32eac7f72469c48205 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 Jun 2026 10:14:13 +0200 Subject: [PATCH 13/82] Removed YosysJS related files --- misc/yosysjs/demo01.html | 197 ------------------------ misc/yosysjs/demo02.html | 103 ------------- misc/yosysjs/demo03.html | 103 ------------- misc/yosysjs/yosysjs.js | 312 --------------------------------------- misc/yosysjs/yosyswrk.js | 63 -------- 5 files changed, 778 deletions(-) delete mode 100644 misc/yosysjs/demo01.html delete mode 100644 misc/yosysjs/demo02.html delete mode 100644 misc/yosysjs/demo03.html delete mode 100644 misc/yosysjs/yosysjs.js delete mode 100644 misc/yosysjs/yosyswrk.js diff --git a/misc/yosysjs/demo01.html b/misc/yosysjs/demo01.html deleted file mode 100644 index 3f9f737e9..000000000 --- a/misc/yosysjs/demo01.html +++ /dev/null @@ -1,197 +0,0 @@ - - YosysJS Example Application #01 - - -

YosysJS Example Application #01

-
[ load example ]
- -
-

Loading...
- - - diff --git a/misc/yosysjs/demo02.html b/misc/yosysjs/demo02.html deleted file mode 100644 index 9191db98d..000000000 --- a/misc/yosysjs/demo02.html +++ /dev/null @@ -1,103 +0,0 @@ - - YosysJS Example Application #02 - - - -

YosysJS Example Application #02

-

- - - -

- - - - diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html deleted file mode 100644 index c2ca40ef5..000000000 --- a/misc/yosysjs/demo03.html +++ /dev/null @@ -1,103 +0,0 @@ - -YosysJS Example Application #02 - - - - - - -

-

YosysJS Example Application #03

- Your mission: Create a behavioral Verilog model for the following circuit: -

-

- - diff --git a/misc/yosysjs/yosysjs.js b/misc/yosysjs/yosysjs.js deleted file mode 100644 index ea98c9b51..000000000 --- a/misc/yosysjs/yosysjs.js +++ /dev/null @@ -1,312 +0,0 @@ -var YosysJS = new function() { - this.script_element = document.currentScript; - this.viz_element = undefined; - this.viz_ready = true; - - this.url_prefix = this.script_element.src.replace(/[^/]+$/, '') - - this.load_viz = function() { - if (this.viz_element) - return; - - this.viz_element = document.createElement('iframe') - this.viz_element.style.display = 'none' - document.body.appendChild(this.viz_element); - - this.viz_element.contentWindow.document.open(); - this.viz_element.contentWindow.document.write('