Merge remote-tracking branch 'upstream' into merge3

tests/opt/opt_balance_tree.ys

@@ -1031,11 +1031,11 @@ module top (
   wire [1:0] low_bits;
   wire [2:0] mid_bits;
   wire [1:0] high_bits;
-  
+
   assign low_bits = data_in[1:0];
   assign mid_bits = data_in[4:2];
   assign high_bits = data_in[7:6];
-  
+
   assign result = {1'b0, low_bits} + {1'b0, mid_bits} + {3'b0, high_bits} + {2'b0, a} + {2'b0, b} + {2'b0, c};
 endmodule
 EOF
@@ -1065,7 +1065,7 @@ module top (
   output wire [4:0] out2
 );
   wire [3:0] sum1, sum2;
-  
+
   assign sum1 = a + b;
   assign sum2 = c + d;
   assign out1 = sum1 + sum2;
@@ -1097,7 +1097,7 @@ module top (
   output wire [5:0] result
 );
   wire [4:0] sum1, sum2;
-  
+
   assign sum1 = a + b + a;  // 'a' appears twice
   assign sum2 = a + c;      // 'a' appears again
   assign result = sum1 + sum2;  // Final sum includes 'a' three times total
@@ -1134,7 +1134,7 @@ module top (
 );
   wire [4:0] partial1, partial2;
   wire [5:0] intermediate;
-  
+
   assign partial1 = a + c;
   assign partial2 = d + e + c;  // 'c' used twice
   assign intermediate = partial1 + partial2;
@@ -1199,7 +1199,7 @@ module top (
   output wire [6:0] result
 );
   wire [6:0] sum_part, diff_part;
-  
+
   assign sum_part = a + b + c;
   assign diff_part = d - e + f;  // Mix of add and subtract
   assign result = sum_part + diff_part;
@@ -1230,7 +1230,7 @@ module top (
   output wire signed [6:0] result  // Signed output
 );
   wire signed [4:0] intermediate1, intermediate2;
-  
+
   assign intermediate1 = $signed(a) + $signed(b);  // Convert to signed
   assign intermediate2 = $signed(c) + $signed(d);  // Convert to signed
   assign result = intermediate1 + intermediate2;   // Signed addition
@@ -1262,7 +1262,7 @@ module top (
   output wire signed [7:0] result  // Signed output
 );
   wire signed [5:0] sum_signed, sum_unsigned;
-  
+
   assign sum_signed = a + b;                    // Signed + Signed
   assign sum_unsigned = $signed({1'b0, c}) + $signed({1'b0, d});  // Force unsigned to signed safely
   assign result = sum_signed + sum_unsigned;   // Mixed result
@@ -1290,7 +1290,7 @@ design -reset
 read_verilog <<EOF
 module top (
   input wire signed [2:0] narrow_a,     // 3-bit signed
-  input wire signed [4:0] wide_b,       // 5-bit signed  
+  input wire signed [4:0] wide_b,       // 5-bit signed
   input wire [3:0] unsigned_c,          // 4-bit unsigned
   input wire signed [3:0] signed_d,     // 4-bit signed
   output wire signed [8:0] result       // Wide signed output
@@ -1357,11 +1357,11 @@ module top (
 );
   wire signed [8:0] sum_full;
   wire signed [6:0] sum_high, sum_low;
-  
+
   assign sum_full = data_a + data_b;
   assign sum_high = data_a[7:2] + data_b[7:2];           // High bits (signed)
   assign sum_low = $signed({1'b0, data_a[5:0]}) + $signed({1'b0, data_b[5:0]});  // Low bits as unsigned->signed
-  
+
   // Combine with unsigned offset
   assign result = sum_full + $signed({6'b0, unsigned_offset});
 endmodule
@@ -1395,17 +1395,17 @@ module top (
 );
   wire signed [5:0] extended_base;
   wire signed [6:0] offset_sum;
-  
+
   // Conditional sign extension based on input
-  assign extended_base = extend_sign ? 
+  assign extended_base = extend_sign ?
     {{1{base_val[4]}}, base_val} :     // Sign extend
     {1'b0, base_val};                  // Zero extend
-  
+
   // Mix of signed and unsigned offsets
-  assign offset_sum = $signed({2'b0, pos_offset1}) + 
-                     $signed({2'b0, pos_offset2}) + 
+  assign offset_sum = $signed({2'b0, pos_offset1}) +
+                     $signed({2'b0, pos_offset2}) +
                      {{2{signed_offset[3]}}, signed_offset};
-  
+
   assign result = extended_base + offset_sum;
 endmodule
 EOF

tests/opt/opt_dff_qd.ys

@@ -47,4 +47,3 @@ select -assert-count 6 t:$_DFFE_??_
 select -assert-count 4 t:$_DLATCH_?_
 select -assert-count 4 t:$_SR_??_
 select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
-

tests/opt/opt_dff_srst.ys

@@ -110,4 +110,3 @@ select -assert-count 2 t:$_DFF_P_
 select -assert-count 4 t:$_DFFE_PP_
 
 design -reset
-

tests/opt/opt_expr.ys

@@ -374,4 +374,4 @@ EOF
 
 scratchpad -set opt.did_something false
 opt_expr
-scratchpad -assert opt.did_something false
+scratchpad -assert opt.did_something false

tests/opt/opt_expr_mux_undef.ys

@@ -287,4 +287,3 @@ select -assert-none t:$_MUX16_
 select -assert-count 1 o:out %ci*
 
 ##########
-

tests/opt/opt_expr_sub_not.ys

@@ -0,0 +1,100 @@
+# Rewrite (2^k-1)-x into ~x when x is known to be smaller than 2^k
+
+read_verilog -icells <<EOT
+module test(input [3:0] b, output [3:0] y);
+$sub #(
+	.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) sub (
+	.A(4'hf), .B(b), .Y(y),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+
+design -load postopt
+select -assert-count 1 t:$not
+select -assert-none t:$sub
+select -assert-none t:$not t:* %D
+
+design -reset
+
+read_verilog -icells <<EOT
+module test(input [1:0] b, output [3:0] y);
+$sub #(
+	.A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) sub (
+	.A(4'd3), .B(b), .Y(y),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+
+design -load postopt
+select -assert-count 1 t:$not
+select -assert-none t:$sub
+
+design -reset
+
+read_verilog -icells <<EOT
+module test(input [3:0] b, output [3:0] y);
+$sub #(
+	.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) sub (
+	.A(4'b1011), .B(b), .Y(y),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+
+design -load postopt
+select -assert-none t:$not
+
+design -reset
+
+read_verilog -icells <<EOT
+module test(input [3:0] b, output [3:0] y);
+$sub #(
+	.A_WIDTH(2), .B_WIDTH(4), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) sub (
+	.A(2'b11), .B(b), .Y(y),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+
+design -load postopt
+select -assert-none t:$not
+
+design -reset
+
+read_verilog <<EOT
+module test(input [1:0] sel, input [0:3] data, output out);
+assign out = data[sel];
+endmodule
+EOT
+
+equiv_opt -assert opt -full
+
+design -load postopt
+select -assert-none t:$sub t:$add t:$alu
+
+design -reset
+
+read_verilog <<EOT
+module test(input sel, input [0:1] data, output out);
+assign out = data[sel];
+endmodule
+EOT
+
+equiv_opt -assert opt -full
+
+design -load postopt
+select -assert-none t:$sub t:$add t:$alu

tests/opt/opt_merge_properties.ys

@@ -13,4 +13,3 @@ chformal -lower
 clean
 opt_merge
 select -assert-count 2 t:$cover
-

tests/opt/opt_share_bug2538.ys

@@ -17,4 +17,3 @@ EOT
 proc
 alumacc
 equiv_opt -assert opt_share
-