Merge remote-tracking branch 'upstream' into merge3

tests/arch/analogdevices/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 2 t:RBRAM2
-

tests/arch/analogdevices/asym_ram_sdp_read_wider.v

@@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 	parameter WIDTHA = 4;
 	parameter SIZEA = 1024;
 	parameter ADDRWIDTHA = 10;
-	
+
 	parameter WIDTHB = 16;
 	parameter SIZEB = 256;
 	parameter ADDRWIDTHB = 8;

tests/arch/analogdevices/attributes_test.ys

@@ -4,7 +4,7 @@ hierarchy -top block_ram
 synth_analogdevices -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 # select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive.
- 
+
 # Check that distributed memory without parameters is not modified
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad
 cd distributed_ram # Constrain all select calls below inside the top module
 select -assert-count 8 t:RAMS64X1
 select -assert-count 8 t:FFRE
- 
+
 # Set ram_style distributed to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 64 t:RAMS64X1
 select -assert-count 4 t:FFRE
- 
+
 # Set synthesis, logic_block to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:*
 synth_analogdevices -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 0 t:RBRAM2
- 
+
 # Set ram_style block to a distributed memory; will be implemented as blockram
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v

tests/arch/analogdevices/blockram.ys

@@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
 synth_analogdevices -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
@@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set logic_block 1 m:memory
 synth_analogdevices -top sync_ram_sdp -noiopad
 cd sync_ram_sdp

tests/arch/analogdevices/bug1598.ys

@@ -3,14 +3,14 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc
-equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices 
+equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices

tests/arch/analogdevices/dffs.ys

@@ -38,4 +38,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:FFRE
 select -assert-none t:FFRE %% t:* %D
-

tests/arch/analogdevices/dsp_abc9.ys

@@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P);
 assign P = A * B;
 endmodule
 EOT
-synth_analogdevices 
+synth_analogdevices
 techmap -autoproc -wb -map +/analogdevices/cells_sim.v
 opt -full -fine
 select -assert-count 2 t:$mul
@@ -34,9 +34,8 @@ EOT
 async2sync
 techmap -map +/analogdevices/dsp_map.v
 verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
-synth_analogdevices 
+synth_analogdevices
 techmap -autoproc -wb -map +/analogdevices/cells_sim.v
 opt -full -fine
 select -assert-count 0 t:* t:$assert %d
 sat -verify -prove-asserts
-

tests/arch/common/blockram.v

@@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp
 
 
 module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
-   (input  wire                      clk_a, clk_b, 
+   (input  wire                      clk_a, clk_b,
     input  wire                      write_enable_a, write_enable_b,
     input  wire                      read_enable_a, read_enable_b,
     input  wire  [DATA_WIDTH-1:0]    write_data_a, write_data_b,
@@ -325,4 +325,3 @@ module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
     );
 
 endmodule // double_sync_ram_tdp
-

tests/arch/common/fsm.v

@@ -19,7 +19,7 @@
             state <=  #1  IDLE;
             gnt_0 <= 0;
             gnt_1 <= 0;
-          end 
+          end
           else
             case(state)
               IDLE :  if (req_0 == 1'b1) begin

tests/arch/common/memory_attributes/attributes_test.v

@@ -85,4 +85,3 @@ module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
 
    assign data_out = data_out_r;
 endmodule // distributed_ram
-

tests/arch/common/shifter.v

@@ -13,5 +13,5 @@ module top(out, clk, in);
 	begin
 		out    <= out >> 1;
 		out[7] <= in;
-	end    
+	end
 endmodule

tests/arch/ecp5/add_sub.ys

@@ -9,4 +9,3 @@ select -assert-max 26 t:LUT4
 select -assert-count 10 t:PFUMX
 select -assert-count 6 t:L6MUX21
 select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
-

tests/arch/ecp5/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/ecp5/bug1836.mem

@@ -1,32 +1,32 @@
-0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1,
-0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10,
-0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a,
-0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842,
-0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6,
-0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504,
-0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3,
-0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5,
-0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d,
-0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b,
-0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23,
-0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3,
-0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3,
-0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de,
-0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b,
-0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324,
-0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e,
-0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef,
-0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85,
-0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd,
-0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759,
-0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb,
-0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c,
-0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa,
-0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2,
-0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894,
-0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc,
-0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c,
-0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c,
-0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21,
-0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4,
-0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb,
+0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1,
+0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10,
+0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a,
+0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842,
+0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6,
+0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504,
+0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3,
+0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5,
+0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d,
+0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b,
+0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23,
+0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3,
+0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3,
+0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de,
+0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b,
+0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324,
+0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e,
+0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef,
+0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85,
+0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd,
+0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759,
+0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb,
+0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c,
+0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa,
+0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2,
+0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894,
+0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc,
+0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c,
+0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c,
+0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21,
+0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4,
+0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb,

tests/arch/ecp5/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
+select -assert-none t:TRELLIS_FF %% t:* %D

tests/arch/ecp5/memories.ys

@@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
 hierarchy -top sync_ram_tdp
 synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
-select -assert-count 1 t:DP16KD 
+select -assert-count 1 t:DP16KD
 select -assert-none t:LUT4

tests/arch/ecp5/shifter.ys

@@ -5,6 +5,6 @@ flatten
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
- 
+
 select -assert-count 8 t:TRELLIS_FF
 select -assert-none t:TRELLIS_FF %% t:* %D

tests/arch/efinix/add_sub.ys

@@ -7,4 +7,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:EFX_ADD
 select -assert-count 4  t:EFX_LUT4
 select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
-

tests/arch/gowin/add_sub.ys

@@ -10,4 +10,3 @@ select -assert-count 8 t:IBUF
 select -assert-count 1 t:GND
 select -assert-count 1 t:VCC
 select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
-

tests/arch/gowin/compare.ys

@@ -5,5 +5,3 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 5 t:ALU
-
-

tests/arch/gowin/tribuf.ys

@@ -11,4 +11,4 @@ cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:TBUF
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:IBUF
-select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
+select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D

tests/arch/ice40/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:SB_LUT4
 select -assert-count 6 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
-

tests/arch/ice40/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/ice40/bug1626.ys

@@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth
     attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
     switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
       case 1'1
-      case 
+      case
         attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
         switch \ahbls_hready
           case 1'1
             attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
             switch \ahbls_htrans [1]
               case 1'1
-              case 
+              case
             end
-          case 
+          case
             attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
             switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
               case 1'1
-              case 
+              case
             end
         end
     end

tests/arch/ice40/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D

tests/arch/ice40/ice40_dsp_const.ys

@@ -75,7 +75,7 @@ EOT
 techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
 
 async2sync
-equiv_make top ref equiv 
-select -assert-any -module equiv t:$equiv 
-equiv_induct 
+equiv_make top ref equiv
+select -assert-any -module equiv t:$equiv
+equiv_induct
 equiv_status -assert

tests/arch/ice40/spram.v

@@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1;
 input clk;
 input write_enable, read_enable;
 input [DATA_WIDTH - 1 : 0] write_data;
-input [ADDR_WIDTH - 1 : 0] addr; 
+input [ADDR_WIDTH - 1 : 0] addr;
 output [DATA_WIDTH - 1 : 0] read_data;
 
 (* ram_style = "huge" *)

tests/arch/intel_alm/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 stat
 select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
-

tests/arch/intel_alm/adffs.ys

@@ -45,4 +45,3 @@ select -assert-count 1 t:MISTRAL_FF
 select -assert-count 2 t:MISTRAL_NOT
 
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
-

tests/arch/intel_alm/blockram.ys

@@ -5,4 +5,3 @@ cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
-

tests/arch/intel_alm/counter.ys

@@ -10,4 +10,3 @@ select -assert-count 2 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/dffs.ys

@@ -18,4 +18,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/fsm.ys

@@ -19,4 +19,3 @@ select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
 select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/logic.ys

@@ -9,4 +9,3 @@ select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 6 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
-

tests/arch/intel_alm/lutram.ys

@@ -37,4 +37,3 @@ select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
-

tests/arch/intel_alm/mul.ys

@@ -32,4 +32,3 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:MISTRAL_MUL27X27
 select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
-

tests/arch/intel_alm/mux.ys

@@ -42,4 +42,3 @@ select -assert-max 1 t:MISTRAL_ALUT3
 select -assert-max 2 t:MISTRAL_ALUT5
 select -assert-max 5 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/shifter.ys

@@ -7,4 +7,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/tribuf.ys

@@ -10,4 +10,3 @@ cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-

tests/arch/microchip/.gitignore

@@ -1,2 +1 @@
 *.vm
-

tests/arch/microchip/dff.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -73,4 +73,4 @@ synth_microchip -top dffs -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CLKBUF
 select -assert-count 1 t:CFG1
-select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
+select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

tests/arch/microchip/dff_opt.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -39,4 +39,4 @@ synth_microchip -top dff_opt -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
 select -assert-count 1 t:CLKBUF
-select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

tests/arch/microchip/dsp.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -120,7 +120,7 @@ output reg cout;
 input [n:0] a;
 input [n:0] b;
 input [n-1:0] c;
-	always @(*) 
+	always @(*)
 	begin
 		{cout,out} = a * b + c;
 	end

tests/arch/microchip/mult.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

tests/arch/microchip/ram_SDP.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -27,7 +27,7 @@ output reg [d_width-1:0] q;
 reg [d_width-1:0] mem [mem_depth-1:0];
 
 always @(posedge clk) begin
-	if (we) begin 
+	if (we) begin
 		mem[waddr] <= data;
 	end else begin
 		q <= mem[waddr];
@@ -47,4 +47,4 @@ hierarchy -top sync_ram_sdp
 chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
 synth_microchip -top sync_ram_sdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/ram_TDP.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
 always @ (posedge clka)
 begin
 	addra_reg <= addra;
-			
+
 	if(wea) begin
 		mem[addra] <= dataina;
 		qa <= dataina;
@@ -61,4 +61,4 @@ chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_tdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 2 t:CFG1
-select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

tests/arch/microchip/reduce.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -25,4 +25,3 @@ EOT
 synth_microchip -top reduce -family polarfire -noiopad
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
-

tests/arch/microchip/simple_ram.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -19,4 +19,4 @@ hierarchy -top sync_ram_sp
 chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_sp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/uram_ar.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0];
 assign q = mem[waddr];
 
 always @(posedge clk) begin
-	if (we) 
+	if (we)
 		mem[waddr] <= data;
 
 end

tests/arch/microchip/uram_sr.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout);
 	end
 
 	always@(posedge clk) begin
-		raddr_reg <= raddr; 
+		raddr_reg <= raddr;
 		if(wr)
 			mem[waddr]<= din;
 	end

tests/arch/microchip/widemux.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -38,4 +38,4 @@ equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 3 t:CFG3
-select -assert-none t:CFG3 %% t:* %D
+select -assert-none t:CFG3 %% t:* %D

tests/arch/nanoxplore/meminit.v

@@ -31,7 +31,7 @@ always @(posedge clk) begin
         read_addr <= counter;
         read_val <= mem[counter];
     end else begin
-        did_read <= 1'b0; 
+        did_read <= 1'b0;
     end
 
     if (!done)

tests/arch/nanoxplore/meminit.ys

@@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36
 prep
 opt_dff
 prep -rdff
-synth_nanoxplore 
+synth_nanoxplore
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
 read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18
 prep
 opt_dff
 prep -rdff
-synth_nanoxplore 
+synth_nanoxplore
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
 read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18
 prep
 opt_dff
 prep -rdff
-synth_nanoxplore 
+synth_nanoxplore
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
 read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v

tests/arch/quicklogic/qlf_k6n10f/dffs.ys

@@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd my_dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:sdffsre
-select -assert-none t:sdffsre %% t:* %D 
+select -assert-none t:sdffsre %% t:* %D
 
 design -load read
 hierarchy -top my_dffe
@@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd my_dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:sdffsre
-select -assert-none t:sdffsre %% t:* %D 
+select -assert-none t:sdffsre %% t:* %D

tests/arch/quicklogic/qlf_k6n10f/mem_tb.v

@@ -46,7 +46,7 @@ initial begin
 	end
 
 	`MEM_TEST_VECTOR
-	
+
 end
 
 
@@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
 always @(posedge clk) begin
 	if (i < VECTORLEN-1) begin
 		if (i > 0) begin
-			if($past(rce_a)) 
+			if($past(rce_a))
 				assert(rq_a == rq_a_e);
 			if($past(rce_b))
 				assert(rq_b == rq_b_e);

tests/arch/quicklogic/qlf_k6n10f/meminit.v

@@ -31,7 +31,7 @@ always @(posedge clk) begin
         read_addr <= counter;
         read_val <= mem[counter];
     end else begin
-        did_read <= 1'b0; 
+        did_read <= 1'b0;
     end
 
     if (!done)

tests/arch/xilinx/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_xilinx -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 1 t:RAMB18E1
-

tests/arch/xilinx/asym_ram_sdp_read_wider.v

@@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 	parameter WIDTHA = 4;
 	parameter SIZEA = 1024;
 	parameter ADDRWIDTHA = 10;
-	
+
 	parameter WIDTHB = 16;
 	parameter SIZEB = 256;
 	parameter ADDRWIDTHB = 8;
@@ -69,4 +69,4 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 		end
 	end
 	assign doB = readB;
-endmodule
+endmodule

tests/arch/xilinx/asym_ram_sdp_write_wider.v

@@ -68,4 +68,4 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
 			end
 		end
 	end
-endmodule
+endmodule

tests/arch/xilinx/attributes_test.ys

@@ -4,7 +4,7 @@ hierarchy -top block_ram
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAMB18E1
- 
+
 # Check that distributed memory without parameters is not modified
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -12,7 +12,7 @@ hierarchy -top distributed_ram
 synth_xilinx -top distributed_ram -noiopad
 cd distributed_ram # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAM32M
- 
+
 # Set ram_style distributed to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 16 t:RAM256X1S
- 
+
 # Set synthesis, logic_block to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 0 t:RAMB18E1
- 
+
 # Set ram_style block to a distributed memory; will be implemented as blockram
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v

tests/arch/xilinx/blockram.ys

@@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
@@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set logic_block 1 m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp

tests/arch/xilinx/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/xilinx/dffs.ys

@@ -42,4 +42,3 @@ cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-none t:BUFG t:FDRE %% t:* %D
-

tests/arch/xilinx/dsp_cascade.ys

@@ -87,4 +87,3 @@ select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)
 select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
-

tests/arch/xilinx/dynamic_upto_select.ys

@@ -0,0 +1,19 @@
+# https://github.com/YosysHQ/yosys/issues/892
+
+read_verilog <<EOT
+module top (input clk, sel, di, output do);
+	reg [0:1] data [0:0];
+	always @(posedge clk)
+		data[0] <= {di, data[0][0]};
+	assign do = data[0][sel];
+endmodule
+EOT
+
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
+design -load postopt
+
+select -assert-count 1 t:BUFG
+select -assert-count 2 t:FDRE
+select -assert-count 1 t:LUT3
+select -assert-none t:BUFG t:FDRE t:LUT3 %% t:* %D

tests/arch/xilinx/xilinx_srl.v

@@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 wire clk = C ^ CLKPOL;
 always @(posedge C)
-    if (E) 
+    if (E)
         r <= { r[DEPTH-2:0], D };
 assign Q = r[L];
 endmodule