Merge remote-tracking branch 'upstream' into merge3

tests/Makefile

@@ -75,6 +75,7 @@ MK_TEST_DIRS += ./memories
 MK_TEST_DIRS += ./aiger
 MK_TEST_DIRS += ./alumacc
 MK_TEST_DIRS += ./check_mem
+MK_TEST_DIRS += ./write_verilog
 MK_TEST_DIRS += ./silimate
 
 all: vanilla-test

tests/arch/analogdevices/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 2 t:RBRAM2
-

tests/arch/analogdevices/asym_ram_sdp_read_wider.v

@@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 	parameter WIDTHA = 4;
 	parameter SIZEA = 1024;
 	parameter ADDRWIDTHA = 10;
-	
+
 	parameter WIDTHB = 16;
 	parameter SIZEB = 256;
 	parameter ADDRWIDTHB = 8;

tests/arch/analogdevices/attributes_test.ys

@@ -4,7 +4,7 @@ hierarchy -top block_ram
 synth_analogdevices -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 # select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive.
- 
+
 # Check that distributed memory without parameters is not modified
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad
 cd distributed_ram # Constrain all select calls below inside the top module
 select -assert-count 8 t:RAMS64X1
 select -assert-count 8 t:FFRE
- 
+
 # Set ram_style distributed to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 64 t:RAMS64X1
 select -assert-count 4 t:FFRE
- 
+
 # Set synthesis, logic_block to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:*
 synth_analogdevices -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 0 t:RBRAM2
- 
+
 # Set ram_style block to a distributed memory; will be implemented as blockram
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v

tests/arch/analogdevices/blockram.ys

@@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
 synth_analogdevices -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
@@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set logic_block 1 m:memory
 synth_analogdevices -top sync_ram_sdp -noiopad
 cd sync_ram_sdp

tests/arch/analogdevices/bug1598.ys

@@ -3,14 +3,14 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc
-equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices 
+equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices

tests/arch/analogdevices/dffs.ys

@@ -38,4 +38,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:FFRE
 select -assert-none t:FFRE %% t:* %D
-

tests/arch/analogdevices/dsp_abc9.ys

@@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P);
 assign P = A * B;
 endmodule
 EOT
-synth_analogdevices 
+synth_analogdevices
 techmap -autoproc -wb -map +/analogdevices/cells_sim.v
 opt -full -fine
 select -assert-count 2 t:$mul
@@ -34,9 +34,8 @@ EOT
 async2sync
 techmap -map +/analogdevices/dsp_map.v
 verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
-synth_analogdevices 
+synth_analogdevices
 techmap -autoproc -wb -map +/analogdevices/cells_sim.v
 opt -full -fine
 select -assert-count 0 t:* t:$assert %d
 sat -verify -prove-asserts
-

tests/arch/common/blockram.v

@@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp
 
 
 module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
-   (input  wire                      clk_a, clk_b, 
+   (input  wire                      clk_a, clk_b,
     input  wire                      write_enable_a, write_enable_b,
     input  wire                      read_enable_a, read_enable_b,
     input  wire  [DATA_WIDTH-1:0]    write_data_a, write_data_b,
@@ -325,4 +325,3 @@ module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
     );
 
 endmodule // double_sync_ram_tdp
-

tests/arch/common/fsm.v

@@ -19,7 +19,7 @@
             state <=  #1  IDLE;
             gnt_0 <= 0;
             gnt_1 <= 0;
-          end 
+          end
           else
             case(state)
               IDLE :  if (req_0 == 1'b1) begin

tests/arch/common/memory_attributes/attributes_test.v

@@ -85,4 +85,3 @@ module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
 
    assign data_out = data_out_r;
 endmodule // distributed_ram
-

tests/arch/common/shifter.v

@@ -13,5 +13,5 @@ module top(out, clk, in);
 	begin
 		out    <= out >> 1;
 		out[7] <= in;
-	end    
+	end
 endmodule

tests/arch/ecp5/add_sub.ys

@@ -9,4 +9,3 @@ select -assert-max 26 t:LUT4
 select -assert-count 10 t:PFUMX
 select -assert-count 6 t:L6MUX21
 select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
-

tests/arch/ecp5/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/ecp5/bug1836.mem

@@ -1,32 +1,32 @@
-0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1,
-0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10,
-0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a,
-0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842,
-0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6,
-0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504,
-0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3,
-0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5,
-0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d,
-0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b,
-0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23,
-0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3,
-0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3,
-0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de,
-0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b,
-0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324,
-0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e,
-0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef,
-0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85,
-0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd,
-0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759,
-0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb,
-0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c,
-0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa,
-0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2,
-0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894,
-0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc,
-0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c,
-0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c,
-0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21,
-0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4,
-0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb,
+0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1,
+0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10,
+0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a,
+0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842,
+0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6,
+0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504,
+0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3,
+0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5,
+0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d,
+0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b,
+0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23,
+0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3,
+0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3,
+0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de,
+0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b,
+0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324,
+0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e,
+0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef,
+0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85,
+0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd,
+0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759,
+0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb,
+0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c,
+0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa,
+0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2,
+0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894,
+0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc,
+0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c,
+0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c,
+0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21,
+0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4,
+0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb,

tests/arch/ecp5/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
+select -assert-none t:TRELLIS_FF %% t:* %D

tests/arch/ecp5/memories.ys

@@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
 hierarchy -top sync_ram_tdp
 synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
-select -assert-count 1 t:DP16KD 
+select -assert-count 1 t:DP16KD
 select -assert-none t:LUT4

tests/arch/ecp5/shifter.ys

@@ -5,6 +5,6 @@ flatten
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
- 
+
 select -assert-count 8 t:TRELLIS_FF
 select -assert-none t:TRELLIS_FF %% t:* %D

tests/arch/efinix/add_sub.ys

@@ -7,4 +7,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:EFX_ADD
 select -assert-count 4  t:EFX_LUT4
 select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
-

tests/arch/gowin/add_sub.ys

@@ -10,4 +10,3 @@ select -assert-count 8 t:IBUF
 select -assert-count 1 t:GND
 select -assert-count 1 t:VCC
 select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
-

tests/arch/gowin/compare.ys

@@ -5,5 +5,3 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 5 t:ALU
-
-

tests/arch/gowin/tribuf.ys

@@ -11,4 +11,4 @@ cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:TBUF
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:IBUF
-select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
+select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D

tests/arch/ice40/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:SB_LUT4
 select -assert-count 6 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
-

tests/arch/ice40/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/ice40/bug1626.ys

@@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth
     attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
     switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
       case 1'1
-      case 
+      case
         attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
         switch \ahbls_hready
           case 1'1
             attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
             switch \ahbls_htrans [1]
               case 1'1
-              case 
+              case
             end
-          case 
+          case
             attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
             switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
               case 1'1
-              case 
+              case
             end
         end
     end

tests/arch/ice40/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D

tests/arch/ice40/ice40_dsp_const.ys

@@ -75,7 +75,7 @@ EOT
 techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
 
 async2sync
-equiv_make top ref equiv 
-select -assert-any -module equiv t:$equiv 
-equiv_induct 
+equiv_make top ref equiv
+select -assert-any -module equiv t:$equiv
+equiv_induct
 equiv_status -assert

tests/arch/ice40/spram.v

@@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1;
 input clk;
 input write_enable, read_enable;
 input [DATA_WIDTH - 1 : 0] write_data;
-input [ADDR_WIDTH - 1 : 0] addr; 
+input [ADDR_WIDTH - 1 : 0] addr;
 output [DATA_WIDTH - 1 : 0] read_data;
 
 (* ram_style = "huge" *)

tests/arch/intel_alm/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 stat
 select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
-

tests/arch/intel_alm/adffs.ys

@@ -45,4 +45,3 @@ select -assert-count 1 t:MISTRAL_FF
 select -assert-count 2 t:MISTRAL_NOT
 
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
-

tests/arch/intel_alm/blockram.ys

@@ -5,4 +5,3 @@ cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
-

tests/arch/intel_alm/counter.ys

@@ -10,4 +10,3 @@ select -assert-count 2 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/dffs.ys

@@ -18,4 +18,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/fsm.ys

@@ -19,4 +19,3 @@ select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
 select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/logic.ys

@@ -9,4 +9,3 @@ select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 6 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
-

tests/arch/intel_alm/lutram.ys

@@ -37,4 +37,3 @@ select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
-

tests/arch/intel_alm/mul.ys

@@ -32,4 +32,3 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:MISTRAL_MUL27X27
 select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
-

tests/arch/intel_alm/mux.ys

@@ -42,4 +42,3 @@ select -assert-max 1 t:MISTRAL_ALUT3
 select -assert-max 2 t:MISTRAL_ALUT5
 select -assert-max 5 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/shifter.ys

@@ -7,4 +7,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/tribuf.ys

@@ -10,4 +10,3 @@ cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-

tests/arch/microchip/.gitignore

@@ -1,2 +1 @@
 *.vm
-

tests/arch/microchip/dff.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -73,4 +73,4 @@ synth_microchip -top dffs -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CLKBUF
 select -assert-count 1 t:CFG1
-select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
+select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

tests/arch/microchip/dff_opt.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -39,4 +39,4 @@ synth_microchip -top dff_opt -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
 select -assert-count 1 t:CLKBUF
-select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

tests/arch/microchip/dsp.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -120,7 +120,7 @@ output reg cout;
 input [n:0] a;
 input [n:0] b;
 input [n-1:0] c;
-	always @(*) 
+	always @(*)
 	begin
 		{cout,out} = a * b + c;
 	end

tests/arch/microchip/mult.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

tests/arch/microchip/ram_SDP.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -27,7 +27,7 @@ output reg [d_width-1:0] q;
 reg [d_width-1:0] mem [mem_depth-1:0];
 
 always @(posedge clk) begin
-	if (we) begin 
+	if (we) begin
 		mem[waddr] <= data;
 	end else begin
 		q <= mem[waddr];
@@ -47,4 +47,4 @@ hierarchy -top sync_ram_sdp
 chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
 synth_microchip -top sync_ram_sdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/ram_TDP.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
 always @ (posedge clka)
 begin
 	addra_reg <= addra;
-			
+
 	if(wea) begin
 		mem[addra] <= dataina;
 		qa <= dataina;
@@ -61,4 +61,4 @@ chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_tdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 2 t:CFG1
-select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

tests/arch/microchip/reduce.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -25,4 +25,3 @@ EOT
 synth_microchip -top reduce -family polarfire -noiopad
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
-

tests/arch/microchip/simple_ram.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -19,4 +19,4 @@ hierarchy -top sync_ram_sp
 chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_sp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/uram_ar.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0];
 assign q = mem[waddr];
 
 always @(posedge clk) begin
-	if (we) 
+	if (we)
 		mem[waddr] <= data;
 
 end

tests/arch/microchip/uram_sr.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout);
 	end
 
 	always@(posedge clk) begin
-		raddr_reg <= raddr; 
+		raddr_reg <= raddr;
 		if(wr)
 			mem[waddr]<= din;
 	end

tests/arch/microchip/widemux.ys

@@ -1,11 +1,11 @@
 # ISC License
-# 
+#
 # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-# 
+#
 # Permission to use, copy, modify, and/or distribute this software for any
 # purpose with or without fee is hereby granted, provided that the above
 # copyright notice and this permission notice appear in all copies.
-# 
+#
 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -38,4 +38,4 @@ equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 3 t:CFG3
-select -assert-none t:CFG3 %% t:* %D
+select -assert-none t:CFG3 %% t:* %D

tests/arch/nanoxplore/meminit.v

@@ -31,7 +31,7 @@ always @(posedge clk) begin
         read_addr <= counter;
         read_val <= mem[counter];
     end else begin
-        did_read <= 1'b0; 
+        did_read <= 1'b0;
     end
 
     if (!done)

tests/arch/nanoxplore/meminit.ys

@@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36
 prep
 opt_dff
 prep -rdff
-synth_nanoxplore 
+synth_nanoxplore
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
 read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18
 prep
 opt_dff
 prep -rdff
-synth_nanoxplore 
+synth_nanoxplore
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
 read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18
 prep
 opt_dff
 prep -rdff
-synth_nanoxplore 
+synth_nanoxplore
 clean_zerowidth
 select -assert-none t:$mem_v2 t:$mem
 read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v

tests/arch/quicklogic/qlf_k6n10f/dffs.ys

@@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd my_dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:sdffsre
-select -assert-none t:sdffsre %% t:* %D 
+select -assert-none t:sdffsre %% t:* %D
 
 design -load read
 hierarchy -top my_dffe
@@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd my_dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:sdffsre
-select -assert-none t:sdffsre %% t:* %D 
+select -assert-none t:sdffsre %% t:* %D

tests/arch/quicklogic/qlf_k6n10f/mem_tb.v

@@ -46,7 +46,7 @@ initial begin
 	end
 
 	`MEM_TEST_VECTOR
-	
+
 end
 
 
@@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
 always @(posedge clk) begin
 	if (i < VECTORLEN-1) begin
 		if (i > 0) begin
-			if($past(rce_a)) 
+			if($past(rce_a))
 				assert(rq_a == rq_a_e);
 			if($past(rce_b))
 				assert(rq_b == rq_b_e);

tests/arch/quicklogic/qlf_k6n10f/meminit.v

@@ -31,7 +31,7 @@ always @(posedge clk) begin
         read_addr <= counter;
         read_val <= mem[counter];
     end else begin
-        did_read <= 1'b0; 
+        did_read <= 1'b0;
     end
 
     if (!done)

tests/arch/xilinx/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_xilinx -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 1 t:RAMB18E1
-

tests/arch/xilinx/asym_ram_sdp_read_wider.v

@@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 	parameter WIDTHA = 4;
 	parameter SIZEA = 1024;
 	parameter ADDRWIDTHA = 10;
-	
+
 	parameter WIDTHB = 16;
 	parameter SIZEB = 256;
 	parameter ADDRWIDTHB = 8;
@@ -69,4 +69,4 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 		end
 	end
 	assign doB = readB;
-endmodule
+endmodule

tests/arch/xilinx/asym_ram_sdp_write_wider.v

@@ -68,4 +68,4 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
 			end
 		end
 	end
-endmodule
+endmodule

tests/arch/xilinx/attributes_test.ys

@@ -4,7 +4,7 @@ hierarchy -top block_ram
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAMB18E1
- 
+
 # Check that distributed memory without parameters is not modified
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -12,7 +12,7 @@ hierarchy -top distributed_ram
 synth_xilinx -top distributed_ram -noiopad
 cd distributed_ram # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAM32M
- 
+
 # Set ram_style distributed to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 16 t:RAM256X1S
- 
+
 # Set synthesis, logic_block to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
@@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 0 t:RAMB18E1
- 
+
 # Set ram_style block to a distributed memory; will be implemented as blockram
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v

tests/arch/xilinx/blockram.ys

@@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
@@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
 setattr -set logic_block 1 m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp

tests/arch/xilinx/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/xilinx/dffs.ys

@@ -42,4 +42,3 @@ cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-none t:BUFG t:FDRE %% t:* %D
-

tests/arch/xilinx/dsp_cascade.ys

@@ -87,4 +87,3 @@ select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)
 select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
-

tests/arch/xilinx/dynamic_upto_select.ys

@@ -0,0 +1,19 @@
+# https://github.com/YosysHQ/yosys/issues/892
+
+read_verilog <<EOT
+module top (input clk, sel, di, output do);
+	reg [0:1] data [0:0];
+	always @(posedge clk)
+		data[0] <= {di, data[0][0]};
+	assign do = data[0][sel];
+endmodule
+EOT
+
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
+design -load postopt
+
+select -assert-count 1 t:BUFG
+select -assert-count 2 t:FDRE
+select -assert-count 1 t:LUT3
+select -assert-none t:BUFG t:FDRE t:LUT3 %% t:* %D

tests/arch/xilinx/xilinx_srl.v

@@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 wire clk = C ^ CLKPOL;
 always @(posedge C)
-    if (E) 
+    if (E)
         r <= { r[DEPTH-2:0], D };
 assign Q = r[L];
 endmodule

tests/arith_tree/arith_tree_42.ys

@@ -0,0 +1,122 @@
+read_verilog <<EOT
+module four_op_42(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy 42
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 0 t:$fa c:*emit_compressor_32* %i
+design -reset
+
+read_verilog <<EOT
+module four_op_fa(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy fa
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$fa c:*emit_compressor_42* %i
+select -assert-count 2 t:$fa c:*emit_compressor_32* %i
+design -reset
+
+read_verilog <<EOT
+module eight_op_42(
+	input [3:0] a, b, c, d, e, f, g, h,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy 42
+design -load postopt
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module sixteen_op_42(
+	input [3:0] a0, a1, a2, a3, a4, a5, a6, a7,
+	input [3:0] a8, a9, a10, a11, a12, a13, a14, a15,
+	output [3:0] y
+);
+	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
+	        + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy 42
+design -load postopt
+select -assert-count 14 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module five_op_42(
+	input [3:0] a, b, c, d, e,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy 42
+design -load postopt
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module six_op_42(
+	input [3:0] a, b, c, d, e, f,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy 42
+design -load postopt
+select -assert-count 4 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module seven_op_42(
+	input [3:0] a, b, c, d, e, f, g,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -strategy 42
+design -load postopt
+select -assert-count 5 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset

tests/arith_tree/arith_tree_alu_macc_equiv.ys

@@ -10,7 +10,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -28,7 +28,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -46,7 +46,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
@@ -64,7 +64,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -82,7 +82,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
@@ -100,8 +100,8 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
-design -reset
+design -reset

tests/arith_tree/arith_tree_defaults.ys

@@ -0,0 +1,76 @@
+# Idempotence
+read_verilog <<EOT
+module idem_add4(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+arith_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module idem_mac(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree
+stat
+arith_tree
+select -assert-count 1 t:$add
+select -assert-count 0 t:$macc
+select -assert-count 0 t:$macc_v2
+select -assert-count 0 t:$mul
+design -reset
+
+read_verilog <<EOT
+module default_smoke(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 0 t:$_AND_
+select -assert-min 0 t:$_XOR_
+design -reset
+
+read_verilog <<EOT
+module default_narrow(
+	input [14:0] a, b, c, d,
+	output [14:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
+design -reset

tests/arith_tree/arith_tree_edge_cases.ys

@@ -217,6 +217,25 @@ alumacc
 opt
 arith_tree
 opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-none t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module macc_mul_nofma(
+	input [7:0] a, b, c,
+	output [15:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree -no-fma
+opt_clean
 select -assert-none t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset
@@ -402,6 +421,25 @@ alumacc
 opt
 arith_tree
 opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-none t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module macc_mul_survives_nofma(
+	input [7:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a * b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree -no-fma
+opt_clean
 select -assert-none t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset

tests/arith_tree/arith_tree_equiv.ys

@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -24,7 +24,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -40,7 +40,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -56,7 +56,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
@@ -72,7 +72,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -90,7 +90,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -106,7 +106,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -122,7 +122,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
@@ -138,7 +138,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
@@ -154,7 +154,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -171,7 +171,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add

tests/arith_tree/arith_tree_final_adder.ys

@@ -0,0 +1,69 @@
+read_verilog <<EOT
+module final_auto_wide(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -final auto
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa
+select -assert-none t:$_AND_
+select -assert-none 1 t:$_XOR_
+design -reset
+
+read_verilog <<EOT
+module final_auto_narrow(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -final auto
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa
+select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
+design -reset
+
+read_verilog <<EOT
+module final_ripple(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
+design -reset
+
+read_verilog <<EOT
+module final_prefix_narrow(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt -assert arith_tree -final prefix
+design -load postopt
+select -assert-none t:$add
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
+design -reset

tests/arith_tree/arith_tree_fma.ys

@@ -0,0 +1,120 @@
+read_verilog <<EOT
+module fma_mul_only(
+	input [3:0] a, b,
+	output [7:0] y
+);
+	assign y = a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 1 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 0 t:$add
+select -assert-min 0 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_mac(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_dot2(
+	input [3:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a * b + c * d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_mac_sub(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b - c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_disabled(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree -no-fma
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset
+
+read_verilog <<EOT
+module fma_signed(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset

tests/arith_tree/arith_tree_signed_fma.ys

@@ -0,0 +1,135 @@
+read_verilog <<EOT
+module signed_mac(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mul(
+	input signed [3:0] a, b,
+	output signed [7:0] y
+);
+	assign y = a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 1 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 0 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_dot2(
+	input signed [3:0] a, b, c, d,
+	output signed [7:0] y
+);
+	assign y = a * b + c * d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_sub(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b - c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_negprod(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = c - a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_wide(
+	input signed [7:0] a, b,
+	input signed [15:0] c,
+	output signed [15:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_nofma(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt -assert arith_tree -no-fma
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset

tests/arith_tree/kogge_stone_equiv.ys

@@ -0,0 +1,67 @@
+# Verify that CompressorTree::emit_kogge_stone() is eq to the implementation in techlibs/common/choices/kogge-stone.v
+
+test_kogge_stone -width 1
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 2
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 3
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 4
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 5
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 7
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 8
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 16
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 17
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 32
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 33
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset

tests/asicworld/code_hdl_models_GrayCounter.v

@@ -6,19 +6,19 @@
 
 module GrayCounter
    #(parameter   COUNTER_WIDTH = 4)
-   
+
     (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,  //'Gray' code count output.
-    
+
      input wire                         Enable_in,  //Count enable.
      input wire                         Clear_in,   //Count reset.
-    
+
      input wire                         Clk);
 
     /////////Internal connections & variables///////
     reg    [COUNTER_WIDTH-1:0]         BinaryCount;
 
     /////////Code///////////////////////
-    
+
     always @ (posedge Clk)
         if (Clear_in) begin
             BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;  //Gray count begins @ '1' with
@@ -29,5 +29,5 @@ module GrayCounter
             GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
                               BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
         end
-    
+
 endmodule

tests/asicworld/code_hdl_models_arbiter.v

@@ -3,32 +3,32 @@
 // orginally coded by WD Peterson in VHDL.
 //----------------------------------------------------
 module arbiter (
-  clk,    
-  rst,    
-  req3,   
-  req2,   
-  req1,   
-  req0,   
-  gnt3,   
-  gnt2,   
-  gnt1,   
-  gnt0   
+  clk,
+  rst,
+  req3,
+  req2,
+  req1,
+  req0,
+  gnt3,
+  gnt2,
+  gnt1,
+  gnt0
 );
-// --------------Port Declaration----------------------- 
-input           clk;    
-input           rst;    
-input           req3;   
-input           req2;   
-input           req1;   
-input           req0;   
-output          gnt3;   
-output          gnt2;   
-output          gnt1;   
-output          gnt0;   
+// --------------Port Declaration-----------------------
+input           clk;
+input           rst;
+input           req3;
+input           req2;
+input           req1;
+input           req0;
+output          gnt3;
+output          gnt2;
+output          gnt1;
+output          gnt0;
 
 //--------------Internal Registers----------------------
-wire    [1:0]   gnt       ;   
-wire            comreq    ; 
+wire    [1:0]   gnt       ;
+wire            comreq    ;
 wire            beg       ;
 wire   [1:0]    lgnt      ;
 wire            lcomreq   ;
@@ -41,14 +41,14 @@ reg             lmask0    ;
 reg             lmask1    ;
 reg             ledge     ;
 
-//--------------Code Starts Here----------------------- 
+//--------------Code Starts Here-----------------------
 always @ (posedge clk)
 if (rst) begin
   lgnt0 <= 0;
   lgnt1 <= 0;
   lgnt2 <= 0;
   lgnt3 <= 0;
-end else begin                                     
+end else begin
   lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
         | (~lcomreq & ~lmask1 &  lmask0 & ~req3 & ~req2 &  req0)
         | (~lcomreq &  lmask1 & ~lmask0 & ~req3 &  req0)
@@ -69,18 +69,18 @@ end else begin
         | (~lcomreq &  lmask1 & ~lmask0 & req3)
         | (~lcomreq &  lmask1 &  lmask0 & req3  & ~req2 & ~req1 & ~req0)
         | ( lcomreq & lgnt3);
-end 
+end
 
 //----------------------------------------------------
 // lasmask state machine.
 //----------------------------------------------------
 assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
 always @ (posedge clk)
-begin                                     
+begin
   lasmask <= (beg & ~ledge & ~lasmask);
-  ledge   <= (beg & ~ledge &  lasmask) 
+  ledge   <= (beg & ~ledge &  lasmask)
           |  (beg &  ledge & ~lasmask);
-end 
+end
 
 //----------------------------------------------------
 // comreq logic.
@@ -108,7 +108,7 @@ end else if(lasmask) begin
 end else begin
   lmask1 <= lmask1;
   lmask0 <= lmask0;
-end 
+end
 
 assign comreq = lcomreq;
 assign gnt    = lgnt;

tests/asicworld/code_hdl_models_arbiter_tb.v

@@ -6,10 +6,10 @@ reg             req3 = 0;
 reg             req2 = 0;
 reg             req1 = 0;
 reg             req0 = 0;
-wire            gnt3;   
-wire            gnt2;   
-wire            gnt1;   
-wire            gnt0;  
+wire            gnt3;
+wire            gnt2;
+wire            gnt1;
+wire            gnt0;
 
 // Clock generator
 always #1 clk = ~clk;
@@ -41,20 +41,20 @@ initial begin
   req0 <= 0;
   repeat (1) @ (posedge clk);
   #10 $finish;
-end 
+end
 
 // Connect the DUT
 arbiter U (
- clk,    
- rst,    
- req3,   
- req2,   
- req1,   
- req0,   
- gnt3,   
- gnt2,   
- gnt1,   
- gnt0   
+ clk,
+ rst,
+ req3,
+ req2,
+ req1,
+ req0,
+ gnt3,
+ gnt2,
+ gnt1,
+ gnt0
 );
 
 endmodule

tests/asicworld/code_hdl_models_cam.v

@@ -9,18 +9,18 @@ clk         , // Cam clock
 cam_enable  , // Cam enable
 cam_data_in , // Cam data to match
 cam_hit_out , // Cam match has happened
-cam_addr_out  // Cam output address 
+cam_addr_out  // Cam output address
 );
 
 parameter ADDR_WIDTH  = 8;
 parameter DEPTH       = 1 << ADDR_WIDTH;
 //------------Input Ports--------------
-input                    clk;      
-input                    cam_enable;   
-input  [DEPTH-1:0]       cam_data_in;  
+input                    clk;
+input                    cam_enable;
+input  [DEPTH-1:0]       cam_data_in;
 //----------Output Ports--------------
-output                   cam_hit_out;  
-output [ADDR_WIDTH-1:0]  cam_addr_out;  
+output                   cam_hit_out;
+output [ADDR_WIDTH-1:0]  cam_addr_out;
 //------------Internal Variables--------
 reg [ADDR_WIDTH-1:0]  cam_addr_out;
 reg                   cam_hit_out;
@@ -46,7 +46,7 @@ always @(cam_data_in) begin
   end
 end
 
-// Register the outputs 
+// Register the outputs
 always @(posedge clk) begin
   if (cam_enable) begin
     cam_hit_out  <=  cam_hit_combo;
@@ -57,4 +57,4 @@ always @(posedge clk) begin
   end
 end
 
-endmodule 
+endmodule

tests/asicworld/code_hdl_models_clk_div.v

@@ -6,7 +6,7 @@
 //-----------------------------------------------------
 
 module clk_div (clk_in, enable,reset, clk_out);
- // --------------Port Declaration----------------------- 
+ // --------------Port Declaration-----------------------
  input               clk_in                   ;
  input               reset                    ;
  input               enable                   ;
@@ -16,12 +16,12 @@ module clk_div (clk_in, enable,reset, clk_out);
  wire                 enable                  ;
 //--------------Internal Registers----------------------
 reg                   clk_out                 ;
-//--------------Code Starts Here----------------------- 
-always @ (posedge clk_in) 
-if (reset) begin 
+//--------------Code Starts Here-----------------------
+always @ (posedge clk_in)
+if (reset) begin
   clk_out <= 1'b0;
 end else if (enable) begin
-  clk_out <= !clk_out ; 
+  clk_out <= !clk_out ;
 end
 
-endmodule  
+endmodule

tests/asicworld/code_hdl_models_clk_div_45.v

@@ -28,7 +28,7 @@ reg         toggle2    ;
 
 //--------------Code Starts Here-----------------------
 always @ (posedge clk_in)
-if (enable == 1'b0) begin 
+if (enable == 1'b0) begin
    counter1 <= 4'b0;
    toggle1  <= 0;
 end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4))  begin
@@ -37,7 +37,7 @@ end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4))  begin
 end else   begin
    counter1 <= counter1 + 1;
 end
-   
+
 always @ (negedge clk_in)
 if (enable == 1'b0) begin
   counter2 <= 4'b0;

tests/asicworld/code_hdl_models_decoder_using_assign.v

@@ -6,14 +6,14 @@
 //-----------------------------------------------------
 module decoder_using_assign (
 binary_in   , //  4 bit binary input
-decoder_out , //  16-bit out 
+decoder_out , //  16-bit out
 enable        //  Enable for the decoder
 );
 input [3:0] binary_in  ;
-input  enable ; 
-output [15:0] decoder_out ; 
-        
-wire [15:0] decoder_out ; 
+input  enable ;
+output [15:0] decoder_out ;
+
+wire [15:0] decoder_out ;
 
 assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
 

tests/asicworld/code_hdl_models_dff_async_reset.v

@@ -7,11 +7,11 @@
 module dff_async_reset (
 data  , // Data Input
 clk    , // Clock Input
-reset , // Reset input 
+reset , // Reset input
 q         // Q output
 );
 //-----------Input Ports---------------
-input data, clk, reset ; 
+input data, clk, reset ;
 
 //-----------Output Ports---------------
 output q;

tests/asicworld/code_hdl_models_dff_sync_reset.v

@@ -11,7 +11,7 @@ reset  , // Reset input
 q        // Q output
 );
 //-----------Input Ports---------------
-input data, clk, reset ; 
+input data, clk, reset ;
 
 //-----------Output Ports---------------
 output q;

tests/asicworld/code_hdl_models_encoder_using_case.v

@@ -10,31 +10,31 @@ encoder_in , //  16-bit Input
 enable       //  Enable for the encoder
 );
 output [3:0] binary_out  ;
-input  enable ; 
-input [15:0] encoder_in ; 
-     
+input  enable ;
+input [15:0] encoder_in ;
+
 reg [3:0] binary_out ;
-      
+
 always @ (enable or encoder_in)
 begin
   binary_out = 0;
   if (enable) begin
-    case (encoder_in) 
-      16'h0002 : binary_out = 1; 
-      16'h0004 : binary_out = 2; 
-      16'h0008 : binary_out = 3; 
+    case (encoder_in)
+      16'h0002 : binary_out = 1;
+      16'h0004 : binary_out = 2;
+      16'h0008 : binary_out = 3;
       16'h0010 : binary_out = 4;
-      16'h0020 : binary_out = 5; 
-      16'h0040 : binary_out = 6; 
-      16'h0080 : binary_out = 7; 
+      16'h0020 : binary_out = 5;
+      16'h0040 : binary_out = 6;
+      16'h0080 : binary_out = 7;
       16'h0100 : binary_out = 8;
       16'h0200 : binary_out = 9;
-      16'h0400 : binary_out = 10; 
-      16'h0800 : binary_out = 11; 
-      16'h1000 : binary_out = 12; 
-      16'h2000 : binary_out = 13; 
-      16'h4000 : binary_out = 14; 
-      16'h8000 : binary_out = 15; 
+      16'h0400 : binary_out = 10;
+      16'h0800 : binary_out = 11;
+      16'h1000 : binary_out = 12;
+      16'h2000 : binary_out = 13;
+      16'h4000 : binary_out = 14;
+      16'h8000 : binary_out = 15;
    endcase
   end
 end

tests/asicworld/code_hdl_models_encoder_using_if.v

@@ -8,51 +8,51 @@ module encoder_using_if(
 binary_out , //  4 bit binary output
 encoder_in , //  16-bit input
 enable       //  Enable for the encoder
-); 
+);
 //-----------Output Ports---------------
 output [3:0] binary_out  ;
 //-----------Input Ports---------------
-input  enable ; 
-input [15:0] encoder_in ; 
+input  enable ;
+input [15:0] encoder_in ;
 //------------Internal Variables--------
-reg [3:0] binary_out ;  
+reg [3:0] binary_out ;
 //-------------Code Start-----------------
 always @ (enable or encoder_in)
- begin 
-   binary_out = 0; 
+ begin
+   binary_out = 0;
    if (enable) begin
      if (encoder_in == 16'h0002) begin
       binary_out = 1;
-     end  if (encoder_in == 16'h0004) begin 
-      binary_out = 2; 
-     end  if (encoder_in == 16'h0008) begin 
-      binary_out = 3; 
-     end  if (encoder_in == 16'h0010) begin 
-      binary_out = 4; 
-     end  if (encoder_in == 16'h0020) begin 
-      binary_out = 5; 
-     end  if (encoder_in == 16'h0040) begin 
-      binary_out = 6; 
-     end  if (encoder_in == 16'h0080) begin 
-      binary_out = 7; 
-     end  if (encoder_in == 16'h0100) begin 
-      binary_out = 8; 
-     end  if (encoder_in == 16'h0200) begin 
-      binary_out = 9; 
-     end if (encoder_in == 16'h0400) begin 
-      binary_out = 10; 
-     end  if (encoder_in == 16'h0800) begin 
-      binary_out = 11; 
+     end  if (encoder_in == 16'h0004) begin
+      binary_out = 2;
+     end  if (encoder_in == 16'h0008) begin
+      binary_out = 3;
+     end  if (encoder_in == 16'h0010) begin
+      binary_out = 4;
+     end  if (encoder_in == 16'h0020) begin
+      binary_out = 5;
+     end  if (encoder_in == 16'h0040) begin
+      binary_out = 6;
+     end  if (encoder_in == 16'h0080) begin
+      binary_out = 7;
+     end  if (encoder_in == 16'h0100) begin
+      binary_out = 8;
+     end  if (encoder_in == 16'h0200) begin
+      binary_out = 9;
+     end if (encoder_in == 16'h0400) begin
+      binary_out = 10;
+     end  if (encoder_in == 16'h0800) begin
+      binary_out = 11;
      end  if (encoder_in == 16'h1000) begin
-      binary_out = 12; 
-     end  if (encoder_in == 16'h2000) begin 
+      binary_out = 12;
+     end  if (encoder_in == 16'h2000) begin
       binary_out = 13;
-     end  if (encoder_in == 16'h4000) begin 
-      binary_out = 14; 
-     end if (encoder_in == 16'h8000) begin 
-      binary_out = 15; 
+     end  if (encoder_in == 16'h4000) begin
+      binary_out = 14;
+     end if (encoder_in == 16'h8000) begin
+      binary_out = 15;
      end
   end
 end
-      
+
 endmodule

tests/asicworld/code_hdl_models_gray_counter.v

@@ -10,24 +10,24 @@ module gray_counter (
   clk    , // clock
   rst      // active hight reset
   );
-  
+
   //------------Input Ports--------------
-  input clk, rst, enable; 
+  input clk, rst, enable;
   //----------Output Ports----------------
   output [ 7:0] out;
   //------------Internal Variables--------
   wire [7:0] out;
   reg [7:0] count;
   //-------------Code Starts Here---------
-  always @ (posedge clk) 
-  if (rst) 
-    count <= 0; 
-  else if (enable) 
-    count <= count + 1; 
-    
-  assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ 
-               count[5]),(count[5] ^ count[4]), (count[4] ^ 
-               count[3]),(count[3] ^ count[2]), (count[2] ^ 
+  always @ (posedge clk)
+  if (rst)
+    count <= 0;
+  else if (enable)
+    count <= count + 1;
+
+  assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
+               count[5]),(count[5] ^ count[4]), (count[4] ^
+               count[3]),(count[3] ^ count[2]), (count[2] ^
                count[1]),(count[1] ^ count[0]) };
-    
-endmodule 
+
+endmodule

tests/asicworld/code_hdl_models_lfsr.v

@@ -30,6 +30,6 @@ end else if (enable) begin
           out[4],out[3],
           out[2],out[1],
           out[0], linear_feedback};
-end 
+end
 
 endmodule // End Of Module counter

tests/asicworld/code_hdl_models_lfsr_updown.v

@@ -1,4 +1,4 @@
-`define WIDTH 8 
+`define WIDTH 8
 module lfsr_updown (
 clk       ,   // Clock input
 reset     ,   // Reset input
@@ -10,7 +10,7 @@ overflow      // Overflow output
 
  input clk;
  input reset;
- input enable; 
+ input enable;
  input up_down;
 
  output [`WIDTH-1 : 0] count;
@@ -18,11 +18,11 @@ overflow      // Overflow output
 
  reg [`WIDTH-1 : 0] count;
 
- assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : 
+ assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
                                (count == {1'b1, {`WIDTH-1{1'b0}}}) ;
 
  always @(posedge clk)
- if (reset) 
+ if (reset)
     count <= {`WIDTH{1'b0}};
  else if (enable) begin
     if (up_down) begin

tests/asicworld/code_hdl_models_mux_using_case.v

@@ -19,10 +19,10 @@ reg  mux_out;
 //-------------Code Starts Here---------
 always @ (sel or din_0 or din_1)
 begin : MUX
- case(sel ) 
+ case(sel )
     1'b0 : mux_out = din_0;
     1'b1 : mux_out = din_1;
- endcase 
+ endcase
 end
 
 endmodule //End Of Module mux

tests/asicworld/code_hdl_models_one_hot_cnt.v

@@ -17,7 +17,7 @@ output [7:0] out;
 input enable, clk, reset;
 
 //------------Internal Variables--------
-reg [7:0] out;  
+reg [7:0] out;
 
 //-------------Code Starts Here-------
 always @ (posedge clk)
@@ -28,4 +28,4 @@ end else if (enable) begin
           out[2],out[1],out[0],out[7]};
 end
 
-endmodule  
+endmodule

tests/asicworld/code_hdl_models_parallel_crc.v

@@ -8,8 +8,8 @@ module parallel_crc_ccitt (
 clk     ,
 reset   ,
 enable  ,
-init    , 
-data_in , 
+init    ,
+data_in ,
 crc_out
 );
 //-----------Input Ports---------------

tests/asicworld/code_hdl_models_parity_using_assign.v

@@ -9,13 +9,13 @@ data_in    , //  8 bit data in
 parity_out   //  1 bit parity out
 );
 output  parity_out ;
-input [7:0] data_in ; 
-     
+input [7:0] data_in ;
+
 wire parity_out ;
-      
-assign parity_out =  (data_in[0] ^ data_in[1]) ^  
-                     (data_in[2] ^ data_in[3]) ^ 
-                     (data_in[4] ^ data_in[5]) ^  
+
+assign parity_out =  (data_in[0] ^ data_in[1]) ^
+                     (data_in[2] ^ data_in[3]) ^
+                     (data_in[4] ^ data_in[5]) ^
                      (data_in[6] ^ data_in[7]);
 
-endmodule 
+endmodule

tests/asicworld/code_hdl_models_parity_using_bitwise.v

@@ -9,8 +9,8 @@ data_in    , //  8 bit data in
 parity_out   //  1 bit parity out
 );
 output  parity_out ;
-input [7:0] data_in ; 
-     
-assign parity_out = ^data_in; 
+input [7:0] data_in ;
+
+assign parity_out = ^data_in;
 
 endmodule

tests/asicworld/code_hdl_models_parity_using_function.v

@@ -9,21 +9,21 @@ data_in    , //  8 bit data in
 parity_out   //  1 bit parity out
 );
 output  parity_out ;
-input [7:0] data_in ; 
-     
-wire parity_out ; 
+input [7:0] data_in ;
+
+wire parity_out ;
 
 function parity;
-  input [31:0] data; 
+  input [31:0] data;
   begin
-    parity =  (data_in[0] ^ data_in[1]) ^  
-              (data_in[2] ^ data_in[3]) ^ 
-              (data_in[4] ^ data_in[5]) ^  
+    parity =  (data_in[0] ^ data_in[1]) ^
+              (data_in[2] ^ data_in[3]) ^
+              (data_in[4] ^ data_in[5]) ^
               (data_in[6] ^ data_in[7]);
-  end 
-endfunction 
- 
-      
+  end
+endfunction
+
+
 assign parity_out = parity(data_in);
 
 endmodule

tests/asicworld/code_hdl_models_pri_encoder_using_assign.v

@@ -6,31 +6,31 @@
 //-----------------------------------------------------
 module pri_encoder_using_assign (
 binary_out , //  4 bit binary output
-encoder_in , //  16-bit input 
+encoder_in , //  16-bit input
 enable       //  Enable for the encoder
 );
 
 output [3:0] binary_out ;
-input  enable ; 
-input [15:0] encoder_in ; 
+input  enable ;
+input [15:0] encoder_in ;
 
 wire [3:0] binary_out ;
-      
-assign  binary_out  = (!enable) ? 0 : (
-    (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : 
-    (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : 
-    (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : 
-    (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : 
-    (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : 
-    (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : 
-    (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : 
-    (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : 
-    (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : 
-    (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : 
-    (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : 
-    (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : 
-    (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : 
-    (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : 
-    (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15); 
 
-endmodule 
+assign  binary_out  = (!enable) ? 0 : (
+    (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
+    (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
+    (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
+    (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
+    (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
+    (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
+    (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
+    (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
+    (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
+    (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
+    (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
+    (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
+    (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
+    (encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
+    (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
+
+endmodule

tests/asicworld/code_hdl_models_rom_using_case.v

@@ -7,7 +7,7 @@
 module rom_using_case (
 address , // Address input
 data    , // Data output
-read_en , // Read Enable 
+read_en , // Read Enable
 ce        // Chip Enable
 );
 input [3:0] address;
@@ -16,7 +16,7 @@ input read_en;
 input ce;
 
 reg [7:0] data ;
-       
+
 always @ (ce or read_en or address)
 begin
   case (address)

tests/asicworld/code_hdl_models_serial_crc.v

@@ -8,8 +8,8 @@ module serial_crc_ccitt (
 clk     ,
 reset   ,
 enable  ,
-init    , 
-data_in , 
+init    ,
+data_in ,
 crc_out
 );
 //-----------Input Ports---------------
@@ -49,6 +49,6 @@ end else if (enable) begin
     lfsr[14] <= lfsr[13];
     lfsr[15] <= lfsr[14];
   end
-end 
+end
 
 endmodule

tests/asicworld/code_hdl_models_tff_async_reset.v

@@ -11,7 +11,7 @@ reset , // Reset input
 q       // Q output
 );
 //-----------Input Ports---------------
-input data, clk, reset ; 
+input data, clk, reset ;
 //-----------Output Ports---------------
 output q;
 //------------Internal Variables--------