Merge remote-tracking branch 'upstream' into merge3

techlibs/xilinx/arith_map.v

@@ -199,4 +199,3 @@ end else begin
 
 end endgenerate
 endmodule
-

techlibs/xilinx/brams_xcu_map.v

@@ -222,4 +222,3 @@ end
 endgenerate
 
 endmodule
-

techlibs/xilinx/cells_xtra.v

@@ -34826,4 +34826,3 @@ module FE(DEBUG_DOUT, DEBUG_PHASE, INTERRUPT, M_AXIS_DOUT_TDATA, M_AXIS_DOUT_TLA
     input [31:0] S_AXI_WDATA;
     input S_AXI_WVALID;
 endmodule
-

techlibs/xilinx/ff_map.v

@@ -117,4 +117,3 @@ module  \$_DLATCH_PPP_ (input E, S, R, D, output Q);
 endmodule
 
 `endif
-

techlibs/xilinx/lut_map.v

@@ -98,4 +98,3 @@ module \$lut (A, Y);
 endmodule
 
 `endif
-

techlibs/xilinx/tests/bram1.sh

@@ -61,4 +61,3 @@ grep -h 'Mapping to bram type' bram1_*/synth.log | sort | uniq -c
 
 echo "Cleaning up..."
 rm -rf bram1_cmp bram1.mk bram1_[0-9]*/
-

techlibs/xilinx/tests/bram2.sh

@@ -5,4 +5,3 @@ unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
 ../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
 iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
 vvp -N bram2_tb
-

techlibs/xilinx/tests/test_dsp_model.v

@@ -178,7 +178,7 @@ module testbench;
 				{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
 				{ALUMODE, INMODE} = $urandom;
 				CARRYINSEL = $urandom & $urandom & $urandom;
-				OPMODE = $urandom; 
+				OPMODE = $urandom;
 				if ($urandom & 1'b1)
 					OPMODE[3:0] = 4'b0101; // test multiply more than other modes
 				{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;

techlibs/xilinx/xc3s_mult_map.v

@@ -11,4 +11,3 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 		.P(Y)
 	);
 endmodule
-

techlibs/xilinx/xc3sda_dsp_map.v

@@ -31,4 +31,3 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-

techlibs/xilinx/xc5v_dsp_map.v

@@ -42,4 +42,3 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-

techlibs/xilinx/xc6s_dsp_map.v

@@ -31,5 +31,3 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-
-

techlibs/xilinx/xcu_dsp_map.v

@@ -48,4 +48,3 @@ module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-

techlibs/xilinx/xilinx_dffopt.cc

@@ -365,4 +365,3 @@ unmap:
 } XilinxDffOptPass;
 
 PRIVATE_NAMESPACE_END
-