Merge remote-tracking branch 'upstream' into merge3

kernel/CMakeLists.txt

@@ -25,6 +25,8 @@ yosys_core(kernel
 	celledges.h
 	celltypes.h
 	compute_graph.h
+	compressor_tree.cc
+	compressor_tree.h
 	consteval.h
 	constids.inc
 	cost.cc
@@ -80,7 +82,6 @@ yosys_core(kernel
 	topo_scc.h
 	utils.h
 	version.cc
-	wallace_tree.h
 	yosys.cc
 	yosys_common.h
 	yosys_config.h
@@ -155,7 +156,7 @@ yosys_core(kernel
 
 set(yosys_cc_definitions
 	"$<$<BOOL:${YOSYS_ABC_EXECUTABLE}>:ABCEXTERNAL=\"${YOSYS_ABC_EXECUTABLE}\">"
-	$<$<BOOL:${MSYS}>:YOSYS_WIN32_UNIX_DIR>
+	$<$<BOOL:${MINGW}>:YOSYS_WIN32_UNIX_DIR>
 )
 set_source_files_properties(yosys.cc PROPERTIES
 	COMPILE_DEFINITIONS "${yosys_cc_definitions}"

kernel/calc.cc

@@ -712,4 +712,3 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
 }
 
 YOSYS_NAMESPACE_END
-

kernel/cellhelp.py

@@ -19,7 +19,7 @@ class SimHelper:
     def __init__(self) -> None:
         self.desc = []
         self.tags = []
-    
+
     def __str__(self) -> str:
         printed_fields = [
             "name", "title", "ports", "source", "desc", "code", "group", "ver",
@@ -65,7 +65,7 @@ for line in fileinput.input():
     elif line.startswith("//* "):
         _, key, val = line.split(maxsplit=2)
         setattr(simHelper, key, val)
-    
+
     # code parsing
     if line.startswith("module "):
         clean_line = line[7:].replace("\\", "").replace(";", "")
@@ -97,4 +97,3 @@ for line in fileinput.input():
         print(simHelper)
         # new
         simHelper = SimHelper()
-

kernel/compressor_tree.cc

@@ -0,0 +1,328 @@
+#include "compressor_tree.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+namespace CompressorTree
+{
+
+std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
+{
+	SigSpec sum = module->addWire(NEW_ID, width);
+	SigSpec cout = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, a, b, c, cout, sum);
+
+	SigSpec carry;
+	carry.append(State::S0);
+	carry.append(cout.extract(0, width - 1));
+	return {sum, carry};
+}
+
+std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
+{
+	// First FA: a + b + c -> s0
+	SigSpec s0 = module->addWire(NEW_ID, width);
+	SigSpec cout_h_full = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
+
+	// cin[0] = 0, cin[i] = cout_h_full[i-1]
+	SigSpec cin;
+	cin.append(State::S0);
+	if (width > 1)
+		cin.append(cout_h_full.extract(0, width - 1));
+
+	// Second FA: s0 + d + cin -> sum
+	SigSpec sum = module->addWire(NEW_ID, width);
+	SigSpec carry_full = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
+
+	SigSpec carry;
+	carry.append(State::S0);
+	if (width > 1)
+		carry.append(carry_full.extract(0, width - 1));
+
+	return {sum, carry};
+}
+
+std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
+	int width_a = GetSize(a);
+	int width_b = GetSize(b);
+	std::vector<DepthSig> products;
+	products.reserve(width_a + 3);
+
+	for (int i = 0; i < width_a; i++) {
+		SigBit ai = a[i];
+
+		// b_shifted = (0_i ## b)
+		SigSpec b_shifted = SigSpec(State::S0, i);
+		b_shifted.append(b);
+		b_shifted.extend_u0(width, false);
+
+		// row = b_shifted & replicate(a[i], width)
+		SigSpec ai_rep = SigSpec(ai, width);
+		SigSpec row = module->addWire(NEW_ID, width);
+		module->addAnd(NEW_ID, b_shifted, ai_rep, row);
+
+		// Apply Modified Baugh-Wooley inversions for this row
+		bool row_is_bottom = (i == width_a - 1);
+		bool any_inversion = (row_is_bottom && b_signed) || a_signed;
+
+		if (any_inversion) {
+			std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
+
+			for (int j = 0; j < width_b; j++) {
+				int col = i + j;
+				if (col < 0 || col >= width)
+					continue;
+				bool col_is_right = (j == width_b - 1);
+				// Flip masks
+				bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
+				if (invert)
+					mask[col] = RTLIL::State::S1;
+			}
+
+			// Skip the xor entirely if the mask is all zeroes
+			bool nonzero = false;
+			for (auto s : mask)
+				if (s == RTLIL::State::S1) {
+					nonzero = true;
+					break;
+				}
+			if (nonzero) {
+				SigSpec inverted = module->addWire(NEW_ID, width);
+				module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
+				row = inverted;
+			}
+		}
+
+		products.push_back({row, 0});
+	}
+
+	// Correction constants
+	auto push_one_at = [&](int col) {
+		if (col < 0 || col >= width)
+			return;
+		std::vector<RTLIL::State> v(width, RTLIL::State::S0);
+		v[col] = RTLIL::State::S1;
+		products.push_back({SigSpec(RTLIL::Const(v)), 0});
+	};
+
+	if (b_signed)
+		push_one_at(width_a - 1);
+	if (a_signed)
+		push_one_at(width_b - 1);
+	if (a_signed || b_signed)
+		push_one_at(width_a + width_b - 1);
+
+	return products;
+}
+
+std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *out_compressor_count, int *out_final_depth) {
+	int levels = 0;
+	int fa_count = 0;
+	int c42_count = 0;
+	int final_depth = 0;
+
+	for (auto &op : operands)
+		op.sig.extend_u0(width);
+
+	// Only compress operands ready at current level
+	for (int level = 0; operands.size() > 2; level++) {
+		// Partition operands into ready and waiting
+		std::vector<DepthSig> ready;
+		std::vector<DepthSig> waiting;
+		ready.reserve(operands.size());
+		for (auto &op : operands) {
+			if (op.depth <= level)
+				ready.push_back(op);
+			else
+				waiting.push_back(op);
+		}
+
+		if (ready.size() < 3) {
+			levels++;
+			continue;
+		}
+
+		// Apply compressors to ready operands
+		std::vector<DepthSig> compressed;
+		compressed.reserve(ready.size());
+		size_t i = 0;
+
+		// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
+		// FA_ONLY skips
+		// DADDA = PREFER_42 (TODO: inspect column heights?)
+		bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
+
+		while (i < ready.size()) {
+			size_t remaining = ready.size() - i;
+
+			if (try_42 && remaining >= 4) {
+				DepthSig a = ready[i + 0];
+				DepthSig b = ready[i + 1];
+				DepthSig c = ready[i + 2];
+				DepthSig d = ready[i + 3];
+
+				auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
+				int dmax = std::max({a.depth, b.depth, c.depth, d.depth});
+
+				compressed.push_back({sum, dmax + 2});
+				compressed.push_back({carry, dmax + 2});
+
+				fa_count += 2;
+				c42_count += 1;
+				i += 4;
+			} else if (remaining >= 3) {
+				DepthSig a = ready[i + 0];
+				DepthSig b = ready[i + 1];
+				DepthSig c = ready[i + 2];
+
+				auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
+				int dmax = std::max({a.depth, b.depth, c.depth});
+
+				compressed.push_back({sum, dmax + 1});
+				compressed.push_back({carry, dmax + 1});
+
+				fa_count += 1;
+				i += 3;
+			} else {
+				// Uncompressed operands pass through to next level
+				for (; i < ready.size(); i++)
+					compressed.push_back(ready[i]);
+				break;
+			}
+		}
+
+		// Merge compressed with waiting operands
+		for (auto &op : waiting)
+			compressed.push_back(op);
+
+		operands = std::move(compressed);
+		levels++;
+	}
+
+	if(out_compressor_count)
+		*out_compressor_count = fa_count;
+	if (operands.size() == 0) {
+		if (out_final_depth)
+			*out_final_depth = 0;
+		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
+	}
+	if (operands.size() == 1) {
+		if (out_final_depth)
+			*out_final_depth = operands[0].depth;
+		return {operands[0].sig, SigSpec(State::S0, width)};
+	}
+
+	final_depth = std::max(operands[0].depth, operands[1].depth);
+	if (out_final_depth)
+		*out_final_depth = final_depth;
+	log_assert(operands.size() == 2);
+	log("    CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
+	return {operands[0].sig, operands[1].sig};
+}
+
+void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
+{
+	int width = GetSize(y);
+	log_assert(GetSize(a) == width);
+	log_assert(GetSize(b) == width);
+
+	if (width == 0)
+		return;
+
+	if (width == 1) {
+		module->addXorGate(NEW_ID, a[0], b[0], y[0]);
+		return;
+	}
+
+	// Bit level gen and prop
+	std::vector<SigBit> g_pre(width), p_pre(width);
+	for (int i = 0; i < width; i++) {
+		SigBit gi = module->addWire(NEW_ID);
+		SigBit pi = module->addWire(NEW_ID);
+		module->addAndGate(NEW_ID, a[i], b[i], gi);
+		module->addXorGate(NEW_ID, a[i], b[i], pi);
+		g_pre[i] = gi;
+		p_pre[i] = pi;
+	}
+
+	// Propagate (g, p) through ceil(log2 W) levels
+	std::vector<SigBit> g = g_pre;
+	std::vector<SigBit> p = p_pre;
+	int num_levels = 0;
+
+	while ((1 << num_levels) < width)
+		num_levels++;
+
+	for (int k = 1; k <= num_levels; k++) {
+		int s = 1 << (k - 1);
+		std::vector<SigBit> g_next(width), p_next(width);
+		for (int i = 0; i < width; i++) {
+			if (i < s) {
+				// Nothing to do
+				g_next[i] = g[i];
+				p_next[i] = p[i];
+			} else {
+				// g_i^k = g_i | (p_i & g_(i-s))
+				SigBit and_pg = module->addWire(NEW_ID);
+				module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
+				SigBit gnew = module->addWire(NEW_ID);
+				module->addOrGate(NEW_ID, g[i], and_pg, gnew);
+				g_next[i] = gnew;
+
+				// p_i^k = p_i & p_(i-s)
+				if (k < num_levels) {
+					SigBit pnew = module->addWire(NEW_ID);
+					module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
+					p_next[i] = pnew;
+				} else {
+					// Skip last level
+					p_next[i] = State::Sx;
+				}
+			}
+		}
+
+		g = std::move(g_next);
+		p = std::move(p_next);
+	}
+
+	// Sum layer, g[i] is COUT of bit i
+	// With CIN 0:
+	//   sum[0] = p_pre[0]
+	//   sum[i] = p_pre[i] ^ g[i-1] ...
+	module->connect(y[0], p_pre[0]);
+	for (int i = 1; i < width; i++)
+		module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
+}
+
+Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
+	switch (choice) {
+		case FinalAdder::DEFAULT:
+		case FinalAdder::RIPPLE: {
+			return module->addAdd(NEW_ID, a, b, y, false);
+		}
+		case FinalAdder::PARALLEL_PREFIX: {
+			emit_kogge_stone(module, a, b, y);
+			return nullptr;
+		}
+	}
+	log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
+	return nullptr;
+}
+
+FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode) {
+	switch (mode) {
+		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
+		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
+		case FinalMode::AUTO:
+		default: {
+			bool wide = width >= RIPPLE_PREFIX_WIDTH_THRESHOLD;
+			bool deep = final_depth >= RIPPLE_PREFIX_DEPTH_THRESHOLD;
+			return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
+		}
+	}
+}
+
+} // namespace CompressorTree
+
+YOSYS_NAMESPACE_END

kernel/compressor_tree.h

@@ -0,0 +1,117 @@
+/**
+ * Generalized compressor-tree utilities for multi-operand addition
+ *
+ * Terminology:
+ * - compressor: $fa viewed as reducing N inputs to M outputs (sum + shifted carry) (N:M compressor)
+ * - level:      A stage of parallel compression operations
+ * - depth:      Maximum number of N:M compressor levels from any input to a signal
+ *
+ * Supported compressors:
+ * - 3:2 compressor
+ * - 4:2 compressor
+ *
+ * References:
+ * - "Some schemes for parallel multipliers" (https://www.acsel-lab.com/arithmetic/arith6/papers/ARITH6_Dadda.pdf)
+ * - "Basilisk: Achieving Competitive Performance with Open EDA Tools" (https://arxiv.org/pdf/2405.03523)
+ * - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
+ * - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
+ */
+
+#ifndef COMPRESSOR_TREE_H
+#define COMPRESSOR_TREE_H
+
+#include "kernel/sigtools.h"
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+namespace CompressorTree
+{
+
+// Width and depth thresholds below which a ripple is preferred over parallel-prefix
+// NOTE: Based on "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (Tables 4.7, 4.9) - the threshold
+//       should be the point where Kogge-Stone isn't strictly less efficient than RCA
+constexpr int RIPPLE_PREFIX_WIDTH_THRESHOLD = 16;
+constexpr int RIPPLE_PREFIX_DEPTH_THRESHOLD = 5;
+
+enum class Strategy {
+	FA_ONLY,   // 3:2 compressors
+	PREFER_42, // Prefer 4:2 grouping when >=4 operands ready
+	DADDA,     // Defer compression until column counts exceed
+};
+
+struct DepthSig {
+	SigSpec sig;
+	int depth;
+};
+
+enum class FinalAdder {
+	DEFAULT,         // emit $add and let downstream techmap pick
+	RIPPLE,          // emit $add with explicit narrow hint
+	PARALLEL_PREFIX, // emit $add with PARALLEL_PREFIX
+};
+
+enum class FinalMode {
+	AUTO,
+	RIPPLE,
+	PREFIX,
+};
+
+std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
+std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
+
+/**
+ * generate_partial_products() - Generate partial products for FMA concat
+ * @module:The Yosys module to which the compressors will be added
+ * @a: Signal A
+ * @b: Signal B
+ * @a_signed: Whether signal A is signed
+ * @b_signed: Whether signal B is signed
+ * @width: Target width
+ *
+ * Return: Partial-product matrix as a set of depth-0 vectors
+ */
+std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width);
+
+/**
+ * reduce_scheduled() - Reduce multiple operands to two using a compressor tree
+ * @module: The Yosys module to which the compressors will be added
+ * @operands: Vector of operands to be reduced
+ * @sigs: Vector of input signals (operands) to be reduced
+ * @width: Target bit-width to which all operands will be zero-extended
+ * @strategy: Compression strategy to use
+ * @out_compressor_count: Optional pointer to return the number of $fa cells emitted
+ * @out_final_depth: Optional pointer to return the final depth of the scheduled tree
+ *
+ * Return: The final two reduced operands, that are to be fed into an adder
+ */
+std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *out_compressor_count = nullptr, int *out_final_depth = nullptr);
+
+/**
+ * emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
+ * @module: The Yosys module to which the gates will be added
+ * @a: Signal A
+ * @b: Signal B
+ * @y: Signal Y = (A + B) mod 2^W
+ */
+void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y);
+
+/**
+ * emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
+ * @module:The Yosys module to which the compressors will be added
+ * @a: Signal A
+ * @b: Signal B
+ * @y: Signal Y
+ * @choice: Adder type to instantiate
+ *
+ * Return: Cell* of the emitted instance
+ */
+Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice);
+
+FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode);
+
+} // namespace CompressorTree
+
+YOSYS_NAMESPACE_END
+
+#endif // COMPRESSOR_TREE_H

kernel/driver.cc

@@ -70,75 +70,6 @@ namespace py = pybind11;
 
 USING_YOSYS_NAMESPACE
 
-#ifdef EMSCRIPTEN
-#  include <sys/stat.h>
-#  include <sys/types.h>
-#  include <emscripten.h>
-
-extern "C" int main(int, char**);
-extern "C" void run(const char*);
-extern "C" const char *errmsg();
-extern "C" const char *prompt();
-
-int main(int argc, char **argv)
-{
-	EM_ASM(
-		if (ENVIRONMENT_IS_NODE)
-		{
-			FS.mkdir('/hostcwd');
-			FS.mount(NODEFS, { root: '.' }, '/hostcwd');
-			FS.mkdir('/hostfs');
-			FS.mount(NODEFS, { root: '/' }, '/hostfs');
-		}
-	);
-
-	mkdir("/work", 0777);
-	chdir("/work");
-	log_files.push_back(stdout);
-	log_error_stderr = true;
-	yosys_banner();
-	yosys_setup();
-#ifdef YOSYS_ENABLE_PYTHON
-	py::object sys = py::module_::import("sys");
-	sys.attr("path").attr("append")(proc_self_dirname());
-	sys.attr("path").attr("append")(proc_share_dirname());
-#endif
-
-	if (argc == 2)
-	{
-		// Run the first argument as a script file
-		run_frontend(argv[1], "script");
-	}
-}
-
-void run(const char *command)
-{
-	int selSize = GetSize(yosys_get_design()->selection_stack);
-	try {
-		log_last_error = "Internal error (see JavaScript console for details)";
-		run_pass(command);
-		log_last_error = "";
-	} catch (...) {
-		while (GetSize(yosys_get_design()->selection_stack) > selSize)
-			yosys_get_design()->pop_selection();
-		throw;
-	}
-}
-
-const char *errmsg()
-{
-	return log_last_error.c_str();
-}
-
-const char *prompt()
-{
-	const char *p = create_prompt(yosys_get_design(), 0);
-	while (*p == '\n') p++;
-	return p;
-}
-
-#else /* EMSCRIPTEN */
-
 #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
 int yosys_history_offset = 0;
 std::string yosys_history_file;
@@ -781,5 +712,3 @@ int main(int argc, char **argv)
 
 	return 0;
 }
-
-#endif /* EMSCRIPTEN */

kernel/functional.h

@@ -33,7 +33,7 @@ YOSYS_NAMESPACE_BEGIN
 namespace Functional {
 	// each function is documented with a short pseudocode declaration or definition
 	// standard C/Verilog operators are used to describe the result
-	// 
+	//
 	// the sorts used in this are:
 	// - bit[N]: a bitvector of N bits
 	//   bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend
@@ -345,9 +345,9 @@ namespace Functional {
 			case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break;
 			case Fn::equal: return v.equal(*this, arg(0), arg(1)); break;
 			case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break;
-			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; 
+			case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break;
 			case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break;
-			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; 
+			case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break;
 			case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break;
 			case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break;
 			case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break;
@@ -510,7 +510,7 @@ namespace Functional {
 				return a;
 			return add(Fn::reduce_or, Sort(1), {a});
 		}
-		Node reduce_xor(Node a) { 
+		Node reduce_xor(Node a) {
 			check_unary(a);
 			if(a.width() == 1)
 				return a;

kernel/io.h

@@ -202,7 +202,7 @@ static auto has_name_member_imp(int)
 	-> decltype(static_cast<const RTLIL::IdString>(std::declval<T>().name), std::true_type{});
 
 template <class T>
-static auto has_name_member_imp(long) 
+static auto has_name_member_imp(long)
 	-> std::false_type;
 
 template <class T>
@@ -213,7 +213,7 @@ static auto ptr_has_name_member_imp(int)
 	-> decltype(static_cast<const RTLIL::IdString>(std::declval<T>()->name), std::true_type{});
 
 template <class T>
-static auto ptr_has_name_member_imp(long) 
+static auto ptr_has_name_member_imp(long)
 	-> std::false_type;
 
 template <class T>
@@ -475,7 +475,7 @@ public:
 private:
 	std::string_view fmt;
 	bool has_escapes = false;
-	// Making array at least size of one to make MSVC happy and strict to standards 
+	// Making array at least size of one to make MSVC happy and strict to standards
 	FoundFormatSpec specs[sizeof...(Args) ? sizeof...(Args) : 1] = {};
 };
 

kernel/json.cc

@@ -169,4 +169,3 @@ void PrettyJson::entry_json(const char *name, const Json &value)
     this->name(name);
     this->value(value);
 }
-

kernel/log.cc

@@ -335,9 +335,6 @@ void log_suppressed() {
 [[noreturn]]
 static void log_error_with_prefix(std::string_view prefix, std::string str)
 {
-#ifdef EMSCRIPTEN
-	auto backup_log_files = log_files;
-#endif
 	int bak_log_make_debug = log_make_debug;
 	log_make_debug = 0;
 	log_suppressed();
@@ -378,10 +375,7 @@ static void log_error_with_prefix(std::string_view prefix, std::string str)
 	if (e && atoi(e))
 		abort();
 
-#ifdef EMSCRIPTEN
-	log_files = backup_log_files;
-	throw 0;
-#elif defined(_MSC_VER)
+#if defined(_MSC_VER)
 	_exit(1);
 #else
 	_Exit(1);
@@ -679,9 +673,7 @@ void log_check_expected()
 			log_warn_regexes.clear();
 			log("Expected %s pattern '%s' found !!!\n", kind, pattern);
 			yosys_shutdown();
-			#ifdef EMSCRIPTEN
-				throw 0;
-			#elif defined(_MSC_VER)
+			#if defined(_MSC_VER)
 				_exit(0);
 			#else
 				_Exit(0);

kernel/log_compat.cc

@@ -83,4 +83,13 @@ void log(const char *format, ...)
     log_formatted(formatted);
 }
 
+void log_compat(const char *format, ...)
+{
+    va_list ap;
+    va_start(ap, format);
+    std::string formatted = vstringf(format, ap);
+    va_end(ap);
+    log_formatted(formatted);
+}
+
 YOSYS_NAMESPACE_END

kernel/mem.cc

@@ -1949,4 +1949,4 @@ RTLIL::Const::iterator MemContents::_range_write(RTLIL::Const::iterator it, RTLI
 	auto it_next = std::next(it, _data_width);
 	std::fill(to_end, it_next, State::S0);
 	return it_next;
-}
+}

kernel/rtlil.cc

@@ -616,6 +616,15 @@ int RTLIL::Const::as_int_saturating(bool is_signed) const
 	return as_int(is_signed);
 }
 
+void RTLIL::Const::tag_bare_integer_const(const std::string &value)
+{
+	if (value.empty() || value.find('\'') != std::string::npos)
+		return;
+	size_t start = (value[0] == '-' || value[0] == '+') ? 1 : 0;
+	if (start < value.size() && std::all_of(value.begin() + start, value.end(), ::isdigit))
+		flags |= RTLIL::CONST_FLAG_SIGNED;
+}
+
 int RTLIL::Const::get_min_size(bool is_signed) const
 {
 	if (empty()) return 0;

kernel/rtlil.h

@@ -1097,6 +1097,8 @@ public:
 	// over/underflow, otherwise the max/min value for int depending on the sign.
 	int as_int_saturating(bool is_signed = false) const;
 
+	void tag_bare_integer_const(const std::string &value);
+
 	std::string as_string(const char* any = "-") const;
 	static Const from_string(const std::string &str);
 	std::vector<RTLIL::State> to_bits() const;

kernel/tclapi.cc

@@ -567,7 +567,7 @@ int yosys_tcl_interp_init(Tcl_Interp *interp)
 	// unpack
 	// pack
 
-	// Note (dev jf 24-12-02): Make log_id escape everything that’s not a valid 
+	// Note (dev jf 24-12-02): Make log_id escape everything that’s not a valid
 	// verilog identifier before adding any tcl API that returns IdString values
 	// to avoid -option injection
 

kernel/topo_scc.h

@@ -241,7 +241,7 @@ public:
     }
 
     // process all remaining nodes in the graph
-    TopoSortedSccs &process_all() {   
+    TopoSortedSccs &process_all() {
         node_enumerator nodes = graph.enumerate_nodes();
         // iterate over all nodes to ensure we process the whole graph
         while (!nodes.finished())

kernel/wallace_tree.h

@@ -1,112 +0,0 @@
-/**
- * Wallace tree utilities for multi-operand addition using carry-save adders
- *
- * Terminology:
- * - compressor: $fa viewed as reducing 3 inputs to 2 outputs (sum + shifted carry) (3:2 compressor)
- * - level:      A stage of parallel compression operations
- * - depth:      Maximum number of 3:2 compressor levels from any input to a signal
- *
- * References:
- * - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
- * - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
- */
-
-#ifndef WALLACE_TREE_H
-#define WALLACE_TREE_H
-
-#include "kernel/sigtools.h"
-#include "kernel/yosys.h"
-
-YOSYS_NAMESPACE_BEGIN
-
-inline std::pair<SigSpec, SigSpec> emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
-{
-	SigSpec sum = module->addWire(NEW_ID, width);
-	SigSpec cout = module->addWire(NEW_ID, width);
-
-	module->addFa(NEW_ID, a, b, c, cout, sum);
-
-	SigSpec carry;
-	carry.append(State::S0);
-	carry.append(cout.extract(0, width - 1));
-	return {sum, carry};
-}
-
-/**
- * wallace_reduce_scheduled() - Reduce multiple operands to two using a Wallace tree
- * @module: The Yosys module to which the compressors will be added
- * @sigs: Vector of input signals (operands) to be reduced
- * @width: Target bit-width to which all operands will be zero-extended
- * @compressor_count: Optional pointer to return the number of $fa cells emitted
- *
- * Return: The final two reduced operands, that are to be fed into an adder
- */
-inline std::pair<SigSpec, SigSpec> wallace_reduce_scheduled(Module *module, std::vector<SigSpec> &sigs, int width, int *compressor_count = nullptr)
-{
-	struct DepthSig {
-		SigSpec sig;
-		int depth;
-	};
-
-	for (auto &s : sigs)
-		s.extend_u0(width);
-
-	std::vector<DepthSig> operands;
-	operands.reserve(sigs.size());
-	for (auto &s : sigs)
-		operands.push_back({s, 0});
-
-	// Number of $fa's emitted
-	if (compressor_count)
-		*compressor_count = 0;
-
-	// Only compress operands ready at current level
-	for (int level = 0; operands.size() > 2; level++) {
-		// Partition operands into ready and waiting
-		std::vector<DepthSig> ready, waiting;
-		for (auto &op : operands) {
-			if (op.depth <= level)
-				ready.push_back(op);
-			else
-				waiting.push_back(op);
-		}
-
-		if (ready.size() < 3)
-			continue;
-
-		// Apply compressors to ready operands
-		std::vector<DepthSig> compressed;
-		size_t i = 0;
-		while (i + 2 < ready.size()) {
-			auto [sum, carry] = emit_fa(module, ready[i].sig, ready[i + 1].sig, ready[i + 2].sig, width);
-			int new_depth = std::max({ready[i].depth, ready[i + 1].depth, ready[i + 2].depth}) + 1;
-			compressed.push_back({sum, new_depth});
-			compressed.push_back({carry, new_depth});
-			if (compressor_count)
-				(*compressor_count)++;
-			i += 3;
-		}
-		// Uncompressed operands pass through to next level
-		for (; i < ready.size(); i++)
-			compressed.push_back(ready[i]);
-		// Merge compressed with waiting operands
-		for (auto &op : waiting)
-			compressed.push_back(op);
-
-		operands = std::move(compressed);
-	}
-
-	if (operands.size() == 0)
-		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
-	else if (operands.size() == 1)
-		return {operands[0].sig, SigSpec(State::S0, width)};
-	else {
-		log_assert(operands.size() == 2);
-		log("    Wallace tree depth: %d levels of $fa + 1 final $add\n", std::max(operands[0].depth, operands[1].depth));
-		return {operands[0].sig, operands[1].sig};
-	}
-}
-
-YOSYS_NAMESPACE_END
-
-#endif

kernel/yosys.cc

@@ -553,7 +553,7 @@ std::string proc_self_dirname()
 		shortpath[--i] = 0;
 	return shortpath;
 }
-#elif defined(EMSCRIPTEN) || defined(__wasm)
+#elif defined(__wasm)
 std::string proc_self_dirname()
 {
 	return "/";
@@ -591,7 +591,7 @@ std::string proc_self_dirname(void)
 	#error "Don't know how to determine process executable base path!"
 #endif
 
-#if defined(EMSCRIPTEN) || defined(__wasm)
+#if defined(__wasm)
 void init_share_dirname()
 {
 	yosys_share_dirname = "/share/";

kernel/yosys_common.h

@@ -77,7 +77,6 @@
 
 #  define strtok_r strtok_s
 #  define strdup _strdup
-#  define snprintf _snprintf
 #  define getcwd _getcwd
 #  define mkdir _mkdir
 #  define popen _popen