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Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id

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Cleaning up log_id()
This commit is contained in:
Miodrag Milanović 2026-05-15 11:07:43 +00:00 • committed by GitHub
commit 36eceed720
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GPG key ID: B5690EEEBB952194
197 changed files with 1311 additions and 1278 deletions
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2
passes/sat/assertpmux.cc
View file

@ -148,7 +148,7 @@ struct AssertpmuxWorker
void run(Cell *pmux)
{
log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
log("Adding assert for $pmux cell %s.%s.\n", module, pmux);
int swidth = pmux->getParam(ID::S_WIDTH).as_int();
int cntbits = ceil_log2(swidth+1);

10
passes/sat/async2sync.cc
View file

@ -91,7 +91,7 @@ struct Async2syncPass : public Pass {
int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
if (trg_width > 1)
log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", log_id(cell));
log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", cell);
if (trg_width == 0) {
if (initstate == State::S0)
@ -147,7 +147,7 @@ struct Async2syncPass : public Pass {
ff.unmap_ce_srst();
log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -212,7 +212,7 @@ struct Async2syncPass : public Pass {
ff.unmap_ce_srst();
log("Replacing %s.%s (%s): ALOAD=%s, AD=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type,
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -245,7 +245,7 @@ struct Async2syncPass : public Pass {
ff.unmap_srst();
log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_arst), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -279,7 +279,7 @@ struct Async2syncPass : public Pass {
{
// Latch.
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);

18
passes/sat/clk2fflogic.cc
View file

@ -173,7 +173,7 @@ struct Clk2fflogicPass : public Pass {
auto &port = mem.rd_ports[i];
if (port.clk_enable)
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(mem.memid), log_id(module));
"Call \"memory\" with -nordff to avoid this error.\n", i, mem.memid.unescape(), module);
}
for (int i = 0; i < GetSize(mem.wr_ports); i++)
@ -184,10 +184,10 @@ struct Clk2fflogicPass : public Pass {
continue;
log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
i, log_id(module), log_id(mem.memid), log_signal(port.clk),
i, module, mem.memid.unescape(), log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_ID, port.clk, past_clk);
@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
module->addFf(NEW_ID, port.en, en_q);
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
module->addFf(NEW_ID, port.addr, addr_q);
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
module->addFf(NEW_ID, port.data, data_q);
port.clk = State::S0;
@ -291,16 +291,16 @@ struct Clk2fflogicPass : public Pass {
if (ff.has_clk) {
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
} else if (ff.has_aload) {
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
} else {
// $sr.
log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
}

8
passes/sat/cutpoint.cc
View file

@ -93,7 +93,7 @@ struct CutpointPass : public Pass {
for (auto module : design->all_selected_modules())
{
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
log("Making all outputs of module %s cut points, removing module contents.\n", module);
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))
module->remove(cell);
@ -125,7 +125,7 @@ struct CutpointPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($anyseq))
continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", module, cell);
for (auto &conn : cell->connections()) {
if (cell->output(conn.first)) {
bool do_cut = true;
@ -171,7 +171,7 @@ struct CutpointPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->port_output) {
log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
log("Making output wire %s.%s a cutpoint.\n", module, wire);
Wire *new_wire = module->addWire(NEW_ID, wire);
module->swap_names(wire, new_wire);
module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire)));
@ -180,7 +180,7 @@ struct CutpointPass : public Pass {
wire->port_output = false;
continue;
}
log("Making wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
log("Making wire %s.%s a cutpoint.\n", module, wire);
for (auto bit : sigmap(wire))
cutpoint_bits.insert(bit);
}

20
passes/sat/eval.cc
View file

@ -149,7 +149,7 @@ struct VlogHammerReporter
for (auto c : module->cells())
if (!satgen.importCell(c))
log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
log_error("Failed to import cell %s (type %s) to SAT database.\n", c->name.unescape(), c->type.unescape());
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
@ -262,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
log_error("Can't read back value for port %s!\n", inputs[i].unescape());
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, inputs[i].unescape(), sig.as_const().as_string());
}
}
if (module->wire(ID(y)) == nullptr)
log_error("No output wire (y) found in module %s!\n", log_id(module->name));
log_error("No output wire (y) found in module %s!\n", module->name.unescape());
RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", module, log_signal(sig), log_signal(undef));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), module->name.unescape());
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@ -288,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
log_error("Output (y) has a different width in module %s compared to rtl!\n", module->name.unescape());
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@ -319,10 +319,10 @@ struct VlogHammerReporter
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name, log_id(mod->name));
log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name, log_id(mod->name));
log_error("Wire %s in module %s is not an input!\n", name, mod->name.unescape());
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
@ -443,7 +443,7 @@ struct EvalPass : public Pass {
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
log_id(module->name), log_id(mod->name));
module->name.unescape(), mod->name.unescape());
module = mod;
}
if (module == NULL)

4
passes/sat/expose.cc
View file

@ -210,7 +210,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", name.unescape());
return module->addWire(name, width);
}
@ -673,7 +673,7 @@ struct ExposePass : public Pass {
}
for (auto cell : delete_cells) {
log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removing cell: %s/%s (%s)\n", module, cell, cell->type.unescape());
module->remove(cell);
}
}

16
passes/sat/fmcombine.cc
View file

@ -77,7 +77,7 @@ struct FmcombineWorker
void import_hier_cell(Cell *cell)
{
if (!cell->parameters.empty())
log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", log_id(original), log_id(cell));
log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", original, cell);
FmcombineWorker sub_worker(design, cell->type, opts);
sub_worker.generate();
@ -95,11 +95,11 @@ struct FmcombineWorker
void generate()
{
if (design->module(combined_type)) {
// log("Combined module %s already exists.\n", log_id(combined_type));
// log("Combined module %s already exists.\n", combined_type.unescape());
return;
}
log("Generating combined module %s from module %s.\n", log_id(combined_type), log_id(orig_type));
log("Generating combined module %s from module %s.\n", combined_type.unescape(), orig_type.unescape());
module = design->addModule(combined_type);
for (auto wire : original->wires()) {
@ -332,15 +332,15 @@ struct FmcombinePass : public Pass {
module = design->module(module_name);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", log_id(module_name));
log_cmd_error("Module %s not found.\n", module_name.unescape());
gold_cell = module->cell(gold_name);
if (gold_cell == nullptr)
log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gold_name), log_id(module));
log_cmd_error("Gold cell %s not found in module %s.\n", gold_name.unescape(), module);
gate_cell = module->cell(gate_name);
if (gate_cell == nullptr)
log_cmd_error("Gate cell %s not found in module %s.\n", log_id(gate_name), log_id(module));
log_cmd_error("Gate cell %s not found in module %s.\n", gate_name.unescape(), module);
}
else
{
@ -363,13 +363,13 @@ struct FmcombinePass : public Pass {
FmcombineWorker worker(design, gold_cell->type, opts);
worker.generate();
IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", log_id(gold_cell), log_id(gate_cell)));
IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", gold_cell, gate_cell));
Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
cell->attributes = gold_cell->attributes;
cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src));
log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
log("Combining cells %s and %s in module %s into new cell %s.\n", gold_cell, gate_cell, module, cell);
for (auto &conn : gold_cell->connections())
cell->setPort(conn.first.str() + "_gold", conn.second);

62
passes/sat/formalff.cc
View file

@ -402,7 +402,7 @@ struct PropagateWorker
sigmap.apply(bit);
if (replaced_clk_bits.count(bit))
log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n",
log_signal(bit), log_id(cell->name), log_id(cell->type), log_id(module));
log_signal(bit), cell->name.unescape(), cell->type.unescape(), module);
}
}
}
@ -436,7 +436,7 @@ struct PropagateWorker
if (it != replaced_clk_bits.end()) {
if (it->second != polarity)
log_error("signal %s from module %s is used as clock with different polarities, run clk2fflogic instead.\n",
log_signal(bit), log_id(module));
log_signal(bit), module);
return;
}
@ -659,7 +659,7 @@ struct FormalFfPass : public Pass {
// XXX $check $print
}
log_debug("%s has %d clk bits\n", log_id(module), GetSize(clk_bits));
log_debug("%s has %d clk bits\n", module, GetSize(clk_bits));
for (auto port : module->ports) {
Wire *wire = module->wire(port);
@ -675,7 +675,7 @@ struct FormalFfPass : public Pass {
}
}
}
log_debug("%s has %d non-input clk bits\n", log_id(module), GetSize(clk_bits));
log_debug("%s has %d non-input clk bits\n", module, GetSize(clk_bits));
if (clk_bits.empty())
continue;
@ -687,21 +687,21 @@ struct FormalFfPass : public Pass {
vector<Cell *> &clocked_cells = clk_bit.second;
if (!clk.is_wire()) {
log_debug("constant clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("constant clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
if (input_bits.count(clk)) {
log_debug("input clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("input clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
auto found = modwalker.signal_drivers.find(clk);
if (found == modwalker.signal_drivers.end() || found->second.empty()) {
log_debug("undriven clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("undriven clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
if (found->second.size() > 1) {
log_debug("multiple drivers for clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("multiple drivers for clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
@ -711,9 +711,9 @@ struct FormalFfPass : public Pass {
pol_clk ? driver.cell->type.in(ID($and), ID($_AND_)) : driver.cell->type.in(ID($or), ID($_OR_));
if (!is_gate) {
log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", log_id(module),
log_id(driver.cell), log_id(driver.cell->type), pol_clk ? "posedge" : "negedge",
log_id(module), log_signal(SigSpec(clk)));
log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", module,
driver.cell, driver.cell->type.unescape(), pol_clk ? "posedge" : "negedge",
module, log_signal(SigSpec(clk)));
continue;
}
@ -724,28 +724,28 @@ struct FormalFfPass : public Pass {
for (int i = 0; i < 2; i++) {
std::swap(gate_clock, gate_enable);
log_debug("clock %s.%s for gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_clock)),
log_id(module), log_signal(SigSpec(clk)));
log_debug("enable %s.%s for gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_enable)),
log_id(module), log_signal(SigSpec(clk)));
log_debug("clock %s.%s for gated clk bit %s.%s\n", module, log_signal(SigSpec(gate_clock)),
module, log_signal(SigSpec(clk)));
log_debug("enable %s.%s for gated clk bit %s.%s\n", module, log_signal(SigSpec(gate_enable)),
module, log_signal(SigSpec(clk)));
found = modwalker.signal_drivers.find(gate_enable);
if (found == modwalker.signal_drivers.end() || found->second.empty()) {
log_debug("undriven gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
log_debug("undriven gate enable %s.%s of gated clk bit %s.%s\n", module,
log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)));
continue;
}
if (found->second.size() > 1) {
log_debug("multiple drivers for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
log_debug("multiple drivers for gate enable %s.%s of gated clk bit %s.%s\n", module,
log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)));
continue;
}
auto gate_driver = *found->second.begin();
if (!gate_driver.cell->is_builtin_ff()) {
log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", module,
log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)));
continue;
}
@ -753,8 +753,8 @@ struct FormalFfPass : public Pass {
if (ff.has_gclk || ff.has_ce || ff.has_sr || ff.has_srst || ff.has_arst || (ff.has_aload && ff.has_clk)) {
log_debug(
"FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible type: %s\n",
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)),
log_id(gate_driver.cell->type));
module, log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)),
gate_driver.cell->type.unescape());
continue;
}
@ -770,8 +770,8 @@ struct FormalFfPass : public Pass {
if (!ff.has_clk || sigmap(ff.sig_clk) != gate_clock || ff.pol_clk != pol_clk) {
log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: "
"%s %s.%s\n",
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module),
log_signal(SigSpec(clk)), ff.pol_clk ? "posedge" : "negedge", log_id(module),
module, log_signal(SigSpec(gate_enable)), module,
log_signal(SigSpec(clk)), ff.pol_clk ? "posedge" : "negedge", module,
log_signal(SigSpec(ff.sig_clk)));
continue;
}
@ -781,8 +781,8 @@ struct FormalFfPass : public Pass {
log_debug("found clock gate, rewriting %d cells\n", GetSize(clocked_cells));
for (auto clocked_cell : clocked_cells) {
log_debug("rewriting cell %s.%s (%s)\n", log_id(module), log_id(clocked_cell),
log_id(clocked_cell->type));
log_debug("rewriting cell %s.%s (%s)\n", module, clocked_cell,
clocked_cell->type.unescape());
if (clocked_cell->is_builtin_ff()) {
@ -855,7 +855,7 @@ struct FormalFfPass : public Pass {
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_const(before), log_const(ff.val_init));
worker.initvals.set_init(ff.sig_q, ff.val_init);
}
@ -892,10 +892,10 @@ struct FormalFfPass : public Pass {
if (flag_clk2ff && ff.has_clk) {
if (ff.sig_clk.is_fully_const())
log_error("Const CLK on %s (%s) from module %s, run async2sync first.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type, module);
if (ff.has_aload || ff.has_arst || ff.has_sr)
log_error("Async inputs on %s (%s) from module %s, run async2sync first.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
@ -912,7 +912,7 @@ struct FormalFfPass : public Pass {
if (!attr.empty() && attr != clk_polarity)
log_error("CLK %s on %s (%s) from module %s also used with opposite polarity, run clk2fflogic instead.\n",
log_id(clk_wire), log_id(cell), log_id(cell->type), log_id(module));
clk_wire, cell, cell->type.unescape(), module);
attr = clk_polarity;
clk_wire->set_bool_attribute(ID::keep);

38
passes/sat/mutate.cc
View file

@ -558,7 +558,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (opts.none) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
log("%s\n", str);
@ -569,20 +569,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &entry : database) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += stringf(" -mode %s", entry.mode);
if (!entry.module.empty())
str += stringf(" -module %s", log_id(entry.module));
str += stringf(" -module %s", entry.module.unescape());
if (!entry.cell.empty())
str += stringf(" -cell %s", log_id(entry.cell));
str += stringf(" -cell %s", entry.cell.unescape());
if (!entry.port.empty())
str += stringf(" -port %s", log_id(entry.port));
str += stringf(" -port %s", entry.port.unescape());
if (entry.portbit >= 0)
str += stringf(" -portbit %d", entry.portbit);
if (entry.ctrlbit >= 0)
str += stringf(" -ctrlbit %d", entry.ctrlbit);
if (!entry.wire.empty())
str += stringf(" -wire %s", log_id(entry.wire));
str += stringf(" -wire %s", entry.wire.unescape());
if (entry.wirebit >= 0)
str += stringf(" -wirebit %d", entry.wirebit);
for (auto &s : entry.src)
@ -600,7 +600,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
if (ctrl_wire == nullptr)
{
log("Adding ctrl port %s to module %s.\n", log_id(name), log_id(module));
log("Adding ctrl port %s to module %s.\n", name.unescape(), module);
ctrl_wire = module->addWire(name, width);
ctrl_wire->port_input = true;
@ -614,7 +614,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
SigSpec ctrl = mutate_ctrl_sig(mod, name, width);
log("Connecting ctrl port to cell %s in module %s.\n", log_id(cell), log_id(mod));
log("Connecting ctrl port to cell %s in module %s.\n", cell, mod);
cell->setPort(name, ctrl);
}
}
@ -652,13 +652,13 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
if (cell->input(opts.port))
{
log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add input inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
SigBit outbit = module->Not(NEW_ID, bit);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = module->Not(NEW_ID, inbit);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -680,13 +680,13 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
SigBit outbit = one ? State::S1 : State::S0;
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? State::S1 : State::S0;
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -709,13 +709,13 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -947,26 +947,26 @@ struct MutatePass : public Pass {
Module *module = design->module(opts.module);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", log_id(opts.module));
log_cmd_error("Module %s not found.\n", opts.module.unescape());
if (opts.cell.empty())
log_cmd_error("Missing -cell argument.\n");
Cell *cell = module->cell(opts.cell);
if (cell == nullptr)
log_cmd_error("Cell %s not found in module %s.\n", log_id(opts.cell), log_id(opts.module));
log_cmd_error("Cell %s not found in module %s.\n", opts.cell.unescape(), opts.module.unescape());
if (opts.port.empty())
log_cmd_error("Missing -port argument.\n");
if (!cell->hasPort(opts.port))
log_cmd_error("Port %s not found on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
log_cmd_error("Port %s not found on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
if (opts.portbit < 0)
log_cmd_error("Missing -portbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
if (opts.mode == "inv") {
mutate_inv(design, opts);
@ -982,7 +982,7 @@ struct MutatePass : public Pass {
log_cmd_error("Missing -ctrlbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
if (opts.mode == "cnot0" || opts.mode == "cnot1") {
mutate_cnot(design, opts, opts.mode == "cnot1");

2
passes/sat/qbfsat.cc
View file

@ -597,7 +597,7 @@ struct QbfSatPass : public Pass {
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the QBF-SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
log_cmd_error("Only one module must be selected for the QBF-SAT pass! (selected: %s and %s)\n", module, mod);
module = mod;
}
if (module == nullptr)

6
passes/sat/recover_names.cc
View file

@ -641,8 +641,8 @@ struct RecoverNamesWorker {
for (auto gate_bit : gate_bits) {
if (solved_gate.count(gate_bit.bit))
continue;
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", log_id(gold_bit.name), gold_bit.bit,
gate_bit.inverted ? "" : "!", log_id(gate_bit.bit.name), gate_bit.bit.bit);
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", gold_bit.name.unescape(), gold_bit.bit,
gate_bit.inverted ? "" : "!", gate_bit.bit.name.unescape(), gate_bit.bit.bit);
if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted))
continue;
log_debug(" success!\n");
@ -660,7 +660,7 @@ struct RecoverNamesWorker {
break;
}
}
log("Recovered %d net name pairs in module `%s' out.\n", GetSize(gate2gold), log_id(gate_mod));
log("Recovered %d net name pairs in module `%s' out.\n", GetSize(gate2gold), gate_mod);
gate_worker.do_rename(gold_mod, gate2gold, buffer_types);
}

2
passes/sat/sat.cc
View file

@ -1369,7 +1369,7 @@ struct SatPass : public Pass {
RTLIL::Module *module = NULL;
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", module, mod);
module = mod;
}
if (module == NULL)

92
passes/sat/sim.cc
View file

@ -250,11 +250,11 @@ struct SimInstance
if (module->get_blackbox_attribute(true))
log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
log_id(module->name), hiername().c_str());
module->name.unescape(), hiername().c_str());
if (module->has_processes())
log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
log_id(module), hiername().c_str());
module, hiername().c_str());
if (parent) {
log_assert(parent->children.count(instance) == 0);
@ -413,9 +413,9 @@ struct SimInstance
std::string hiername() const
{
if (instance != nullptr)
return parent->hiername() + "." + log_id(instance->name);
return parent->hiername() + "." + instance->name.unescape();
return log_id(module->name);
return module->name.unescape();
}
vector<std::string> witness_full_path() const
@ -520,7 +520,7 @@ struct SimInstance
{
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, memid.unescape());
if (state.data[offset] != data) {
state.data.set(offset, data);
dirty_memories.insert(memid);
@ -573,7 +573,7 @@ struct SimInstance
if (has_y) sig_y = cell->getPort(ID::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type));
log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape());
bool err = false;
RTLIL::Const eval_state;
@ -593,7 +593,7 @@ struct SimInstance
err = true;
if (err)
log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
else
set_state(sig_y, eval_state);
return;
@ -602,7 +602,7 @@ struct SimInstance
if (cell->type == ID($print))
return;
log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
}
void update_memory(IdString id) {
@ -616,7 +616,7 @@ struct SimInstance
Const data = Const(State::Sx, mem.width << port.wide_log2);
if (port.clk_enable)
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid));
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, mem.memid.unescape());
if (addr.is_fully_def()) {
int addr_int = addr.as_int();
@ -819,14 +819,14 @@ struct SimInstance
log_assert(cell->module == module);
bool has_src = cell->has_attribute(ID::src);
log("%s %s%s\n", opening_verbiage,
log_id(cell), has_src ? " at" : "");
cell, has_src ? " at" : "");
log_source(cell);
struct SimInstance *sim = this;
while (sim->instance) {
has_src = sim->instance->has_attribute(ID::src);
log(" in instance %s of module %s%s\n", log_id(sim->instance),
log_id(sim->instance->type), has_src ? " at" : "");
log(" in instance %s of module %s%s\n", sim->instance,
sim->instance->type.unescape(), has_src ? " at" : "");
log_source(sim->instance);
sim = sim->parent;
}
@ -927,7 +927,7 @@ struct SimInstance
{
for (auto cell : formal_database)
{
string label = log_id(cell);
string label = cell->name.unescape();
if (cell->attributes.count(ID::src))
label = cell->attributes.at(ID::src).decode_string();
@ -939,17 +939,17 @@ struct SimInstance
}
if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
log("Cover %s.%s (%s) reached.\n", hiername(), log_id(cell), label);
log("Cover %s.%s (%s) reached.\n", hiername(), cell, label);
if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
log("Assumption %s.%s (%s) failed.\n", hiername(), cell, label);
if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
log_cell_w_hierarchy("Failed assertion", cell);
if (shared->serious_asserts)
log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
log_error("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
else
log_warning("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
log_warning("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
}
}
}
@ -970,7 +970,7 @@ struct SimInstance
{
if (!ff_database.empty() || !mem_database.empty()) {
if (wbmods.count(module))
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), log_id(module));
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), module);
wbmods.insert(module);
}
@ -1061,7 +1061,7 @@ struct SimInstance
for (auto name : hdlname)
exit_scope();
} else
register_signal(log_id(signal.first->name), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
register_signal(signal.first->name.unescape().c_str(), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
}
for (auto &trace_mem : trace_mem_database)
@ -1082,7 +1082,7 @@ struct SimInstance
for (auto name : hdlname)
enter_scope("\\" + name);
} else {
signal_name = log_id(memid);
signal_name = memid.unescape();
}
for (auto &trace_index : trace_mem.second) {
@ -1269,13 +1269,13 @@ struct SimInstance
Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
Const sim_val = get_state(item.first);
if (sim_val.size()!=fst_val.size()) {
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first));
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, item.first);
continue;
}
if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
for(int i=0;i<fst_val.size();i++) {
if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, item.first, log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
@ -1283,14 +1283,14 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
for(int i=0;i<sim_val.size();i++) {
if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, item.first, log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
}
} else {
if (fst_val!=sim_val) {
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope, item.first, log_signal(fst_val), log_signal(sim_val));
retVal = true;
}
}
@ -1409,7 +1409,7 @@ struct SimWorker : SimShared
Wire *w = top->module->wire(portname);
if (w == nullptr)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
top->set_state(w, value);
}
@ -1492,24 +1492,24 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
}
for (auto portname : clockn)
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
}
@ -1630,7 +1630,7 @@ struct SimWorker : SimShared
escaped_s = RTLIL::escape_id(cell_name(symbol));
Cell *c = topmod->cell(escaped_s);
if (!c)
log_warning("Wire/cell %s not present in module %s\n",symbol,log_id(topmod));
log_warning("Wire/cell %s not present in module %s\n",symbol,topmod);
if (c->is_mem_cell()) {
std::string memid = c->parameters.at(ID::MEMID).decode_string();
@ -1829,7 +1829,7 @@ struct SimWorker : SimShared
if (!w) {
Cell *c = topmod->cell(escaped_s);
if (!c)
log_warning("Wire/cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
log_warning("Wire/cell %s not present in module %s\n",escaped_s.unescape(),topmod);
else if (c->type.in(ID($anyconst), ID($anyseq))) {
SigSpec sig_y= c->getPort(ID::Y);
if ((int)parts[1].size() != GetSize(sig_y))
@ -1844,9 +1844,9 @@ struct SimWorker : SimShared
} else {
Cell *c = topmod->cell(escaped_s);
if (!c)
log_error("Cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod);
if (!c->is_mem_cell())
log_error("Cell %s is not memory cell in module %s\n",log_id(escaped_s),log_id(topmod));
log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod);
Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
Const data = Const::from_string(parts[2]);
@ -2077,13 +2077,13 @@ struct SimWorker : SimShared
json.entry("version", "Yosys sim summary");
json.entry("generator", yosys_maybe_version());
json.entry("steps", step);
json.entry("top", log_id(top->module->name));
json.entry("top", top->module->name.unescape());
json.name("assertions");
json.begin_array();
for (auto &assertion : triggered_assertions) {
json.begin_object();
json.entry("step", assertion.step);
json.entry("type", log_id(assertion.cell->type));
json.entry("type", assertion.cell->type.unescape());
json.entry("path", assertion.instance->witness_full_path(assertion.cell));
auto src = assertion.cell->get_string_attribute(ID::src);
if (!src.empty()) {
@ -2148,12 +2148,12 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2161,12 +2161,12 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2359,7 +2359,7 @@ struct VCDWriter : public OutputWriter
vcdfile << stringf("$timescale %s $end\n", worker->timescale);
worker->top->write_output_header(
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", name.unescape()); },
[this]() { vcdfile << stringf("$upscope $end\n");},
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2425,7 +2425,7 @@ struct FSTWriter : public OutputWriter
fstWriterSetRepackOnClose(fstfile, 1);
worker->top->write_output_header(
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
[this]() { fstWriterSetUpscope(fstfile); },
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2488,7 +2488,7 @@ struct AIWWriter : public OutputWriter
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
Wire *w = worker->top->module->wire(escaped_s);
if (!w)
log_error("Wire %s not present in module %s\n",log_id(escaped_s),log_id(worker->top->module));
log_error("Wire %s not present in module %s\n",escaped_s.unescape(),worker->top->module);
if (index < w->start_offset || index > w->start_offset + w->width)
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") {

2
passes/sat/supercover.cc
View file

@ -64,7 +64,7 @@ struct SupercoverPass : public Pass {
pool<SigBit> handled_bits;
int cnt_wire = 0, cnt_bits = 0;
log("Adding cover cells to module %s.\n", log_id(module));
log("Adding cover cells to module %s.\n", module);
for (auto wire : module->selected_wires())
{
bool counted_wire = false;

10
passes/sat/synthprop.cc
View file

@ -60,20 +60,20 @@ struct SynthPropWorker
void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path)
{
log("%*sTracing in module %s..\n", 2*depth, "", log_id(mod));
log("%*sTracing in module %s..\n", 2*depth, "", mod);
tracing_data[mod] = TrackingItem();
int cnt = 0;
for (auto cell : mod->cells()) {
if (cell->type == ID($assert)) {
log("%*sFound assert %s..\n", 2*(depth+1), "", log_id(cell));
log("%*sFound assert %s..\n", 2*(depth+1), "", cell);
tracing_data[mod].assertion_cells.emplace(cell);
if (!or_outputs) {
tracing_data[mod].names.push_back(hier_path + "." + log_id(cell));
tracing_data[mod].names.push_back(hier_path + "." + cell->name.unescape());
}
cnt++;
}
else if (RTLIL::Module *submod = design->module(cell->type)) {
tracing(submod, depth+1, tracing_data, hier_path + "." + log_id(cell));
tracing(submod, depth+1, tracing_data, hier_path + "." + cell->name.unescape());
if (!or_outputs) {
for (size_t i = 0; i < tracing_data[submod].names.size(); i++)
tracing_data[mod].names.push_back(tracing_data[submod].names[i]);
@ -93,7 +93,7 @@ void SynthPropWorker::run()
log_error("Module is not TOP module\n");
TrackingData tracing_data;
tracing(module, 0, tracing_data, log_id(module->name));
tracing(module, 0, tracing_data, module->name.unescape());
for (auto &data : tracing_data) {
if (data.second.names.size() == 0) continue;