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Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id

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Cleaning up log_id()
This commit is contained in:
Miodrag Milanović 2026-05-15 11:07:43 +00:00 • committed by GitHub
commit 36eceed720
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GPG key ID: B5690EEEBB952194
197 changed files with 1311 additions and 1278 deletions
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4
passes/opt/muxpack.cc
View file

@ -193,7 +193,7 @@ struct MuxpackWorker
{
for (auto cell : candidate_cells)
{
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
SigSpec a_sig = sigmap(cell->getPort(ID::A));
if (cell->type == ID($mux)) {
@ -272,7 +272,7 @@ struct MuxpackWorker
Cell *last_cell = chain[cursor+cases-1];
log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
module, first_cell, module, last_cell, cases);
mux_count += cases;
pmux_count += 1;

4
passes/opt/opt_balance_tree.cc
View file

@ -279,7 +279,7 @@ struct OptBalanceTreeWorker {
if (inner_cells)
{
// Create a tree
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", log_id(head_cell), GetSize(sources), inner_cells);
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells);
// Build a vector of all source signals
vector<SigSpec> source_signals;
@ -369,7 +369,7 @@ struct OptBalanceTreePass : public Pass {
// Log stats
for (auto cell_type : cell_types)
log("Converted %d %s cells into trees.\n", cell_count[cell_type], log_id(cell_type));
log("Converted %d %s cells into trees.\n", cell_count[cell_type], cell_type.unescape());
// Clean up
Yosys::run_pass("clean -purge");

2
passes/opt/opt_clean/inits.cc
View file

@ -109,7 +109,7 @@ bool remove_redundant_inits(ShardedVector<RTLIL::Wire*> wires, bool verbose) {
bool did_something = false;
for (RTLIL::Wire *wire : wires) {
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
log_debug(" removing redundant init attribute on %s.\n", wire);
wire->attributes.erase(ID::init);
did_something = true;
}

2
passes/opt/opt_demorgan.cc
View file

@ -43,7 +43,7 @@ void demorgan_worker(
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->name.unescape(), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)
{

44
passes/opt/opt_dff.cc
View file

@ -301,7 +301,7 @@ struct OptDffWorker
initvals.remove_init(ff.sig_q[i]);
module->connect(ff.sig_q[i], State::S0);
log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
i, cell, cell->type.unescape(), module);
sr_removed = true;
} else if (is_always_active(ff.sig_set[i], ff.pol_set)) {
initvals.remove_init(ff.sig_q[i]);
@ -312,7 +312,7 @@ struct OptDffWorker
else
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
i, cell, cell->type.unescape(), module);
sr_removed = true;
} else {
keep_bits.push_back(i);
@ -335,7 +335,7 @@ struct OptDffWorker
if (clr_inactive && signal_all_same(ff.sig_set)) {
log("Removing never-active CLR on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_set;
@ -344,7 +344,7 @@ struct OptDffWorker
changed = true;
} else if (set_inactive && signal_all_same(ff.sig_clr)) {
log("Removing never-active SET on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_clr;
@ -370,7 +370,7 @@ struct OptDffWorker
if (!failed) {
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.val_arst = val_arst_builder.build();
@ -389,7 +389,7 @@ struct OptDffWorker
// Converts constant Async Load to ARST
if (is_always_inactive(ff.sig_aload, ff.pol_aload)) {
log("Removing never-active async load on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_aload = false;
changed = true;
return false;
@ -398,7 +398,7 @@ struct OptDffWorker
if (is_active(ff.sig_aload, ff.pol_aload)) {
// ALOAD always active
log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.remove();
if (ff.has_sr) {
@ -433,7 +433,7 @@ struct OptDffWorker
// AD is constant -> ARST
if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_arst = true;
ff.has_aload = false;
ff.sig_arst = ff.sig_aload;
@ -450,12 +450,12 @@ struct OptDffWorker
// Removes ARST if never active or replaces FF if always active
if (is_inactive(ff.sig_arst, ff.pol_arst)) {
log("Removing never-active ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_arst = false;
changed = true;
} else if (is_always_active(ff.sig_arst, ff.pol_arst)) {
log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.remove();
module->connect(ff.sig_q, ff.val_arst);
return true;
@ -469,12 +469,12 @@ struct OptDffWorker
// Removes SRST if never active or forces D to reset value if always active
if (is_inactive(ff.sig_srst, ff.pol_srst)) {
log("Removing never-active SRST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_srst = false;
changed = true;
} else if (is_always_active(ff.sig_srst, ff.pol_srst)) {
log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_srst = false;
if (!ff.ce_over_srst)
ff.has_ce = false;
@ -489,7 +489,7 @@ struct OptDffWorker
if (is_always_inactive(ff.sig_ce, ff.pol_ce)) {
if (ff.has_srst && !ff.ce_over_srst) {
log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.pol_ce = ff.pol_srst;
ff.sig_ce = ff.sig_srst;
ff.has_srst = false;
@ -497,7 +497,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else {
@ -507,7 +507,7 @@ struct OptDffWorker
}
} else if (is_active(ff.sig_ce, ff.pol_ce)) {
log("Removing always-active EN on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = false;
changed = true;
}
@ -517,7 +517,7 @@ struct OptDffWorker
{
if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
@ -532,7 +532,7 @@ struct OptDffWorker
// Detect feedback loops where D is hardwired to Q
if (ff.has_clk && ff.has_srst) {
log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
if (ff.has_ce && ff.ce_over_srst) {
SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine);
SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine);
@ -549,7 +549,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_gclk = ff.has_clk = ff.has_ce = false;
changed = true;
}
@ -627,7 +627,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",
log_id(cell), log_id(cell->type), log_id(module),
cell, cell->type.unescape(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));
}
@ -701,7 +701,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",
log_id(cell), log_id(cell->type), log_id(module),
cell, cell->type.unescape(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));
}
@ -768,7 +768,7 @@ struct OptDffWorker
if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_aload = false;
changed = true;
}
@ -885,7 +885,7 @@ struct OptDffWorker
}
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
val ? 1 : 0, i, log_id(cell), log_id(cell->type), log_id(module));
val ? 1 : 0, i, cell, cell->type.unescape(), module);
// Replace the Q output with the constant value
initvals.remove_init(ff.sig_q[i]);

54
passes/opt/opt_expr.cc
View file

@ -88,7 +88,7 @@ void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
}
}
log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val));
log_debug("Setting undriven signal in %s to constant: %s = %s\n", module, log_signal(sig), log_signal(val));
module->connect(sig, val);
did_something = true;
}
@ -105,11 +105,11 @@ void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
initval.set(i, State::Sx);
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
log_debug("Removing init attribute from %s/%s.\n", module, wire);
wire->attributes.erase(ID::init);
did_something = true;
} else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
log_debug("Updating init attribute on %s/%s: %s\n", module, wire, log_signal(initval));
wire->attributes[ID::init] = initval;
did_something = true;
}
@ -196,7 +196,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
return false;
log_debug("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
for (int i = 0; i < GRP_N; i++)
{
@ -224,7 +224,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
else log_abort();
}
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescape(), log_signal(new_a));
module->connect(new_y, new_b);
module->connect(new_conn);
continue;
@ -261,7 +261,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
}
}
if (!undef_y.empty()) {
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_signal(undef_a));
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescape(), log_signal(undef_a));
module->connect(undef_y, undef_b);
if (def_y.empty()) {
module->connect(new_conn);
@ -292,7 +292,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
module->connect(new_conn);
log_debug(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
log_debug(" New cell `%s': A=%s", c, log_signal(new_a));
if (b_name == ID::B)
log_debug(", B=%s", log_signal(new_b));
log_debug("\n");
@ -308,7 +308,7 @@ void handle_polarity_inv(Cell *cell, IdString port, IdString param, const SigMap
SigSpec sig = assign_map(cell->getPort(port));
if (invert_map.count(sig)) {
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
port.unescape(), cell->type.unescape(), cell, cell->module,
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->setParam(param, !cell->getParam(param).as_bool());
@ -337,7 +337,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, IdStrin
SigSpec sig = assign_map(cell->getPort(port));
if (invert_map.count(sig)) {
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
port.unescape(), cell->type.unescape(), cell, cell->module,
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->type = cell->type == type1 ? type2 : type1;
@ -511,7 +511,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!cells.sort()) {
// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", module);
}
for (auto cell : cells.sorted)
@ -631,7 +631,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
{
if (cell->type == ID($reduce_xnor)) {
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type.unescape(), cell->name.unescape(), module);
cell->type = ID($not);
did_something = true;
} else {
@ -651,7 +651,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (a_fully_const != b_fully_const)
{
log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type.unescape(), cell->name.unescape(), module);
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(ID::Y));
@ -932,7 +932,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
@ -988,7 +988,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
@ -1062,7 +1062,7 @@ skip_fine_alu:
}
if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescape(), cell, module);
RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
@ -1241,7 +1241,7 @@ skip_fine_alu:
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
} else {
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
cell->type = ID($not);
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
@ -1255,8 +1255,8 @@ skip_fine_alu:
if (cell->type.in(ID($eq), ID($ne)) &&
(assign_map(cell->getPort(ID::A)).is_fully_zero() || assign_map(cell->getPort(ID::B)).is_fully_zero()))
{
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescape(), cell,
module, cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B));
@ -1303,7 +1303,7 @@ skip_fine_alu:
}
log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort(ID::B))), shift_bits, log_id(module), log_signal(sig_y));
cell->type.unescape(), cell, log_signal(assign_map(cell->getPort(ID::B))), shift_bits, module, log_signal(sig_y));
module->connect(cell->getPort(ID::Y), sig_y);
module->remove(cell);
@ -1428,7 +1428,7 @@ skip_identity:
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
@ -1446,7 +1446,7 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
@ -1465,7 +1465,7 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::B, cell->getPort(ID::S));
cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
@ -1515,7 +1515,7 @@ skip_identity:
}
if (cell->getPort(ID::S).size() != new_s.size()) {
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
GetSize(cell->getPort(ID::S)) - GetSize(new_s), cell->type.unescape(), cell, module);
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
cell->setPort(ID::S, new_s);
@ -2021,7 +2021,7 @@ skip_alu_split:
Const y_value(cell->type.in(ID($eq), ID($eqx)) ? 0 : 1, GetSize(y_sig));
log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
log_id(cell), log_id(module), log_signal(y_value));
cell, module, log_signal(y_value));
module->connect(y_sig, y_value);
module->remove(cell);
@ -2033,7 +2033,7 @@ skip_alu_split:
if (redundant_bits)
{
log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
redundant_bits, cell->type.unescape(), cell, module);
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
@ -2172,7 +2172,7 @@ skip_alu_split:
if (replace || remove)
{
log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
cell->type.unescape(), cell, condition.c_str(), replacement.c_str());
if (replace)
module->connect(cell->getPort(ID::Y), replace_sig);
module->remove(cell);
@ -2295,7 +2295,7 @@ struct OptExprPass : public Pass {
NewCellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
log("Optimizing module %s.\n", module);
if (undriven) {
did_something = false;

26
passes/opt/opt_hier.cc
View file

@ -101,7 +101,7 @@ struct ModuleIndex {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
log_id(port_name), log_id(instantiation), log_id(module));
port_name.unescape(), instantiation, module);
}
if (port->port_input && port->port_output) {
@ -145,12 +145,12 @@ struct ModuleIndex {
if (nunused > 0) {
log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
nunused, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
if (nconstants > 0) {
log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
nconstants, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
}
@ -189,7 +189,7 @@ struct ModuleIndex {
if (ntie_togethers > 0) {
log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n",
ntie_togethers, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
ntie_togethers, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
@ -290,7 +290,7 @@ struct UsageData {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
log_id(port_name), log_id(instance), log_id(module));
port_name.unescape(), instance, module);
}
if (port->port_input && port->port_output) {
@ -347,7 +347,7 @@ struct UsageData {
};
module->rewrite_sigspecs(disconnect_rewrite);
for (auto chunk : disconnect_outputs.chunks()) {
log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), log_id(module));
log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), module);
did_something = true;
module->connect(chunk, SigSpec(RTLIL::Sx, chunk.size()));
}
@ -368,7 +368,7 @@ struct UsageData {
SigSpec const_ = chunk;
const_.replace(constant_inputs);
log("Substituting constant %s for input terminal '%s' in module '%s'\n",
log_signal(const_), log_signal(chunk), log_id(module));
log_signal(const_), log_signal(chunk), module);
}
// Propagate tied-together inputs
@ -397,7 +397,7 @@ struct UsageData {
module->rewrite_sigspecs(ties_rewrite);
if (applied_ties.size()) {
log("Replacing %zu input terminal bits with tie-togethers in module '%s'\n",
applied_ties.size(), log_id(module));
applied_ties.size(), module);
}
return did_something;
}
@ -433,7 +433,7 @@ struct OptHierPass : Pass {
dict<IdString, ModuleIndex> indices;
for (auto module : d->modules()) {
log_debug("Building index for %s\n", log_id(module));
log_debug("Building index for %s\n", module);
indices.emplace(module->name, ModuleIndex(module));
}
@ -442,14 +442,14 @@ struct OptHierPass : Pass {
if (module->get_bool_attribute(ID::top))
continue;
log_debug("Starting usage data for %s\n", log_id(module));
log_debug("Starting usage data for %s\n", module);
usage_datas.emplace(module->name, UsageData(module));
}
for (auto module : d->modules()) {
for (auto cell : module->cells()) {
if (usage_datas.count(cell->type)) {
log_debug("Account for instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescape(), module);
usage_datas.at(cell->type).refine(cell, indices.at(module->name));
}
}
@ -460,13 +460,13 @@ struct OptHierPass : Pass {
ModuleIndex &parent_index = indices.at(module->name);
if (usage_datas.count(module->name)) {
log_debug("Applying usage data changes to %s\n", log_id(module));
log_debug("Applying usage data changes to %s\n", module);
did_something |= usage_datas.at(module->name).apply_changes(parent_index);
}
for (auto cell : module->cells()) {
if (indices.count(cell->type)) {
log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescape(), module);
did_something |= indices.at(cell->type).apply_changes(parent_index, cell);
}
}

12
passes/opt/opt_lut.cc
View file

@ -121,7 +121,7 @@ struct OptLutWorker
SigSpec lut_input = cell->getPort(ID::A);
int lut_arity = 0;
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, module, cell);
luts.insert(cell);
// First, find all dedicated logic we're connected to. This results in an overapproximation
@ -162,7 +162,7 @@ struct OptLutWorker
{
if (lut_width <= dlogic_conn.first)
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
legal = false;
break;
@ -173,7 +173,7 @@ struct OptLutWorker
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
legal = false;
break;
@ -182,7 +182,7 @@ struct OptLutWorker
if (legal)
{
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
lut_legal_dlogics.insert(lut_dlogic);
for (auto &dlogic_conn : dlogic_map)
lut_dlogic_inputs.insert(dlogic_conn.first);
@ -258,7 +258,7 @@ struct OptLutWorker
if (const0_match || const1_match || input_match != -1)
{
log_debug("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
log_debug("Found redundant cell %s.%s.\n", module, lut);
SigBit value;
if (const0_match)
@ -341,7 +341,7 @@ struct OptLutWorker
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", module, lutA, module, lutB);
if (index.query_is_output(lutA->getPort(ID::Y)))
{

4
passes/opt/opt_lut_ins.cc
View file

@ -64,7 +64,7 @@ struct OptLutInsPass : public Pass {
for (auto module : design->selected_modules())
{
log("Optimizing LUTs in %s.\n", log_id(module));
log("Optimizing LUTs in %s.\n", module);
std::vector<Cell *> remove_cells;
// Gather LUTs.
@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
}
if (!doit)
continue;
log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
log(" Optimizing lut %s (%d -> %d)\n", cell, GetSize(inputs), GetSize(new_inputs));
if (techname == "lattice" || techname == "ecp5") {
// Pad the LUT to 4 inputs, adding consts from the front.
int extra = 4 - GetSize(new_inputs);

6
passes/opt/opt_mem.cc
View file

@ -108,13 +108,13 @@ struct OptMemPass : public Pass {
}
State bit;
if (!always_0[i]) {
log("%s.%s: removing const-1 lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::S1;
} else if (!always_1[i]) {
log("%s.%s: removing const-0 lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::S0;
} else {
log("%s.%s: removing const-x lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-x lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::Sx;
}
// Reconnect read port data.

4
passes/opt/opt_mem_feedback.cc
View file

@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
{
auto &port = mem.wr_ports[i];
log(" Analyzing %s.%s write port %d.\n", log_id(module), log_id(mem.memid), i);
log(" Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
// Okay, let's do it.
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid));
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
// If a write port has a feedback path that we're about to bypass,
// but also has priority over some other write port, the feedback

2
passes/opt/opt_mem_widen.cc
View file

@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass {
factor_log2 = port.wide_log2;
if (factor_log2 == 0)
continue;
log("Widening base width of memory %s in module %s by factor %d.\n", log_id(mem.memid), log_id(module->name), 1 << factor_log2);
log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), module->name.unescape(), 1 << factor_log2);
total_count++;
// The inits are too messy to expand one-by-one, for they may
// collide with one another after expansion. Just hit it with

12
passes/opt/opt_muxtree.cc
View file

@ -229,7 +229,7 @@ struct OptMuxtreeWorker
for (int mux_idx = 0; mux_idx < GetSize(root_muxes); mux_idx++)
if (root_muxes.at(mux_idx)) {
log_debug(" Root of a mux tree: %s%s\n", log_id(mux2info[mux_idx].cell), root_enable_muxes.at(mux_idx) ? " (pure)" : "");
log_debug(" Root of a mux tree: %s%s\n", mux2info[mux_idx].cell, root_enable_muxes.at(mux_idx) ? " (pure)" : "");
root_mux_rerun.erase(mux_idx);
eval_root_mux(mux_idx);
if (glob_evals_left == 0) {
@ -240,7 +240,7 @@ struct OptMuxtreeWorker
while (!root_mux_rerun.empty()) {
int mux_idx = *root_mux_rerun.begin();
log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", log_id(mux2info[mux_idx].cell));
log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", mux2info[mux_idx].cell);
log_assert(root_enable_muxes.at(mux_idx));
root_mux_rerun.erase(mux_idx);
eval_root_mux(mux_idx);
@ -437,7 +437,7 @@ struct OptMuxtreeWorker
// Ran out of subtree depth, re-eval this input tree in the next re-run
root_mux_rerun.insert(m);
root_enable_muxes.at(m) = true;
log_debug(" Removing pure flag from root mux %s.\n", log_id(mux2info[m].cell));
log_debug(" Removing pure flag from root mux %s.\n", mux2info[m].cell);
} else {
auto new_limits = limits.subtree();
// Since our knowledge includes assumption,
@ -517,8 +517,8 @@ struct OptMuxtreeWorker
}
if (did_something) {
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", log_id(portname),
log_id(muxinfo.cell), log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", portname.unescape(),
muxinfo.cell, log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
muxinfo.cell->setPort(portname, sig);
}
}
@ -530,7 +530,7 @@ struct OptMuxtreeWorker
glob_evals_left--;
muxinfo_t &muxinfo = mux2info[mux_idx];
log_debug("\t\teval %s (replace %d enable %d)\n", log_id(muxinfo.cell), limits.do_replace_known, limits.do_mark_ports_observable);
log_debug("\t\teval %s (replace %d enable %d)\n", muxinfo.cell, limits.do_replace_known, limits.do_mark_ports_observable);
// set input ports to constants if we find known active or inactive signals
if (limits.do_replace_known) {

4
passes/opt/opt_share.cc
View file

@ -560,9 +560,9 @@ struct OptSharePass : public Pass {
log(" Found cells that share an operand and can be merged by moving the %s %s in front "
"of "
"them:\n",
log_id(shared.mux->type), log_id(shared.mux));
shared.mux->type.unescape(), shared.mux);
for (const auto& op : shared.ports)
log(" %s\n", log_id(op.op));
log(" %s\n", op.op);
log("\n");
merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap);

2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -44,7 +44,7 @@ endmatch
code
log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
log_id(module), log_id(latch), log_id(and_gate));
module, latch, and_gate);
// Add a flip-flop and rewire the AND gate to use the output of this flop
// instead of the latch. We don't delete the latch in case its output is

2
passes/opt/peepopt_muldiv.pmg
View file

@ -32,7 +32,7 @@ code
val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
did_something = true;
log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv pattern in %s: mul=%s, div=%s\n", module, mul, div);
module->connect(div_y, val_y);
autoremove(div);
accept;

2
passes/opt/peepopt_muldiv_c.pmg
View file

@ -119,7 +119,7 @@ code
autoremove(div);
// Log, fixup, accept
log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div);
mul->fixup_parameters();
accept;
endcode

2
passes/opt/peepopt_shiftadd.pmg
View file

@ -112,7 +112,7 @@ code
did_something = true;
log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
log_id(module), log_id(shift), log_id(add), offset);
module, shift, add, offset);
SigSpec new_a;
if(offset<0) {

2
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -99,7 +99,7 @@ code
}
did_something = true;
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

2
passes/opt/peepopt_shiftmul_right.pmg
View file

@ -76,7 +76,7 @@ code
reject;
did_something = true;
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

12
passes/opt/pmux2shiftx.cc
View file

@ -390,7 +390,7 @@ struct Pmux2ShiftxPass : public Pass {
if (verbose) {
printed_pmux_header = true;
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
log("Inspecting $pmux cell %s/%s.\n", module, cell);
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
@ -441,7 +441,7 @@ struct Pmux2ShiftxPass : public Pass {
if (!printed_pmux_header) {
printed_pmux_header = true;
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
log("Inspecting $pmux cell %s/%s.\n", module, cell);
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
@ -714,7 +714,7 @@ struct Pmux2ShiftxPass : public Pass {
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
log(" created $shiftx cell %s.\n", log_id(c));
log(" created $shiftx cell %s.\n", c);
// remove this sig and continue with the next block
seldb.erase(sig);
@ -799,7 +799,7 @@ struct OnehotPass : public Pass {
continue;
if (verbose)
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), module, cell);
if (!onehot_db.query(A)) {
if (verbose)
@ -831,7 +831,7 @@ struct OnehotPass : public Pass {
if (verbose)
log(" replacing with constant 0 driver.\n");
else
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), module, cell);
module->connect(Y, SigSpec(1, GetSize(Y)));
}
else
@ -840,7 +840,7 @@ struct OnehotPass : public Pass {
if (verbose)
log(" replacing with signal %s.\n", log_signal(sig));
else
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), log_id(module), log_id(cell), log_signal(sig));
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), module, cell, log_signal(sig));
sig.extend_u0(GetSize(Y));
module->connect(Y, sig);
}

38
passes/opt/share.cc
View file

@ -958,7 +958,7 @@ struct ShareWorker
optimize_activation_patterns(activation_patterns_cache[cell]);
if (activation_patterns_cache[cell].empty()) {
log("%sFound cell that is never activated: %s\n", indent, log_id(cell));
log("%sFound cell that is never activated: %s\n", indent, cell);
RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell];
module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size())));
cells_to_remove.insert(cell);
@ -1123,7 +1123,7 @@ struct ShareWorker
for (auto &loop : toposort.loops) {
log("### loop ###\n");
for (auto &c : loop)
log("%s (%s)\n", log_id(c), log_id(c->type));
log("%s (%s)\n", c, c->type.unescape());
}
return found_scc;
@ -1240,14 +1240,14 @@ struct ShareWorker
return;
log("Found %d cells in module %s that may be considered for resource sharing.\n",
GetSize(shareable_cells), log_id(module));
GetSize(shareable_cells), module);
while (!shareable_cells.empty() && config.limit != 0)
{
RTLIL::Cell *cell = *shareable_cells.begin();
shareable_cells.erase(cell);
log(" Analyzing resource sharing options for %s (%s):\n", log_id(cell), log_id(cell->type));
log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescape());
const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " ");
RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
@ -1275,12 +1275,12 @@ struct ShareWorker
log(" Found %d candidates:", GetSize(candidates));
for (auto c : candidates)
log(" %s", log_id(c));
log(" %s", c);
log("\n");
for (auto other_cell : candidates)
{
log(" Analyzing resource sharing with %s (%s):\n", log_id(other_cell), log_id(other_cell->type));
log(" Analyzing resource sharing with %s (%s):\n", other_cell, other_cell->type.unescape());
const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " ");
RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
@ -1332,13 +1332,13 @@ struct ShareWorker
RTLIL::SigSpec all_ctrl_signals;
for (auto &p : filtered_cell_activation_patterns) {
log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
log(" Activation pattern for cell %s: %s = %s\n", cell, log_signal(p.first), log_signal(p.second));
cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
all_ctrl_signals.append(p.first);
}
for (auto &p : filtered_other_cell_activation_patterns) {
log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
log(" Activation pattern for cell %s: %s = %s\n", other_cell, log_signal(p.first), log_signal(p.second));
other_cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
all_ctrl_signals.append(p.first);
}
@ -1349,13 +1349,13 @@ struct ShareWorker
qcsat.prepare();
if (!qcsat.ez->solve(sub1)) {
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell));
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", cell);
cells_to_remove.insert(cell);
break;
}
if (!qcsat.ez->solve(sub2)) {
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell));
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", other_cell);
cells_to_remove.insert(other_cell);
shareable_cells.erase(other_cell);
continue;
@ -1391,20 +1391,20 @@ struct ShareWorker
if (restrict_activation_patterns(optimized_cell_activation_patterns, optimized_other_cell_activation_patterns)) {
for (auto &p : optimized_cell_activation_patterns)
log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
log(" Simplified activation pattern for cell %s: %s = %s\n", cell, log_signal(p.first), log_signal(p.second));
for (auto &p : optimized_other_cell_activation_patterns)
log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
log(" Simplified activation pattern for cell %s: %s = %s\n", other_cell, log_signal(p.first), log_signal(p.second));
}
}
if (find_in_input_cone(cell, other_cell)) {
log(" Sharing not possible: %s is in input cone of %s.\n", log_id(other_cell), log_id(cell));
log(" Sharing not possible: %s is in input cone of %s.\n", other_cell, cell);
continue;
}
if (find_in_input_cone(other_cell, cell)) {
log(" Sharing not possible: %s is in input cone of %s.\n", log_id(cell), log_id(other_cell));
log(" Sharing not possible: %s is in input cone of %s.\n", cell, other_cell);
continue;
}
@ -1424,14 +1424,14 @@ struct ShareWorker
if (cell_select_score <= other_cell_select_score) {
RTLIL::SigSpec act = make_cell_activation_logic(optimized_cell_activation_patterns, supercell_aux);
supercell = make_supercell(cell, other_cell, act, supercell_aux);
log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act));
log(" Activation signal for %s: %s\n", cell, log_signal(act));
} else {
RTLIL::SigSpec act = make_cell_activation_logic(optimized_other_cell_activation_patterns, supercell_aux);
supercell = make_supercell(other_cell, cell, act, supercell_aux);
log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act));
log(" Activation signal for %s: %s\n", other_cell, log_signal(act));
}
log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type));
log(" New cell: %s (%s)\n", supercell, supercell->type.unescape());
cells_to_remove.insert(cell);
cells_to_remove.insert(other_cell);
@ -1476,9 +1476,9 @@ struct ShareWorker
}
if (!cells_to_remove.empty()) {
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), log_id(module));
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), module);
for (auto c : cells_to_remove) {
log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type));
log(" Removing cell %s (%s).\n", c, c->type.unescape());
remove_cell(c);
}
}

30
passes/opt/wreduce.cc
View file

@ -104,14 +104,14 @@ struct WreduceWorker
sig_removed.append(bits_removed[i]);
if (GetSize(bits_removed) == GetSize(sig_y)) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->connect(sig_y, sig_removed);
module->remove(cell);
return;
}
log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type));
GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescape());
int n_removed = GetSize(sig_removed);
int n_kept = GetSize(sig_y) - GetSize(sig_removed);
@ -204,13 +204,13 @@ struct WreduceWorker
return;
if (GetSize(sig_q) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->remove(cell);
return;
}
log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
for (auto bit : sig_d)
work_queue_bits.insert(bit);
@ -258,7 +258,7 @@ struct WreduceWorker
if (bits_removed) {
log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescape());
cell->setPort(stringf("\\%c", port), sig);
did_something = true;
}
@ -331,7 +331,7 @@ struct WreduceWorker
if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) {
log("Converting cell %s.%s (%s) from unsigned to signed.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 1);
cell->setParam(ID::B_SIGNED, 1);
port_a_signed = true;
@ -339,7 +339,7 @@ struct WreduceWorker
did_something = true;
} else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
@ -359,7 +359,7 @@ struct WreduceWorker
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
@ -372,7 +372,7 @@ struct WreduceWorker
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
port_a_signed = false;
did_something = true;
@ -431,14 +431,14 @@ struct WreduceWorker
}
if (GetSize(sig) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->remove(cell);
return;
}
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
cell->setPort(ID::Y, sig);
did_something = true;
}
@ -510,7 +510,7 @@ struct WreduceWorker
if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)])
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), module, w);
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
@ -603,7 +603,7 @@ struct WreducePass : public Pass {
}
if (original_a_width != GetSize(A)) {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
c->setPort(ID::A, A);
c->setParam(ID::A_WIDTH, GetSize(A));
}
@ -619,7 +619,7 @@ struct WreducePass : public Pass {
}
if (original_b_width != GetSize(B)) {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
c->setPort(ID::B, B);
c->setParam(ID::B_WIDTH, GetSize(B));
}
@ -635,7 +635,7 @@ struct WreducePass : public Pass {
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits,
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid));
module, c, memid.unescape());
c->setParam(ID::ABITS, max_addrbits);
c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
}