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Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id

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Cleaning up log_id()
This commit is contained in:
Miodrag Milanović 2026-05-15 11:07:43 +00:00 • committed by GitHub
commit 36eceed720
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197 changed files with 1311 additions and 1278 deletions
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66
passes/memory/memory_bram.cc
View file

@ -44,7 +44,7 @@ struct rules_t
void dump_config() const
{
log(" bram %s # variant %d\n", log_id(name), variant);
log(" bram %s # variant %d\n", name.unescape(), variant);
log(" init %d\n", init);
log(" abits %d\n", abits);
log(" dbits %d\n", dbits);
@ -61,16 +61,16 @@ struct rules_t
void check_vectors() const
{
if (groups != GetSize(ports)) log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n", log_id(name), variant, groups, GetSize(ports));
if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", log_id(name), variant, groups, GetSize(wrmode));
if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", log_id(name), variant, groups, GetSize(enable));
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", log_id(name), variant, groups, GetSize(transp));
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", log_id(name), variant, groups, GetSize(clocks));
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", log_id(name), variant, groups, GetSize(clkpol));
if (groups != GetSize(ports)) log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n", name.unescape(), variant, groups, GetSize(ports));
if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", name.unescape(), variant, groups, GetSize(wrmode));
if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", name.unescape(), variant, groups, GetSize(enable));
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", name.unescape(), variant, groups, GetSize(transp));
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", name.unescape(), variant, groups, GetSize(clocks));
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", name.unescape(), variant, groups, GetSize(clkpol));
int group = 0;
for (auto e : enable)
if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", log_id(name), variant, group, e, dbits);
if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", name.unescape(), variant, group, e, dbits);
}
vector<portinfo_t> make_portinfos() const
@ -100,7 +100,7 @@ struct rules_t
log_assert(name == other.name);
if (groups != other.groups)
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant);
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", name.unescape(), variant, other.variant);
if (abits != other.abits)
variant_params[ID::CFG_ABITS] = abits;
@ -112,7 +112,7 @@ struct rules_t
for (int i = 0; i < groups; i++)
{
if (ports[i] != other.ports[i])
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", log_id(name), variant, other.variant, 'A'+i);
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", name.unescape(), variant, other.variant, 'A'+i);
if (wrmode[i] != other.wrmode[i])
variant_params[stringf("\\CFG_WRMODE_%c", 'A' + i)] = wrmode[i];
if (enable[i] != other.enable[i])
@ -428,7 +428,7 @@ bool replace_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals, const
transp_max = max(transp_max, pi.transp);
}
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
log(" Mapping to bram type %s (variant %d):\n", bram.name.unescape(), bram.variant);
// bram.dump_config();
std::vector<int> shuffle_map;
@ -715,21 +715,21 @@ grow_read_ports:;
for (auto it : match.min_limits) {
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] >= it.second)
continue;
log(" Rule for bram type %s rejected: requirement 'min %s %d' not met.\n",
log_id(match.name), it.first.c_str(), it.second);
match.name.unescape(), it.first.c_str(), it.second);
return false;
}
for (auto it : match.max_limits) {
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] <= it.second)
continue;
log(" Rule for bram type %s rejected: requirement 'max %s %d' not met.\n",
log_id(match.name), it.first.c_str(), it.second);
match.name.unescape(), it.first.c_str(), it.second);
return false;
}
@ -759,13 +759,13 @@ grow_read_ports:;
if (!exists)
ss << "!";
IdString key = std::get<1>(sums.front());
ss << log_id(key);
ss << key.unescape();
const Const &value = rules.map_case(std::get<2>(sums.front()));
if (exists && value != Const(1))
ss << "=\"" << value.decode_string() << "\"";
log(" Rule for bram type %s rejected: requirement 'attribute %s ...' not met.\n",
log_id(match.name), ss.str().c_str());
match.name.unescape(), ss.str().c_str());
return false;
}
}
@ -874,7 +874,7 @@ grow_read_ports:;
for (int dupidx = 0; dupidx < dup_count; dupidx++)
{
Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid, grid_d, grid_a, dupidx)), bram.name);
log(" Creating %s cell at grid position <%d %d %d>: %s\n", log_id(bram.name), grid_d, grid_a, dupidx, log_id(c));
log(" Creating %s cell at grid position <%d %d %d>: %s\n", bram.name.unescape(), grid_d, grid_a, dupidx, c);
for (auto &vp : variant_params)
c->setParam(vp.first, vp.second);
@ -1004,7 +1004,7 @@ grow_read_ports:;
void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
{
log("Processing %s.%s:\n", log_id(mem.module), log_id(mem.memid));
log("Processing %s.%s:\n", mem.module, mem.memid.unescape());
mem.narrow();
bool cell_init = !mem.inits.empty();
@ -1031,7 +1031,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
auto &match = rules.matches.at(i);
if (!rules.brams.count(rules.matches[i].name))
log_error("No bram description for resource %s found!\n", log_id(rules.matches[i].name));
log_error("No bram description for resource %s found!\n", rules.matches[i].name.unescape());
for (int vi = 0; vi < GetSize(rules.brams.at(match.name)); vi++)
{
@ -1047,7 +1047,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
avail_wr_ports += GetSize(bram.ports) < j ? bram.ports.at(j) : 0;
}
log(" Checking rule #%d for bram type %s (variant %d):\n", i+1, log_id(bram.name), bram.variant);
log(" Checking rule #%d for bram type %s (variant %d):\n", i+1, bram.name.unescape(), bram.variant);
log(" Bram geometry: abits=%d dbits=%d wports=%d rports=%d\n", bram.abits, bram.dbits, avail_wr_ports, avail_rd_ports);
int dups = avail_rd_ports ? (match_properties["rports"] + avail_rd_ports - 1) / avail_rd_ports : 1;
@ -1077,11 +1077,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
goto next_match_rule;
log(" Metrics for %s: awaste=%d dwaste=%d bwaste=%d waste=%d efficiency=%d\n",
log_id(match.name), awaste, dwaste, bwaste, waste, efficiency);
match.name.unescape(), awaste, dwaste, bwaste, waste, efficiency);
if (cell_init && bram.init == 0) {
log(" Rule #%d for bram type %s (variant %d) rejected: cannot be initialized.\n",
i+1, log_id(bram.name), bram.variant);
i+1, bram.name.unescape(), bram.variant);
goto next_match_rule;
}
@ -1090,11 +1090,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
continue;
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] >= it.second)
continue;
log(" Rule #%d for bram type %s (variant %d) rejected: requirement 'min %s %d' not met.\n",
i+1, log_id(bram.name), bram.variant, it.first.c_str(), it.second);
i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
goto next_match_rule;
}
@ -1103,11 +1103,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
continue;
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] <= it.second)
continue;
log(" Rule #%d for bram type %s (variant %d) rejected: requirement 'max %s %d' not met.\n",
i+1, log_id(bram.name), bram.variant, it.first.c_str(), it.second);
i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
goto next_match_rule;
}
@ -1137,18 +1137,18 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
if (!exists)
ss << "!";
IdString key = std::get<1>(sums.front());
ss << log_id(key);
ss << key.unescape();
const Const &value = rules.map_case(std::get<2>(sums.front()));
if (exists && value != Const(1))
ss << "=\"" << value.decode_string() << "\"";
log(" Rule for bram type %s (variant %d) rejected: requirement 'attribute %s ...' not met.\n",
log_id(bram.name), bram.variant, ss.str().c_str());
bram.name.unescape(), bram.variant, ss.str().c_str());
goto next_match_rule;
}
}
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant);
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, bram.name.unescape(), bram.variant);
if (or_next_if_better || !best_rule_cache.empty())
{
@ -1156,7 +1156,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
log_error("Found 'or_next_if_better' in last match rule.\n");
if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 1)) {
log(" Mapping to bram type %s failed.\n", log_id(match.name));
log(" Mapping to bram type %s failed.\n", match.name.unescape());
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
goto next_match_rule;
}
@ -1183,12 +1183,12 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
auto &best_bram = rules.brams.at(rules.matches.at(best_rule.first).name).at(best_rule.second);
if (!replace_memory(mem, rules, initvals, best_bram, rules.matches.at(best_rule.first), match_properties, 2))
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", log_id(best_bram.name), best_bram.variant);
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", best_bram.name.unescape(), best_bram.variant);
return;
}
if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 0)) {
log(" Mapping to bram type %s failed.\n", log_id(match.name));
log(" Mapping to bram type %s failed.\n", match.name.unescape());
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
goto next_match_rule;
}

34
passes/memory/memory_libmap.cc
View file

@ -204,7 +204,7 @@ struct MemMapping {
if (!check_init(rdef))
continue;
if (rdef.prune_rom && mem.wr_ports.empty()) {
log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module->name), log_id(mem.memid), log_id(rdef.id));
log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", mem.module->name.unescape(), mem.memid.unescape(), rdef.id.unescape());
continue;
}
MemConfig cfg;
@ -323,7 +323,7 @@ struct MemMapping {
void log_reject(const Ram &ram, std::string message) {
if(ys_debug(1)) {
rejected_cfg_debug_msgs += stringf("can't map to to %s: ", log_id(ram.id));
rejected_cfg_debug_msgs += stringf("can't map to to %s: ", ram.id.unescape());
rejected_cfg_debug_msgs += message;
rejected_cfg_debug_msgs += "\n";
}
@ -338,7 +338,7 @@ struct MemMapping {
rejected_cfg_debug_msgs += portname;
first = false;
}
rejected_cfg_debug_msgs += stringf("] of %s: ", log_id(ram.id));
rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
rejected_cfg_debug_msgs += message;
rejected_cfg_debug_msgs += "\n";
}
@ -361,7 +361,7 @@ struct MemMapping {
rejected_cfg_debug_msgs += portname;
first = false;
}
rejected_cfg_debug_msgs += stringf("] of %s: ", log_id(ram.id));
rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
rejected_cfg_debug_msgs += message;
rejected_cfg_debug_msgs += "\n";
}
@ -380,7 +380,7 @@ void MemMapping::dump_configs(int stage) {
default:
abort();
}
log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module->name), log_id(mem.memid), stage_name);
log_debug("Memory %s.%s mapping candidates (%s):\n", mem.module->name.unescape(), mem.memid.unescape(), stage_name);
if (logic_ok) {
log_debug("- logic fallback\n");
log_debug(" - cost: %f\n", logic_cost);
@ -391,7 +391,7 @@ void MemMapping::dump_configs(int stage) {
}
void MemMapping::dump_config(MemConfig &cfg) {
log_debug("- %s:\n", log_id(cfg.def->id));
log_debug("- %s:\n", cfg.def->id.unescape());
for (auto &it: cfg.def->options)
log_debug(" - option %s %s\n", it.first, log_const(it.second));
log_debug(" - emulation score: %d\n", cfg.score_emu);
@ -527,7 +527,7 @@ void MemMapping::determine_style() {
auto find_attr = search_for_attribute(mem, ID::lram);
if (find_attr.first && find_attr.second.as_bool()) {
kind = RamKind::Huge;
log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module->name), log_id(mem.memid));
log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", mem.module->name.unescape(), mem.memid.unescape());
return;
}
for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) {
@ -536,7 +536,7 @@ void MemMapping::determine_style() {
Const val = find_attr.second;
if (val == 1) {
kind = RamKind::NotLogic;
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", attr.unescape(), mem.module->name.unescape(), mem.memid.unescape());
return;
}
std::string val_s = val.decode_string();
@ -549,20 +549,20 @@ void MemMapping::determine_style() {
// Nothing.
} else if (val_s == "logic" || val_s == "registers") {
kind = RamKind::Logic;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else if (val_s == "distributed") {
kind = RamKind::Distributed;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
kind = RamKind::Block;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else if (val_s == "huge" || val_s == "ultra") {
kind = RamKind::Huge;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else {
kind = RamKind::NotLogic;
style = val_s;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid), val_s);
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape(), val_s);
}
return;
}
@ -1991,7 +1991,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
}
void MemMapping::emit(const MemConfig &cfg) {
log("mapping memory %s.%s via %s\n", log_id(mem.module->name), log_id(mem.memid), log_id(cfg.def->id));
log("mapping memory %s.%s via %s\n", mem.module->name.unescape(), mem.memid.unescape(), cfg.def->id.unescape());
// First, handle emulations.
if (cfg.emu_read_first)
mem.emulate_read_first(&worker.initvals);
@ -2252,9 +2252,9 @@ struct MemoryLibMapPass : public Pass {
int best = map.logic_cost;
if (!map.logic_ok) {
if (map.cfgs.empty()) {
log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module->name), log_id(mem.memid));
log_debug("Rejected candidates for mapping memory %s.%s:\n", module->name.unescape(), mem.memid.unescape());
log_debug("%s", map.rejected_cfg_debug_msgs);
log_error("no valid mapping found for memory %s.%s\n", log_id(module->name), log_id(mem.memid));
log_error("no valid mapping found for memory %s.%s\n", module->name.unescape(), mem.memid.unescape());
}
idx = 0;
best = map.cfgs[0].cost;
@ -2266,7 +2266,7 @@ struct MemoryLibMapPass : public Pass {
}
}
if (idx == -1) {
log("using FF mapping for memory %s.%s\n", log_id(module->name), log_id(mem.memid));
log("using FF mapping for memory %s.%s\n", module->name.unescape(), mem.memid.unescape());
} else {
map.emit(map.cfgs[idx]);
// Rebuild indices after modifying module

2
passes/memory/memory_memx.cc
View file

@ -60,7 +60,7 @@ struct MemoryMemxPass : public Pass {
{
if (port.clk_enable)
log_error("Memory %s.%s has a synchronous read port. Synchronous read ports are not supported by memory_memx!\n",
log_id(module), log_id(mem.memid));
module, mem.memid.unescape());
SigSpec addr_ok = make_addr_check(mem, port.addr);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));

6
passes/memory/memory_share.cc
View file

@ -80,7 +80,7 @@ struct MemoryShareWorker
if (GetSize(mem.rd_ports) <= 1)
return false;
log("Consolidating read ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
log("Consolidating read ports of memory %s.%s by address:\n", module, mem.memid.unescape());
bool changed = false;
int abits = 0;
@ -197,7 +197,7 @@ struct MemoryShareWorker
if (GetSize(mem.wr_ports) <= 1)
return false;
log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
log("Consolidating write ports of memory %s.%s by address:\n", module, mem.memid.unescape());
bool changed = false;
int abits = 0;
@ -316,7 +316,7 @@ struct MemoryShareWorker
if (eligible_ports.size() <= 1)
return;
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, mem.memid.unescape());
// Group eligible ports by clock domain and width.