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Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id

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Cleaning up log_id()
This commit is contained in:
Miodrag Milanović 2026-05-15 11:07:43 +00:00 • committed by GitHub
commit 36eceed720
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GPG key ID: B5690EEEBB952194
197 changed files with 1311 additions and 1278 deletions
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4
passes/equiv/equiv_induct.cc
View file

@ -84,7 +84,7 @@ struct EquivInductWorker : public EquivWorker<>
void run()
{
log("Found %d unproven $equiv cells in module %s:\n", GetSize(workset), log_id(module));
log("Found %d unproven $equiv cells in module %s:\n", GetSize(workset), module);
if (satgen.model_undef) {
for (auto cell : cells)
@ -217,7 +217,7 @@ struct EquivInductPass : public Pass {
}
if (unproven_equiv_cells.empty()) {
log("No selected unproven $equiv cells found in %s.\n", log_id(module));
log("No selected unproven $equiv cells found in %s.\n", module);
continue;
}

14
passes/equiv/equiv_make.cc
View file

@ -160,7 +160,7 @@ struct EquivMakeWorker
if (encdata.count(id))
{
log("Creating encoder/decoder for signal %s.\n", log_id(id));
log("Creating encoder/decoder for signal %s.\n", id.unescape());
Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width);
Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width);
@ -227,15 +227,15 @@ struct EquivMakeWorker
if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) {
if (gold_wire && gold_wire->port_id)
log_error("Can't match gold port `%s' to a gate port.\n", log_id(gold_wire));
log_error("Can't match gold port `%s' to a gate port.\n", gold_wire);
if (gate_wire && gate_wire->port_id)
log_error("Can't match gate port `%s' to a gold port.\n", log_id(gate_wire));
log_error("Can't match gate port `%s' to a gold port.\n", gate_wire);
continue;
}
log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
log_id(gold_wire), log_signal(assign_map(gold_wire)),
log_id(gate_wire), log_signal(assign_map(gate_wire)), log_id(id));
gold_wire, log_signal(assign_map(gold_wire)),
gate_wire, log_signal(assign_map(gate_wire)), id.unescape());
if (gold_wire->port_output || gate_wire->port_output)
{
@ -314,7 +314,7 @@ struct EquivMakeWorker
new_sig[i] = old_sig[i];
if (old_sig != new_sig) {
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
conn.first.unescape(), c, c->type.unescape(),
log_signal(old_sig), log_signal(new_sig));
c->setPort(conn.first, new_sig);
}
@ -345,7 +345,7 @@ struct EquivMakeWorker
goto try_next_cell_name;
log("Presumably equivalent cells: %s %s (%s) -> %s\n",
log_id(gold_cell), log_id(gate_cell), log_id(gold_cell->type), log_id(id));
gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape());
for (auto gold_conn : gold_cell->connections())
{

2
passes/equiv/equiv_mark.cc
View file

@ -109,7 +109,7 @@ struct EquivMarkWorker
void run()
{
log("Running equiv_mark on module %s:\n", log_id(module));
log("Running equiv_mark on module %s:\n", module);
// marking region 0

12
passes/equiv/equiv_miter.cc
View file

@ -82,7 +82,7 @@ struct EquivMiterWorker
for (auto c : source_module->selected_cells())
if (c->type == ID($equiv)) {
log("Seed $equiv cell: %s\n", log_id(c));
log("Seed $equiv cell: %s\n", c);
seed_cells.insert(c);
}
@ -194,11 +194,11 @@ struct EquivMiterWorker
w->port_input = true;
}
if (w->port_output && w->port_input)
log("Created miter inout port %s.\n", log_id(w));
log("Created miter inout port %s.\n", w);
else if (w->port_output)
log("Created miter output port %s.\n", log_id(w));
log("Created miter output port %s.\n", w);
else if (w->port_input)
log("Created miter input port %s.\n", log_id(w));
log("Created miter input port %s.\n", w);
}
miter_module->fixup_ports();
@ -252,7 +252,7 @@ struct EquivMiterWorker
void run()
{
log("Creating miter %s from module %s.\n", log_id(miter_module), log_id(source_module));
log("Creating miter %s from module %s.\n", miter_module, source_module);
find_miter_cells_wires();
copy_to_miter();
make_stuff();
@ -320,7 +320,7 @@ struct EquivMiterPass : public Pass {
extra_args(args, argidx, design);
if (design->module(worker.miter_name))
log_cmd_error("Miter module %s already exists.\n", log_id(worker.miter_name));
log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
worker.source_module = nullptr;
for (auto m : design->selected_modules()) {

6
passes/equiv/equiv_purge.cc
View file

@ -37,7 +37,7 @@ struct EquivPurgeWorker
Wire *wire = sig.as_wire();
if (wire->name.isPublic()) {
if (!wire->port_output) {
log(" Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
wire->port_output = true;
}
return wire;
@ -53,7 +53,7 @@ struct EquivPurgeWorker
Wire *wire = module->addWire(name, GetSize(sig));
wire->port_output = true;
module->connect(wire, sig);
log(" Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
return wire;
}
}
@ -87,7 +87,7 @@ struct EquivPurgeWorker
void run()
{
log("Running equiv_purge on module %s:\n", log_id(module));
log("Running equiv_purge on module %s:\n", module);
for (auto wire : module->wires()) {
wire->port_input = false;

2
passes/equiv/equiv_remove.cc
View file

@ -69,7 +69,7 @@ struct EquivRemovePass : public Pass {
{
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(ID::Y)));
module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell);
remove_count++;

10
passes/equiv/equiv_simple.cc
View file

@ -205,10 +205,10 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
(GetSize(cone_a.cells) + GetSize(cone_b.cells)) - GetSize(cells));
#if 0
for (auto cell : short_cells_cone_a)
log(" A-side cell: %s\n", log_id(cell));
log(" A-side cell: %s\n", cell);
for (auto cell : short_cells_cone_b)
log(" B-side cell: %s\n", log_id(cell));
log(" B-side cell: %s\n", cell);
#endif
}
void report_new_assume_cells(const pool<Cell*>& extra_problem_cells, int old_size, const pool<Cell*>& problem_cells) const
@ -219,7 +219,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
old_size - (GetSize(problem_cells) - GetSize(extra_problem_cells)));
#if 0
for (auto cell : extra_problem_cells)
log(" cell: %s\n", log_id(cell));
log(" cell: %s\n", cell);
#endif
}
}
@ -305,7 +305,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
pool<SigBit> seed_b = { bit_b };
if (cfg.verbose) {
log(" Trying to prove $equiv cell %s:\n", log_id(cell));
log(" Trying to prove $equiv cell %s:\n", cell);
log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(ID::Y)));
} else {
log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(ID::Y)));
@ -477,7 +477,7 @@ struct EquivSimplePass : public Pass {
continue;
log("Found %d unproven $equiv cells (%d groups) in %s:\n",
unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
unproven_cells_counter, GetSize(unproven_equiv_cells), module);
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))

6
passes/equiv/equiv_status.cc
View file

@ -67,17 +67,17 @@ struct EquivStatusPass : public Pass {
}
if (unproven_equiv_cells.empty() && !proven_equiv_cells) {
log("No $equiv cells found in %s.\n", log_id(module));
log("No $equiv cells found in %s.\n", module);
continue;
}
log("Found %d $equiv cells in %s:\n", GetSize(unproven_equiv_cells) + proven_equiv_cells, log_id(module));
log("Found %d $equiv cells in %s:\n", GetSize(unproven_equiv_cells) + proven_equiv_cells, module);
log(" Of those cells %d are proven and %d are unproven.\n", proven_equiv_cells, GetSize(unproven_equiv_cells));
if (unproven_equiv_cells.empty()) {
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
}
unproven_count += GetSize(unproven_equiv_cells);

14
passes/equiv/equiv_struct.cc
View file

@ -79,7 +79,7 @@ struct EquivStructWorker
inputs_a.append(bits_a[i]);
inputs_b.append(bits_b[i]);
input_names.push_back(GetSize(bits_a) == 1 ? port_a.first.str() :
stringf("%s[%d]", log_id(port_a.first), i));
stringf("%s[%d]", port_a.first.unescape(), i));
}
}
@ -111,7 +111,7 @@ struct EquivStructWorker
}
auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
merged_attr.insert(log_id(cell_b));
merged_attr.insert(cell_b->name.unescape());
cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
module->remove(cell_b);
}
@ -144,7 +144,7 @@ struct EquivStructWorker
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
log(" Purging redundant $equiv cell %s.\n", cell);
module->connect(sig_y, sig_a);
module->remove(cell);
merge_count++;
@ -266,9 +266,9 @@ struct EquivStructWorker
run_strategy:
int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
log(" %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
2*GetSize(cell_pairs), log_id(cells_type), total_group_size, strategy);
2*GetSize(cell_pairs), cells_type.unescape(), total_group_size, strategy);
for (auto it : cell_pairs) {
log(" Merging cells %s and %s.\n", log_id(it.first), log_id(it.second));
log(" Merging cells %s and %s.\n", it.first, it.second);
merge_cell_pair(it.first, it.second);
}
}
@ -347,7 +347,7 @@ struct EquivStructPass : public Pass {
for (auto module : design->selected_modules()) {
int module_merge_count = 0;
log("Running equiv_struct on module %s:\n", log_id(module));
log("Running equiv_struct on module %s:\n", module);
for (int iter = 0;; iter++) {
if (iter == max_iter) {
log(" Reached iteration limit of %d.\n", iter);
@ -359,7 +359,7 @@ struct EquivStructPass : public Pass {
module_merge_count += worker.merge_count;
}
if (module_merge_count)
log(" Performed a total of %d merges in module %s.\n", module_merge_count, log_id(module));
log(" Performed a total of %d merges in module %s.\n", module_merge_count, module);
}
}
} EquivStructPass;