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Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id

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Cleaning up log_id()
This commit is contained in:
Miodrag Milanović 2026-05-15 11:07:43 +00:00 • committed by GitHub
commit 36eceed720
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GPG key ID: B5690EEEBB952194
197 changed files with 1311 additions and 1278 deletions
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8
passes/cmds/abstract.cc
View file

@ -67,7 +67,7 @@ struct Slice {
int wire_offset(RTLIL::Wire *wire, int index) const {
int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index);
if (rtl_offset < 0 || rtl_offset >= wire->width) {
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module));
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), wire, wire->module);
}
return rtl_offset;
}
@ -187,7 +187,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
for (int i = 0; i < GetSize(ff.sig_q); i++) {
SigBit bit = ff.sig_q[i];
if (selected_reps.count(sigmap(bit))) {
log_debug("Abstracting state for %s.Q[%i] in module %s due to selections:\n", log_id(ff.cell), i, log_id(mod));
log_debug("Abstracting state for %s.Q[%i] in module %s due to selections:\n", ff.cell, i, mod);
explain_selections(selected_reps.at(sigmap(bit)));
offsets_to_abstract.insert(i);
}
@ -271,7 +271,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
for (int i = 0; i < conn.second.size(); i++) {
if (selected_reps.count(sigmap(conn.second[i]))) {
log_debug("Abstracting value for %s.%s[%i] in module %s due to selections:\n",
log_id(cell), log_id(conn.first), i, log_id(mod));
cell, conn.first.unescape(), i, mod);
explain_selections(selected_reps.at(sigmap(conn.second[i])));
offsets_to_abstract.insert(i);
}
@ -289,7 +289,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
for (auto bit : SigSpec(wire))
if (selected_reps.count(sigmap(bit))) {
log_debug("Abstracting value for module input port bit %s in module %s due to selections:\n",
log_signal(bit), log_id(mod));
log_signal(bit), mod);
explain_selections(selected_reps.at(sigmap(bit)));
offsets_to_abstract.insert(bit.offset);
}

10
passes/cmds/autoname.cc
View file

@ -48,7 +48,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
for (auto bit : conn.second)
if (bit.wire != nullptr && bit.wire->name[0] != '$') {
if (suffix.empty())
suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first));
suffix = stringf("_%s_%s", cell->type.unescape(), conn.first.unescape());
name_proposal proposed_name(
bit.wire->name.str() + suffix,
cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
@ -66,7 +66,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
for (auto bit : conn.second)
if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
if (suffix.empty())
suffix = stringf("_%s", log_id(conn.first));
suffix = stringf("_%s", conn.first.unescape());
name_proposal proposed_name(
cell->name.str() + suffix,
cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
@ -90,7 +90,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
if (best_name < it.second)
continue;
IdString n = module->uniquify(IdString(it.second.name));
log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
log_debug("Rename cell %s in %s to %s.\n", it.first, module, n.unescape());
module->rename(it.first, n);
count++;
}
@ -99,7 +99,7 @@ int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
if (best_name < it.second)
continue;
IdString n = module->uniquify(IdString(it.second.name));
log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
log_debug("Rename wire %s in %s to %s.\n", it.first, module, n.unescape());
module->rename(it.first, n);
count++;
}
@ -151,7 +151,7 @@ struct AutonamePass : public Pass {
count += n;
}
if (count > 0)
log("Renamed %d objects in module %s (%d iterations).\n", count, log_id(module), iter);
log("Renamed %d objects in module %s (%d iterations).\n", count, module, iter);
}
}
} AutonamePass;

4
passes/cmds/box_derive.cc
View file

@ -79,7 +79,7 @@ struct BoxDerivePass : Pass {
if (!base_name.empty()) {
base_override = d->module(base_name);
if (!base_override)
log_cmd_error("Base module %s not found.\n", log_id(base_name));
log_cmd_error("Base module %s not found.\n", base_name.unescape());
}
dict<std::pair<RTLIL::IdString, dict<RTLIL::IdString, RTLIL::Const>>, Module*> done;
@ -109,7 +109,7 @@ struct BoxDerivePass : Pass {
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
if (!new_name.isPublic())
log_error("Derived module %s cannot be renamed to private name %s.\n",
log_id(derived), log_id(new_name));
derived, new_name.unescape());
derived->attributes.erase(naming_attr);
d->rename(derived, new_name);
}

20
passes/cmds/bugpoint.cc
View file

@ -212,7 +212,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove module %s.\n", log_id(module));
log_header(design, "Trying to remove module %s.\n", module);
removed_module = module;
break;
}
@ -242,7 +242,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove module port %s.\n", log_id(wire));
log_header(design, "Trying to remove module port %s.\n", wire);
wire->port_input = wire->port_output = false;
mod->fixup_ports();
return design_copy;
@ -265,7 +265,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove cell %s.%s.\n", log_id(mod), log_id(cell));
log_header(design, "Trying to remove cell %s.%s.\n", mod, cell);
removed_cell = cell;
break;
}
@ -296,7 +296,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove cell port %s.%s.%s.\n", log_id(mod), log_id(cell), log_id(it.first));
log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, it.first.unescape());
RTLIL::SigSpec port_x(State::Sx, port.size());
cell->unsetPort(it.first);
cell->setPort(it.first, port_x);
@ -305,7 +305,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
@ -334,7 +334,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
log_header(design, "Trying to remove process %s.%s.\n", mod, process.first.unescape());
removed_process = process.second;
break;
}
@ -363,7 +363,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
cs->actions.erase(it);
return design_copy;
}
@ -389,7 +389,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, pr.first.unescape());
sy->actions.erase(it);
return design_copy;
}
@ -399,7 +399,7 @@ struct BugpointPass : public Pass {
{
if (index++ == seed)
{
log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), log_id(it->memid), log_signal(it->address), log_signal(it->data), log_signal(it->enable), log_id(mod), log_id(pr.first));
log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), it->memid.unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, pr.first.unescape());
sy->mem_write_actions.erase(it);
// Remove the bit for removed action from other actions' priority masks.
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
@ -437,7 +437,7 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove wire %s.%s.\n", log_id(mod), log_id(wire));
log_header(design, "Trying to remove wire %s.%s.\n", mod, wire);
removed_wire = wire;
break;
}

32
passes/cmds/check.cc
View file

@ -117,7 +117,7 @@ struct CheckPass : public Pass {
for (auto module : design->selected_whole_modules_warn())
{
log("Checking module %s...\n", log_id(module));
log("Checking module %s...\n", module);
SigMap sigmap(module);
dict<SigBit, vector<string>> wire_drivers;
@ -133,7 +133,7 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(action.first))
wire_drivers[bit].push_back(
stringf("action %s <= %s (case rule) in process %s",
log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
log_signal(action.first), log_signal(action.second), proc_it.first.unescape()));
for (auto bit : sigmap(action.second))
if (bit.wire) used_wires.insert(bit);
@ -154,7 +154,7 @@ struct CheckPass : public Pass {
for (auto bit : sigmap(action.first))
wire_drivers[bit].push_back(
stringf("action %s <= %s (sync rule) in process %s",
log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
log_signal(action.first), log_signal(action.second), proc_it.first.unescape()));
for (auto bit : sigmap(action.second))
if (bit.wire) used_wires.insert(bit);
}
@ -259,7 +259,7 @@ struct CheckPass : public Pass {
{
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", module, cell, cell->type.unescape());
counter++;
cell_allowed:;
}
@ -275,10 +275,10 @@ struct CheckPass : public Pass {
if (input && bit.wire)
used_wires.insert(bit);
if (output && !input && bit.wire)
wire_drivers_count[bit]++;
wire_drivers_count[bit]++;
if (output && (bit.wire || !input))
wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", log_id(conn.first), i,
log_id(cell), log_id(cell->type)));
wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", conn.first.unescape(), i,
cell, cell->type.unescape()));
if (output)
driver_cells[bit] = cell;
}
@ -298,7 +298,7 @@ struct CheckPass : public Pass {
SigSpec sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire || !wire->port_output)
wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i));
wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", wire, i));
}
if (wire->port_output)
for (auto bit : sigmap(wire))
@ -312,7 +312,7 @@ struct CheckPass : public Pass {
if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sigmap(SigBit(wire, i)));
if (noinit) {
log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", module, wire);
counter++;
}
}
@ -329,7 +329,7 @@ struct CheckPass : public Pass {
for (auto it : wire_drivers)
if (wire_drivers_count[it.first] > 1) {
string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
string message = stringf("multiple conflicting drivers for %s.%s:\n", module, log_signal(it.first));
for (auto str : it.second)
message += stringf(" %s\n", str);
log_warning("%s", message);
@ -338,13 +338,13 @@ struct CheckPass : public Pass {
for (auto bit : used_wires)
if (!wire_drivers.count(bit)) {
log_warning("Wire %s.%s is used but has no driver.\n", log_id(module), log_signal(bit));
log_warning("Wire %s.%s is used but has no driver.\n", module, log_signal(bit));
counter++;
}
topo.sort();
for (auto &loop : topo.loops) {
string message = stringf("found logic loop in module %s:\n", log_id(module));
string message = stringf("found logic loop in module %s:\n", module);
// `loop` only contains wire bits, or an occasional special helper node for cells for
// which we have done the edges fallback. The cell and its ports that led to an edge are
@ -378,8 +378,8 @@ struct CheckPass : public Pass {
SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
log_id(to_port), to_bit);
message += stringf(" %s[%d] --> %s[%d]\n", from_port.unescape(), from_bit,
to_port.unescape(), to_bit);
if (nhits == HITS_LIMIT)
message += " ...\n";
}
@ -397,7 +397,7 @@ struct CheckPass : public Pass {
driver_src = stringf(" source: %s", src_attr);
}
message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src);
message += stringf(" cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src);
if (!coarsened_cells.count(driver)) {
MatchingEdgePrinter printer(message, sigmap, prev, bit);
@ -437,7 +437,7 @@ struct CheckPass : public Pass {
init_sig.sort_and_unify();
for (auto chunk : init_sig.chunks()) {
log_warning("Wire %s.%s has 'init' attribute and is not driven by an FF cell.\n", log_id(module), log_signal(chunk));
log_warning("Wire %s.%s has 'init' attribute and is not driven by an FF cell.\n", module, log_signal(chunk));
counter++;
}
}

4
passes/cmds/chformal.cc
View file

@ -330,7 +330,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (is_triggered_check_cell(cell))
log_error("Cannot delay edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
log_error("Cannot delay edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
for (int i = 0; i < mode_arg; i++)
{
@ -411,7 +411,7 @@ struct ChformalPass : public Pass {
continue;
if (is_triggered_check_cell(cell))
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell));
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));

2
passes/cmds/connect.cc
View file

@ -122,7 +122,7 @@ struct ConnectPass : public Pass {
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
log_cmd_error("Multiple modules selected: %s, %s\n", module->name.unescape(), mod->name.unescape());
module = mod;
}
if (module == nullptr)

4
passes/cmds/connwrappers.cc
View file

@ -134,8 +134,8 @@ struct ConnwrappersWorker
}
if (old_sig.size())
log("Connected extended bits of %s.%s:%s: %s -> %s\n", log_id(module->name), log_id(cell->name),
log_id(conn.first), log_signal(old_sig), log_signal(conn.second));
log("Connected extended bits of %s.%s:%s: %s -> %s\n", module->name.unescape(), cell->name.unescape(),
conn.first.unescape(), log_signal(old_sig), log_signal(conn.second));
}
}
}

4
passes/cmds/design.cc
View file

@ -266,7 +266,7 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules)
{
log("Importing %s as %s.\n", log_id(mod), log_id(prefix));
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
RTLIL::Module *t = mod->clone();
t->name = prefix;
@ -295,7 +295,7 @@ struct DesignPass : public Pass {
{
std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\'));
log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));
log("Importing %s as %s.\n", fmod, RTLIL::unescape_id(trg_name));
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));

72
passes/cmds/design_equal.cc
View file

@ -38,9 +38,9 @@ public:
[[noreturn]]
void formatted_error(std::string err)
{
log("Module A: %s\n", log_id(mod_a->name));
log("Module A: %s\n", mod_a->name.unescape());
log_module(mod_a, " ");
log("Module B: %s\n", log_id(mod_b->name));
log("Module B: %s\n", mod_b->name.unescape());
log_module(mod_b, " ");
log_cmd_error("Designs are different: %s\n", err);
}
@ -68,20 +68,20 @@ public:
{
for (const auto &it : a->attributes) {
if (b->attributes.count(it.first) == 0)
return "missing attribute " + std::string(log_id(it.first)) + " in second design";
return "missing attribute " + std::string(it.first.unescape()) + " in second design";
if (it.second != b->attributes.at(it.first))
return "attribute " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
return "attribute " + std::string(it.first.unescape()) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
}
for (const auto &it : b->attributes)
if (a->attributes.count(it.first) == 0)
return "missing attribute " + std::string(log_id(it.first)) + " in first design";
return "missing attribute " + std::string(it.first.unescape()) + " in first design";
return "";
}
std::string compare_wires(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->name != b->name)
return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (a->width != b->width)
return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
if (a->start_offset != b->start_offset)
@ -105,19 +105,19 @@ public:
{
for (const auto &it : mod_a->wires_) {
if (mod_b->wires_.count(it.first) == 0)
error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing wire %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty())
error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
error("Module %s wire %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
}
for (const auto &it : mod_b->wires_)
if (mod_a->wires_.count(it.first) == 0)
error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing wire %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b)
{
if (a->name != b->name)
return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (a->width != b->width)
return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
if (a->start_offset != b->start_offset)
@ -132,31 +132,31 @@ public:
std::string compare_cells(const RTLIL::Cell *a, const RTLIL::Cell *b)
{
if (a->name != b->name)
return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (a->type != b->type)
return "type mismatch: " + std::string(log_id(a->type)) + " != " + log_id(b->type);
return "type mismatch: " + std::string(a->type.unescape()) + " != " + b->type.unescape();
if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
return mismatch;
for (const auto &it : a->parameters) {
if (b->parameters.count(it.first) == 0)
return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in second design";
return "parameter mismatch: missing parameter " + std::string(it.first.unescape()) + " in second design";
if (it.second != b->parameters.at(it.first))
return "parameter mismatch: " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
return "parameter mismatch: " + std::string(it.first.unescape()) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
}
for (const auto &it : b->parameters)
if (a->parameters.count(it.first) == 0)
return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in first design";
return "parameter mismatch: missing parameter " + std::string(it.first.unescape()) + " in first design";
for (const auto &it : a->connections()) {
if (b->connections().count(it.first) == 0)
return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in second design";
return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in second design";
if (!compare_sigspec(it.second, b->connections().at(it.first)))
return "connection " + std::string(log_id(it.first)) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
return "connection " + std::string(it.first.unescape()) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
}
for (const auto &it : b->connections())
if (a->connections().count(it.first) == 0)
return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in first design";
return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in first design";
return "";
}
@ -165,26 +165,26 @@ public:
{
for (const auto &it : mod_a->cells_) {
if (mod_b->cells_.count(it.first) == 0)
error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing cell %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty())
error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
error("Module %s cell %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
}
for (const auto &it : mod_b->cells_)
if (mod_a->cells_.count(it.first) == 0)
error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing cell %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
void check_memories()
{
for (const auto &it : mod_a->memories) {
if (mod_b->memories.count(it.first) == 0)
error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing memory %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty())
error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
error("Module %s memory %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch);
}
for (const auto &it : mod_b->memories)
if (mod_a->memories.count(it.first) == 0)
error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing memory %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b)
@ -251,7 +251,7 @@ public:
const auto &ma = a->mem_write_actions[i];
const auto &mb = b->mem_write_actions[i];
if (ma.memid != mb.memid)
return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + log_id(ma.memid) + " != " + log_id(mb.memid);
return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + ma.memid.unescape() + " != " + mb.memid.unescape();
if (!compare_sigspec(ma.address, mb.address))
return "mem_write_actions " + std::to_string(i) + " address mismatch: " + log_signal(ma.address) + " != " + log_signal(mb.address);
if (!compare_sigspec(ma.data, mb.data))
@ -268,7 +268,7 @@ public:
std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b)
{
if (a->name != b->name) return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
if (a->name != b->name) return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape();
if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
return mismatch;
if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty())
@ -285,13 +285,13 @@ public:
{
for (auto &it : mod_a->processes) {
if (mod_b->processes.count(it.first) == 0)
error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first));
error("Module %s missing process %s in second design.\n", mod_a->name.unescape(), it.first.unescape());
if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty())
error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str());
error("Module %s process %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch.c_str());
}
for (auto &it : mod_b->processes)
if (mod_a->processes.count(it.first) == 0)
error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first));
error("Module %s missing process %s in first design.\n", mod_b->name.unescape(), it.first.unescape());
}
void check_connections()
@ -299,13 +299,13 @@ public:
const auto &conns_a = mod_a->connections();
const auto &conns_b = mod_b->connections();
if (conns_a.size() != conns_b.size()) {
error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size());
error("Module %s connection count differs: %zu != %zu\n", mod_a->name.unescape(), conns_a.size(), conns_b.size());
} else {
for (size_t i = 0; i < conns_a.size(); i++) {
if (!compare_sigspec(conns_a[i].first, conns_b[i].first))
error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
error("Module %s connection %zu LHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
if (!compare_sigspec(conns_a[i].second, conns_b[i].second))
error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
error("Module %s connection %zu RHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
}
}
}
@ -313,9 +313,9 @@ public:
void check()
{
if (mod_a->name != mod_b->name)
error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name));
error("Modules have different names: %s != %s\n", mod_a->name.unescape(), mod_b->name.unescape());
if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty())
error("Module %s %s.\n", log_id(mod_a->name), mismatch);
error("Module %s %s.\n", mod_a->name.unescape(), mismatch);
check_wires();
check_cells();
check_memories();
@ -349,7 +349,7 @@ struct DesignEqualPass : public Pass {
for (auto &it : design->modules_) {
RTLIL::Module *mod = it.second;
if (!other->has(mod->name))
log_error("Second design missing module %s.\n", log_id(mod->name));
log_error("Second design missing module %s.\n", mod->name.unescape());
ModuleComparator cmp(mod, other->module(mod->name));
cmp.check();
@ -357,7 +357,7 @@ struct DesignEqualPass : public Pass {
for (auto &it : other->modules_) {
RTLIL::Module *mod = it.second;
if (!design->has(mod->name))
log_error("First design missing module %s.\n", log_id(mod->name));
log_error("First design missing module %s.\n", mod->name.unescape());
}
log("Designs are identical.\n");

12
passes/cmds/dft_tag.cc
View file

@ -98,7 +98,7 @@ struct DftTagWorker {
}
for (auto cell : overwrite_cells) {
log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A)));
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
@ -470,9 +470,9 @@ struct DftTagWorker {
if (!warned_cells.insert(cell).second)
return;
if (cell->type.isPublic())
log_warning("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s) during tag propagation\n", cell, cell->type.unescape());
else
log_debug("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
log_debug("Unhandled cell %s (%s) during tag propagation\n", cell, cell->type.unescape());
}
void process_cell(IdString tag, Cell *cell)
@ -691,7 +691,7 @@ struct DftTagWorker {
// TODO handle some more variants
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
if (ff.has_clk && !tags(ff.sig_clk).empty())
log_warning("Tags on CLK input ignored for %s (%s)\n", log_id(cell), log_id(cell->type));
log_warning("Tags on CLK input ignored for %s (%s)\n", cell, cell->type.unescape());
int width = ff.width;
@ -709,7 +709,7 @@ struct DftTagWorker {
emit_tag_signal(tag, sig_q, ff.sig_q);
return;
} else {
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
// For unhandled FFs, the default propagation would cause combinational loops
emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
@ -739,7 +739,7 @@ struct DftTagWorker {
// which is an over-approximation (unless the cell is a module that
// generates tags itself in which case it could be arbitrary).
if (warned_cells.insert(cell).second)
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", cell, cell->type.unescape());
}
void emit_tags()

8
passes/cmds/edgetypes.cc
View file

@ -92,12 +92,12 @@ struct EdgetypePass : public Pass {
auto sink_bit_index = std::get<2>(sink);
string source_str = multibit_ports.count(std::pair<IdString, IdString>(source_cell_type, source_port_name)) ?
stringf("%s.%s[%d]", log_id(source_cell_type), log_id(source_port_name), source_bit_index) :
stringf("%s.%s", log_id(source_cell_type), log_id(source_port_name));
stringf("%s.%s[%d]", source_cell_type.unescape(), source_port_name.unescape(), source_bit_index) :
stringf("%s.%s", source_cell_type.unescape(), source_port_name.unescape());
string sink_str = multibit_ports.count(std::pair<IdString, IdString>(sink_cell_type, sink_port_name)) ?
stringf("%s.%s[%d]", log_id(sink_cell_type), log_id(sink_port_name), sink_bit_index) :
stringf("%s.%s", log_id(sink_cell_type), log_id(sink_port_name));
stringf("%s.%s[%d]", sink_cell_type.unescape(), sink_port_name.unescape(), sink_bit_index) :
stringf("%s.%s", sink_cell_type.unescape(), sink_port_name.unescape());
edge_cache.insert(source_str + " " + sink_str);
}

10
passes/cmds/example_dt.cc
View file

@ -226,13 +226,13 @@ struct ExampleDtPass : public Pass
{
auto ref = compute_graph[i];
log("n%d ", i);
log("%s", log_id(ref.function().name));
log("%s", ref.function().name.unescape());
for (auto const &param : ref.function().parameters)
{
if (param.second.empty())
log("[%s]", log_id(param.first));
log("[%s]", param.first.unescape());
else
log("[%s=%s]", log_id(param.first), log_const(param.second));
log("[%s=%s]", param.first.unescape(), log_const(param.second));
}
log("(");
@ -244,13 +244,13 @@ struct ExampleDtPass : public Pass
}
log(")\n");
if (ref.has_sparse_attr())
log("// wire %s\n", log_id(ref.sparse_attr()));
log("// wire %s\n", ref.sparse_attr().unescape());
log("// was #%d %s\n", ref.attr(), log_signal(queue[ref.attr()]));
}
for (auto const &key : compute_graph.keys())
{
log("return %d as %s \n", key.second, log_id(key.first));
log("return %d as %s \n", key.second, key.first.unescape());
}
}
log("Plugin test passed!\n");

4
passes/cmds/future.cc
View file

@ -86,13 +86,13 @@ struct FutureWorker {
log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
auto driver = *found_driver->second.begin();
if (!driver.cell->is_builtin_ff() && driver.cell->type != ID($anyinit))
log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), driver.cell->type.unescape());
FfData ff(&initvals, driver.cell);
if (!ff.has_clk && !ff.has_gclk)
log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
log_id(driver.cell->type));
driver.cell->type.unescape());
ff.unmap_ce_srst();

6
passes/cmds/linecoverage.cc
View file

@ -93,9 +93,9 @@ struct CoveragePass : public Pass {
for (auto module : design->modules())
{
log_debug("Module %s:\n", log_id(module));
log_debug("Module %s:\n", module);
for (auto wire: module->wires()) {
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), log_id(wire->name));
log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), wire->name.unescape());
for (auto src: wire->get_strpool_attribute(ID::src)) {
auto filename = extract_src_filename(src);
if (filename.empty()) continue;
@ -109,7 +109,7 @@ struct CoveragePass : public Pass {
}
}
for (auto cell: module->cells()) {
log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), log_id(cell->name));
log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), cell->name.unescape());
for (auto src: cell->get_strpool_attribute(ID::src)) {
auto filename = extract_src_filename(src);
if (filename.empty()) continue;

8
passes/cmds/ltp.cc
View file

@ -90,7 +90,7 @@ struct LtpWorker
return;
if (busy.count(bit) > 0) {
log_warning("Detected loop at %s in %s\n", log_signal(bit), log_id(module));
log_warning("Detected loop at %s in %s\n", log_signal(bit), module);
return;
}
@ -117,7 +117,7 @@ struct LtpWorker
auto &bitinfo = bits.at(bit);
if (get<2>(bitinfo)) {
printpath(get<1>(bitinfo));
log("%5d: %s (via %s)\n", get<0>(bitinfo), log_signal(bit), log_id(get<2>(bitinfo)));
log("%5d: %s (via %s)\n", get<0>(bitinfo), log_signal(bit), get<2>(bitinfo));
} else {
log("%5d: %s\n", get<0>(bitinfo), log_signal(bit));
}
@ -130,13 +130,13 @@ struct LtpWorker
runner(it.first, 0, State::Sx, nullptr);
log("\n");
log("Longest topological path in %s (length=%d):\n", log_id(module), maxlvl);
log("Longest topological path in %s (length=%d):\n", module, maxlvl);
if (maxlvl >= 0)
printpath(maxbit);
if (bit2ff.count(maxbit))
log("%5s: %s (via %s)\n", "ff", log_signal(get<0>(bit2ff.at(maxbit))), log_id(get<1>(bit2ff.at(maxbit))));
log("%5s: %s (via %s)\n", "ff", log_signal(get<0>(bit2ff.at(maxbit))), get<1>(bit2ff.at(maxbit)));
}
};

6
passes/cmds/portarcs.cc
View file

@ -107,7 +107,7 @@ struct PortarcsPass : Pass {
log_assert(w->port_input || w->port_output);
if (w->port_input && w->port_output) {
log_warning("Module '%s' with ambiguous direction on port %s ignored.\n",
log_id(m), log_id(w));
m, w);
ambiguous_ports = true;
break;
}
@ -128,7 +128,7 @@ struct PortarcsPass : Pass {
if (!cell->type.in(ID($buf), ID($input_port), ID($connect), ID($tribuf))) {
auto tdata = tinfo.find(cell->type);
if (tdata == tinfo.end())
log_cmd_error("Missing timing data for module '%s'.\n", log_id(cell->type));
log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());
for (auto [edge, delay] : tdata->second.comb) {
auto from = edge.first.get_connection(cell);
auto to = edge.second.get_connection(cell);
@ -141,7 +141,7 @@ struct PortarcsPass : Pass {
}
if (!sort.sort())
log_error("Failed to sort instances in module %s.\n", log_id(m));
log_error("Failed to sort instances in module %s.\n", m);
ordering = sort.sorted;
}

4
passes/cmds/portlist.cc
View file

@ -71,9 +71,9 @@ struct PortlistPass : public Pass {
ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
w->upto ? w->start_offset : w->start_offset + w->width - 1,
w->upto ? w->start_offset + w->width - 1 : w->start_offset,
log_id(w)));
w));
}
log("module %s%s\n", log_id(module), m_mode ? " (" : "");
log("module %s%s\n", module, m_mode ? " (" : "");
for (int i = 0; i < GetSize(ports); i++)
log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : "");
if (m_mode)

10
passes/cmds/printattrs.cc
View file

@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), s.unescape(), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string());
log("%s(* %s=%s *)\n", get_indent_str(indent), s.unescape(), x.as_string());
else
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass {
for (auto mod : design->selected_modules())
{
if (design->selected_whole_module(mod)) {
log("%s%s\n", get_indent_str(indent), log_id(mod->name));
log("%s%s\n", get_indent_str(indent), mod->name.unescape());
indent += 2;
for (auto &it : mod->attributes)
log_const(it.first, it.second, indent);
}
for (auto cell : mod->selected_cells()) {
log("%s%s\n", get_indent_str(indent), log_id(cell->name));
log("%s%s\n", get_indent_str(indent), cell->name.unescape());
indent += 2;
for (auto &it : cell->attributes)
log_const(it.first, it.second, indent);
@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass {
}
for (auto wire : mod->selected_wires()) {
log("%s%s\n", get_indent_str(indent), log_id(wire->name));
log("%s%s\n", get_indent_str(indent), wire->name.unescape());
indent += 2;
for (auto &it : wire->attributes)
log_const(it.first, it.second, indent);

12
passes/cmds/rename.cc
View file

@ -31,13 +31,13 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
to_name = RTLIL::escape_id(to_name);
if (module->count_id(to_name))
log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name, module->name);
log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), module->name);
RTLIL::Wire *wire_to_rename = module->wire(from_name);
RTLIL::Cell *cell_to_rename = module->cell(from_name);
if (wire_to_rename != nullptr) {
log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), log_id(to_name), log_id(module));
log("Renaming wire %s to %s in module %s.\n", wire_to_rename, RTLIL::unescape_id(to_name), module);
module->rename(wire_to_rename, to_name);
if (wire_to_rename->port_id || flag_output) {
if (flag_output)
@ -50,12 +50,12 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
if (cell_to_rename != nullptr) {
if (flag_output)
log_cmd_error("Called with -output but the specified object is a cell.\n");
log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), log_id(to_name), log_id(module));
log("Renaming cell %s to %s in module %s.\n", cell_to_rename, RTLIL::unescape_id(to_name), module);
module->rename(cell_to_rename, to_name);
return;
}
log_cmd_error("Object `%s' not found!\n", from_name);
log_cmd_error("Object `%s' not found!\n", RTLIL::unescape_id(from_name));
}
static std::string derive_name_from_src(const std::string &src, int counter)
@ -518,7 +518,7 @@ struct RenamePass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found!\n");
log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
log("Renaming module %s to %s.\n", module, new_name.unescape());
design->rename(module, new_name);
}
else
@ -532,7 +532,7 @@ struct RenamePass : public Pass {
for (auto module : design->selected_modules())
{
if (module->memories.size() != 0 || module->processes.size() != 0) {
log_warning("Skipping module %s with unprocessed memories or processes\n", log_id(module));
log_warning("Skipping module %s with unprocessed memories or processes\n", module);
continue;
}

2
passes/cmds/sdc/sdc.cc
View file

@ -168,7 +168,7 @@ struct SdcObjects {
RTLIL::Wire *wire = top->wire(port);
if (!wire) {
// This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573
log_error("Port %s doesn't exist", log_id(port));
log_error("Port %s doesn't exist", port.unescape());
}
design_ports.push_back(std::make_pair(port.str().substr(1), wire));
}

2
passes/cmds/select.cc
View file

@ -1817,7 +1817,7 @@ struct LsPass : public Pass {
log("\n%d %s:\n", int(matches.size()), "modules");
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
for (auto id : matches)
log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(id)) ? "" : "*");
log(" %s%s\n", id.unescape(), design->selected_whole_module(design->module(id)) ? "" : "*");
}
}
else

4
passes/cmds/setattr.cc
View file

@ -246,9 +246,9 @@ struct ChparamPass : public Pass {
if (!new_parameters.empty())
log_cmd_error("The options -set and -list cannot be used together.\n");
for (auto module : design->selected_modules()) {
log("%s:\n", log_id(module));
log("%s:\n", module);
for (auto param : module->avail_parameters)
log(" %s\n", log_id(param));
log(" %s\n", param.unescape());
}
return;
}

8
passes/cmds/show.cc
View file

@ -645,16 +645,16 @@ struct ShowWorker
module = mod;
if (design->selected_whole_module(module->name)) {
if (module->get_blackbox_attribute()) {
// log("Skipping blackbox module %s.\n", log_id(module->name));
//log("Skipping blackbox module %s.\n", module->name.unescape());
continue;
} else
if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", log_id(module->name));
log("Skipping empty module %s.\n", module->name.unescape());
continue;
} else
log("Dumping module %s to page %d.\n", log_id(module->name), ++page_counter);
log("Dumping module %s to page %d.\n", module->name.unescape(), ++page_counter);
} else
log("Dumping selected parts of module %s to page %d.\n", log_id(module->name), ++page_counter);
log("Dumping selected parts of module %s to page %d.\n", module->name.unescape(), ++page_counter);
handle_module();
}
}

2
passes/cmds/splice.cc
View file

@ -149,7 +149,7 @@ struct SpliceWorker
void run()
{
log("Splicing signals in module %s:\n", log_id(module->name));
log("Splicing signals in module %s:\n", module->name.unescape());
driven_bits.push_back(RTLIL::State::Sm);
driven_bits.push_back(RTLIL::State::Sm);

10
passes/cmds/splitcells.cc
View file

@ -89,7 +89,7 @@ struct SplitcellsWorker
if (GetSize(slices) <= 1) return 0;
slices.push_back(GetSize(outsig));
log("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
log("Splitting %s cell %s/%s into %d slices:\n", cell->type.unescape(), module, cell, GetSize(slices)-1);
for (int i = 1; i < GetSize(slices); i++)
{
int slice_msb = slices[i]-1;
@ -126,7 +126,7 @@ struct SplitcellsWorker
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y)));
}
module->remove(cell);
@ -155,7 +155,7 @@ struct SplitcellsWorker
if (GetSize(slices) <= 1) return 0;
slices.push_back(GetSize(outsig));
log("Splitting %s cell %s/%s into %d slices:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(slices)-1);
log("Splitting %s cell %s/%s into %d slices:\n", cell->type.unescape(), module, cell, GetSize(slices)-1);
for (int i = 1; i < GetSize(slices); i++)
{
int slice_msb = slices[i]-1;
@ -185,7 +185,7 @@ struct SplitcellsWorker
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, log_id(slice_name), log_signal(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q)));
}
module->remove(cell);
@ -258,7 +258,7 @@ struct SplitcellsPass : public Pass {
if (count_split_pre)
log("Split %d cells in module %s into %d cell slices.\n",
count_split_pre, log_id(module), count_split_post);
count_split_pre, module, count_split_post);
}
}
} SplitnetsPass;

16
passes/cmds/sta.cc
View file

@ -66,12 +66,12 @@ struct StaWorker
Module *inst_module = design->module(cell->type);
if (!inst_module) {
if (unrecognised_cells.insert(cell->type).second)
log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
log_warning("Cell type '%s' not recognised! Ignoring.\n", cell->type.unescape());
continue;
}
if (!inst_module->get_blackbox_attribute()) {
log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", log_id(cell->type));
log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", cell->type.unescape());
continue;
}
@ -82,7 +82,7 @@ struct StaWorker
if (!timing.count(derived_type)) {
auto &t = timing.setup_module(inst_module);
if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type));
log_warning("Module '%s' has no timing arcs!\n", cell->type.unescape());
}
auto &t = timing.at(derived_type);
@ -203,10 +203,10 @@ struct StaWorker
return;
}
log("Latest arrival time in '%s' is %d:\n", log_id(module), maxarrival);
log("Latest arrival time in '%s' is %d:\n", module, maxarrival);
auto it = endpoints.find(maxbit);
if (it != endpoints.end() && it->second.sink)
log(" %6d %s (%s.%s)\n", maxarrival, log_id(it->second.sink), log_id(it->second.sink->type), log_id(it->second.port));
log(" %6d %s (%s.%s)\n", maxarrival, it->second.sink, it->second.sink->type.unescape(), it->second.port.unescape());
else {
log(" %6d (%s)\n", maxarrival, b.wire->port_output ? "<primary output>" : "<unknown>");
if (!b.wire->port_output)
@ -217,7 +217,7 @@ struct StaWorker
int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
if (jt->second.driver) {
log(" %s\n", log_signal(b));
log(" %6d %s (%s.%s->%s)\n", arrival, log_id(jt->second.driver), log_id(jt->second.driver->type), log_id(jt->second.src_port), log_id(jt->second.dst_port));
log(" %6d %s (%s.%s->%s)\n", arrival, jt->second.driver, jt->second.driver->type.unescape(), jt->second.src_port.unescape(), jt->second.dst_port.unescape());
}
else if (b.wire->port_input)
log(" %6d %s (%s)\n", arrival, log_signal(b), "<primary input>");
@ -234,13 +234,13 @@ struct StaWorker
continue;
if (!b.wire->attributes.count(ID::sta_arrival)) {
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", log_id(module), log_signal(b));
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", module, log_signal(b));
continue;
}
auto arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
if (arrival < 0) {
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", log_id(module), log_signal(b));
log_warning("Endpoint %s.%s has no (* sta_arrival *) value.\n", module, log_signal(b));
continue;
}
arrival += i.second.required;

22
passes/cmds/stat.cc
View file

@ -523,7 +523,7 @@ struct statdata_t {
print_log_line("cells", local_num_cells, local_area, num_cells, area, 0, print_area, print_hierarchical, print_global_only);
for (auto &it : num_cells_by_type)
if (it.second) {
auto name = string(log_id(it.first));
auto name = string(it.first.unescape());
print_log_line(name, local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
area_cells_by_type.at(it.first), 1, print_area, print_hierarchical, print_global_only);
@ -533,7 +533,7 @@ struct statdata_t {
print_global_only);
for (auto &it : num_submodules_by_type)
if (it.second)
print_log_line(string(log_id(it.first)), it.second, 0, it.second,
print_log_line(string(it.first.unescape()), it.second, 0, it.second,
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0, 1,
print_area, print_hierarchical, print_global_only);
}
@ -607,7 +607,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
log(" %s: %s", json11::Json(it.first.unescape()).dump(),
json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
area_cells_by_type.at(it.first))
@ -621,7 +621,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
log(" %s: %s", json11::Json(it.first.unescape()).dump(),
json_line(0, 0, it.second,
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
.c_str());
@ -662,14 +662,14 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
first_line = false;
}
log("\n");
@ -697,14 +697,14 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
log(" %s: %u", json11::Json(it.first.unescape()).dump(), it.second);
first_line = false;
}
log("\n");
@ -734,7 +734,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
for (auto &it : mod_data.num_submodules_by_type) {
if (mod_stat.count(it.first) > 0) {
if (!quiet)
mod_data.print_log_line(string(log_id(it.first)), mod_stat.at(it.first).local_num_cells,
mod_data.print_log_line(string(it.first.unescape()), mod_stat.at(it.first).local_num_cells,
mod_stat.at(it.first).local_area, mod_stat.at(it.first).num_cells, mod_stat.at(it.first).area,
level, has_area, hierarchy_mode);
hierarchy_worker(mod_stat, it.first, level + 1, quiet, has_area, hierarchy_mode) * it.second;
@ -1009,7 +1009,7 @@ struct StatPass : public Pass {
first_module = false;
} else {
log("\n");
log("=== %s%s ===\n", log_id(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
log("=== %s%s ===\n", mod->name.unescape(), mod->is_selected_whole() ? "" : " (partially selected)");
log("\n");
data.log_data(mod->name, false, has_area, hierarchy_mode);
}
@ -1026,7 +1026,7 @@ struct StatPass : public Pass {
log("=== design hierarchy ===\n");
log("\n");
mod_stat[top_mod->name].print_log_header(has_area, hierarchy_mode, true);
mod_stat[top_mod->name].print_log_line(log_id(top_mod->name), mod_stat[top_mod->name].local_num_cells,
mod_stat[top_mod->name].print_log_line(top_mod->name.unescape(), mod_stat[top_mod->name].local_num_cells,
mod_stat[top_mod->name].local_area, mod_stat[top_mod->name].num_cells,
mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode, true);
}

16
passes/cmds/timeest.cc
View file

@ -83,7 +83,7 @@ struct EstimateSta {
void run()
{
log("\nModule %s\n", log_id(m));
log("\nModule %s\n", m);
if (clk.has_value())
log("Domain %s\n", log_signal(*clk));
@ -97,7 +97,7 @@ struct EstimateSta {
FfData ff(nullptr, cell);
if (!ff.has_clk) {
log_warning("Ignoring unsupported storage element '%s' (%s)\n",
log_id(cell), log_id(cell->type));
cell, cell->type.unescape());
continue;
}
if (ff.sig_clk != clk)
@ -121,7 +121,7 @@ struct EstimateSta {
aigs.emplace(fingerprint, Aig(cell));
if (aigs.at(fingerprint).name.empty()) {
log_error("Unsupported cell '%s' in module '%s'",
log_id(cell->type), log_id(m));
cell->type.unescape(), m);
}
}
@ -141,7 +141,7 @@ struct EstimateSta {
for (auto &mem : Mem::get_all_memories(m)) {
for (auto &rd : mem.rd_ports) {
if (!rd.clk_enable) {
log_error("Unsupported async memory port '%s'\n", log_id(rd.cell));
log_error("Unsupported async memory port '%s'\n", rd.cell);
continue;
}
if (sigmap(rd.clk) != clk)
@ -165,7 +165,7 @@ struct EstimateSta {
} else if (port->port_output && !port->port_input) {
all_outputs.append(port);
} else if (port->port_output && port->port_input) {
log_warning("Ignoring bi-directional port %s\n", log_id(port));
log_warning("Ignoring bi-directional port %s\n", port);
}
}
add_seq(nullptr, all_inputs, all_outputs);
@ -216,7 +216,7 @@ struct EstimateSta {
}
if (!topo.sort())
log_error("Module '%s' contains combinational loops", log_id(m));
log_error("Module '%s' contains combinational loops", m);
// now we determine how long it takes for signals to stabilize
@ -342,7 +342,7 @@ struct EstimateSta {
std::string src_attr = cell->get_src_attribute();
cell_src = stringf(" source: %s", src_attr);
}
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src);
log(" cell %s (%s)%s\n", cell, cell->type.unescape(), cell_src);
printed.insert(cell);
}
} else {
@ -425,7 +425,7 @@ struct TimeestPass : Pass {
if (clk_domain_specified) {
if (!m->wire(RTLIL::escape_id(clk_name))) {
log_warning("No domain '%s' in module %s\n", clk_name.c_str(), log_id(m));
log_warning("No domain '%s' in module %s\n", clk_name.c_str(), m);
continue;
}

6
passes/cmds/torder.cc
View file

@ -74,7 +74,7 @@ struct TorderPass : public Pass {
for (auto module : design->selected_modules())
{
log("module %s\n", log_id(module));
log("module %s\n", module);
SigMap sigmap(module);
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
@ -116,12 +116,12 @@ struct TorderPass : public Pass {
for (auto &it : toposort.loops) {
log(" loop");
for (auto cell : it)
log(" %s", log_id(cell));
log(" %s", cell);
log("\n");
}
for (auto cell : toposort.sorted)
log(" cell %s\n", log_id(cell));
log(" cell %s\n", cell);
}
}
} TorderPass;

12
passes/cmds/trace.cc
View file

@ -28,34 +28,34 @@ struct TraceMonitor : public RTLIL::Monitor
{
void notify_module_add(RTLIL::Module *module) override
{
log("#TRACE# Module add: %s\n", log_id(module));
log("#TRACE# Module add: %s\n", module);
}
void notify_module_del(RTLIL::Module *module) override
{
log("#TRACE# Module delete: %s\n", log_id(module));
log("#TRACE# Module delete: %s\n", module);
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
}
void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
{
log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
log("#TRACE# Connection in module %s: %s = %s\n", module, log_signal(sigsig.first), log_signal(sigsig.second));
}
void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override
{
log("#TRACE# New connections in module %s:\n", log_id(module));
log("#TRACE# New connections in module %s:\n", module);
for (auto &sigsig : sigsig_vec)
log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
}
void notify_blackout(RTLIL::Module *module) override
{
log("#TRACE# Blackout in module %s:\n", log_id(module));
log("#TRACE# Blackout in module %s:\n", module);
}
};

8
passes/cmds/viz.cc
View file

@ -279,7 +279,7 @@ struct Graph {
Graph(Module *module, const VizConfig &config) : module(module), config(config)
{
log("Running 'viz -%d' for module %s:\n", config.effort, log_id(module));
log("Running 'viz -%d' for module %s:\n", config.effort, module);
log(" Phase %d: Construct initial graph\n", phase_counter++);
SigMap sigmap(module);
@ -718,7 +718,7 @@ struct VizWorker
void write_dot(FILE *f)
{
fprintf(f, "digraph \"%s\" {\n", log_id(module));
fprintf(f, "digraph \"%s\" {\n", module->name.unescape().c_str());
fprintf(f, " rankdir = LR;\n");
dict<GraphNode*, std::vector<std::vector<std::string>>> extra_lines;
@ -734,7 +734,7 @@ struct VizWorker
buffer.emplace_back();
for (auto name : g->names())
buffer.back().push_back(log_id(name));
buffer.back().push_back(name.unescape());
std::sort(buffer.back().begin(), buffer.back().end());
std::sort(buffer.begin(), buffer.end());
@ -782,7 +782,7 @@ struct VizWorker
g->names().sort();
std::string label; // = stringf("vg=%d\\n", g->index);
for (auto n : g->names())
label = label + (label.empty() ? "" : "\\n") + log_id(n);
label = label + (label.empty() ? "" : "\\n") + n.unescape();
fprintf(f, "\tn%d [shape=rectangle,label=\"%s\"];\n", g->index, label.c_str());
} else {
std::string label = stringf("vg=%d | %d cells", g->index, GetSize(g->names()));

8
passes/cmds/wrapcell.cc
View file

@ -70,7 +70,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
} else {
auto id = RTLIL::escape_id(std::string(beg, it));
if (!parameters.count(id)) {
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt);
log("Parameter %s referenced in format string '%s' not found\n", id, fmt);
return {};
}
@ -210,7 +210,7 @@ struct WrapcellPass : Pass {
if (!ct.cell_known(cell->type))
log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
for (auto conn : cell->connections()) {
@ -233,7 +233,7 @@ struct WrapcellPass : Pass {
std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
if (!unescaped_name)
log_error("Formatting error when processing cell '%s' in module '%s'\n",
log_id(cell), log_id(module));
cell, module);
IdString name = RTLIL::escape_id(unescaped_name.value());
if (d->module(name))
@ -274,7 +274,7 @@ struct WrapcellPass : Pass {
if (!value)
log_error("Formatting error when processing cell '%s' in module '%s'\n",
log_id(cell), log_id(module));
cell, module);
subm->set_string_attribute(rule.name, value.value());
}

12
passes/cmds/xprop.cc
View file

@ -467,7 +467,7 @@ struct XpropWorker
return;
}
log_warning("Unhandled cell %s (%s) during maybe-x marking\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s) during maybe-x marking\n", cell, cell->type.unescape());
mark_outputs_maybe_x(cell);
}
@ -862,7 +862,7 @@ struct XpropWorker
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
if (ff.has_clk && maybe_x(ff.sig_clk)) {
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", log_id(cell), log_id(cell->type));
log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", cell, cell->type.unescape());
} else {
auto init_q = ff.val_init;
auto init_q_is_1 = init_q;
@ -907,7 +907,7 @@ struct XpropWorker
return;
}
} else {
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", cell, cell->type.unescape());
}
}
@ -964,9 +964,9 @@ struct XpropWorker
log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
if (options.required)
log_error("Unhandled cell %s (%s)\n", log_id(cell), log_id(cell->type));
log_error("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
else
log_warning("Unhandled cell %s (%s)\n", log_id(cell), log_id(cell->type));
log_warning("Unhandled cell %s (%s)\n", cell, cell->type.unescape());
}
void split_ports()
@ -980,7 +980,7 @@ struct XpropWorker
auto wire = module->wire(port);
if (module->design->selected(module, wire)) {
if (wire->port_input == wire->port_output) {
log_warning("Port %s not an input or an output port which is not supported by xprop\n", log_id(wire));
log_warning("Port %s not an input or an output port which is not supported by xprop\n", wire);
} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
auto port_d = module->uniquify(stringf("%s_d", port));
auto port_x = module->uniquify(stringf("%s_x", port));

4
passes/equiv/equiv_induct.cc
View file

@ -84,7 +84,7 @@ struct EquivInductWorker : public EquivWorker<>
void run()
{
log("Found %d unproven $equiv cells in module %s:\n", GetSize(workset), log_id(module));
log("Found %d unproven $equiv cells in module %s:\n", GetSize(workset), module);
if (satgen.model_undef) {
for (auto cell : cells)
@ -217,7 +217,7 @@ struct EquivInductPass : public Pass {
}
if (unproven_equiv_cells.empty()) {
log("No selected unproven $equiv cells found in %s.\n", log_id(module));
log("No selected unproven $equiv cells found in %s.\n", module);
continue;
}

14
passes/equiv/equiv_make.cc
View file

@ -160,7 +160,7 @@ struct EquivMakeWorker
if (encdata.count(id))
{
log("Creating encoder/decoder for signal %s.\n", log_id(id));
log("Creating encoder/decoder for signal %s.\n", id.unescape());
Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width);
Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width);
@ -227,15 +227,15 @@ struct EquivMakeWorker
if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) {
if (gold_wire && gold_wire->port_id)
log_error("Can't match gold port `%s' to a gate port.\n", log_id(gold_wire));
log_error("Can't match gold port `%s' to a gate port.\n", gold_wire);
if (gate_wire && gate_wire->port_id)
log_error("Can't match gate port `%s' to a gold port.\n", log_id(gate_wire));
log_error("Can't match gate port `%s' to a gold port.\n", gate_wire);
continue;
}
log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
log_id(gold_wire), log_signal(assign_map(gold_wire)),
log_id(gate_wire), log_signal(assign_map(gate_wire)), log_id(id));
gold_wire, log_signal(assign_map(gold_wire)),
gate_wire, log_signal(assign_map(gate_wire)), id.unescape());
if (gold_wire->port_output || gate_wire->port_output)
{
@ -314,7 +314,7 @@ struct EquivMakeWorker
new_sig[i] = old_sig[i];
if (old_sig != new_sig) {
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
conn.first.unescape(), c, c->type.unescape(),
log_signal(old_sig), log_signal(new_sig));
c->setPort(conn.first, new_sig);
}
@ -345,7 +345,7 @@ struct EquivMakeWorker
goto try_next_cell_name;
log("Presumably equivalent cells: %s %s (%s) -> %s\n",
log_id(gold_cell), log_id(gate_cell), log_id(gold_cell->type), log_id(id));
gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape());
for (auto gold_conn : gold_cell->connections())
{

2
passes/equiv/equiv_mark.cc
View file

@ -109,7 +109,7 @@ struct EquivMarkWorker
void run()
{
log("Running equiv_mark on module %s:\n", log_id(module));
log("Running equiv_mark on module %s:\n", module);
// marking region 0

12
passes/equiv/equiv_miter.cc
View file

@ -82,7 +82,7 @@ struct EquivMiterWorker
for (auto c : source_module->selected_cells())
if (c->type == ID($equiv)) {
log("Seed $equiv cell: %s\n", log_id(c));
log("Seed $equiv cell: %s\n", c);
seed_cells.insert(c);
}
@ -194,11 +194,11 @@ struct EquivMiterWorker
w->port_input = true;
}
if (w->port_output && w->port_input)
log("Created miter inout port %s.\n", log_id(w));
log("Created miter inout port %s.\n", w);
else if (w->port_output)
log("Created miter output port %s.\n", log_id(w));
log("Created miter output port %s.\n", w);
else if (w->port_input)
log("Created miter input port %s.\n", log_id(w));
log("Created miter input port %s.\n", w);
}
miter_module->fixup_ports();
@ -252,7 +252,7 @@ struct EquivMiterWorker
void run()
{
log("Creating miter %s from module %s.\n", log_id(miter_module), log_id(source_module));
log("Creating miter %s from module %s.\n", miter_module, source_module);
find_miter_cells_wires();
copy_to_miter();
make_stuff();
@ -320,7 +320,7 @@ struct EquivMiterPass : public Pass {
extra_args(args, argidx, design);
if (design->module(worker.miter_name))
log_cmd_error("Miter module %s already exists.\n", log_id(worker.miter_name));
log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape());
worker.source_module = nullptr;
for (auto m : design->selected_modules()) {

6
passes/equiv/equiv_purge.cc
View file

@ -37,7 +37,7 @@ struct EquivPurgeWorker
Wire *wire = sig.as_wire();
if (wire->name.isPublic()) {
if (!wire->port_output) {
log(" Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
wire->port_output = true;
}
return wire;
@ -53,7 +53,7 @@ struct EquivPurgeWorker
Wire *wire = module->addWire(name, GetSize(sig));
wire->port_output = true;
module->connect(wire, sig);
log(" Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape());
return wire;
}
}
@ -87,7 +87,7 @@ struct EquivPurgeWorker
void run()
{
log("Running equiv_purge on module %s:\n", log_id(module));
log("Running equiv_purge on module %s:\n", module);
for (auto wire : module->wires()) {
wire->port_input = false;

2
passes/equiv/equiv_remove.cc
View file

@ -69,7 +69,7 @@ struct EquivRemovePass : public Pass {
{
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(ID::Y)));
module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell);
remove_count++;

10
passes/equiv/equiv_simple.cc
View file

@ -205,10 +205,10 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
(GetSize(cone_a.cells) + GetSize(cone_b.cells)) - GetSize(cells));
#if 0
for (auto cell : short_cells_cone_a)
log(" A-side cell: %s\n", log_id(cell));
log(" A-side cell: %s\n", cell);
for (auto cell : short_cells_cone_b)
log(" B-side cell: %s\n", log_id(cell));
log(" B-side cell: %s\n", cell);
#endif
}
void report_new_assume_cells(const pool<Cell*>& extra_problem_cells, int old_size, const pool<Cell*>& problem_cells) const
@ -219,7 +219,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
old_size - (GetSize(problem_cells) - GetSize(extra_problem_cells)));
#if 0
for (auto cell : extra_problem_cells)
log(" cell: %s\n", log_id(cell));
log(" cell: %s\n", cell);
#endif
}
}
@ -305,7 +305,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
pool<SigBit> seed_b = { bit_b };
if (cfg.verbose) {
log(" Trying to prove $equiv cell %s:\n", log_id(cell));
log(" Trying to prove $equiv cell %s:\n", cell);
log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(ID::Y)));
} else {
log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(ID::Y)));
@ -477,7 +477,7 @@ struct EquivSimplePass : public Pass {
continue;
log("Found %d unproven $equiv cells (%d groups) in %s:\n",
unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
unproven_cells_counter, GetSize(unproven_equiv_cells), module);
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))

6
passes/equiv/equiv_status.cc
View file

@ -67,17 +67,17 @@ struct EquivStatusPass : public Pass {
}
if (unproven_equiv_cells.empty() && !proven_equiv_cells) {
log("No $equiv cells found in %s.\n", log_id(module));
log("No $equiv cells found in %s.\n", module);
continue;
}
log("Found %d $equiv cells in %s:\n", GetSize(unproven_equiv_cells) + proven_equiv_cells, log_id(module));
log("Found %d $equiv cells in %s:\n", GetSize(unproven_equiv_cells) + proven_equiv_cells, module);
log(" Of those cells %d are proven and %d are unproven.\n", proven_equiv_cells, GetSize(unproven_equiv_cells));
if (unproven_equiv_cells.empty()) {
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
}
unproven_count += GetSize(unproven_equiv_cells);

14
passes/equiv/equiv_struct.cc
View file

@ -79,7 +79,7 @@ struct EquivStructWorker
inputs_a.append(bits_a[i]);
inputs_b.append(bits_b[i]);
input_names.push_back(GetSize(bits_a) == 1 ? port_a.first.str() :
stringf("%s[%d]", log_id(port_a.first), i));
stringf("%s[%d]", port_a.first.unescape(), i));
}
}
@ -111,7 +111,7 @@ struct EquivStructWorker
}
auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
merged_attr.insert(log_id(cell_b));
merged_attr.insert(cell_b->name.unescape());
cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
module->remove(cell_b);
}
@ -144,7 +144,7 @@ struct EquivStructWorker
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
log(" Purging redundant $equiv cell %s.\n", cell);
module->connect(sig_y, sig_a);
module->remove(cell);
merge_count++;
@ -266,9 +266,9 @@ struct EquivStructWorker
run_strategy:
int total_group_size = GetSize(gold_cells) + GetSize(gate_cells) + GetSize(other_cells);
log(" %s merging %d %s cells (from group of %d) using strategy %s:\n", phase ? "Bwd" : "Fwd",
2*GetSize(cell_pairs), log_id(cells_type), total_group_size, strategy);
2*GetSize(cell_pairs), cells_type.unescape(), total_group_size, strategy);
for (auto it : cell_pairs) {
log(" Merging cells %s and %s.\n", log_id(it.first), log_id(it.second));
log(" Merging cells %s and %s.\n", it.first, it.second);
merge_cell_pair(it.first, it.second);
}
}
@ -347,7 +347,7 @@ struct EquivStructPass : public Pass {
for (auto module : design->selected_modules()) {
int module_merge_count = 0;
log("Running equiv_struct on module %s:\n", log_id(module));
log("Running equiv_struct on module %s:\n", module);
for (int iter = 0;; iter++) {
if (iter == max_iter) {
log(" Reached iteration limit of %d.\n", iter);
@ -359,7 +359,7 @@ struct EquivStructPass : public Pass {
module_merge_count += worker.merge_count;
}
if (module_merge_count)
log(" Performed a total of %d merges in module %s.\n", module_merge_count, log_id(module));
log(" Performed a total of %d merges in module %s.\n", module_merge_count, module);
}
}
} EquivStructPass;

10
passes/fsm/fsm_detect.cc
View file

@ -132,7 +132,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
if (wire->width <= 1) {
if (has_fsm_encoding_attr) {
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", wire->module, wire);
wire->attributes.erase(ID::fsm_encoding);
}
return;
@ -230,23 +230,23 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
warnings.push_back("FSM seems to be self-resetting. Possible simulation-synthesis mismatch!\n");
if (!warnings.empty()) {
string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire));
string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", wire->module, wire);
for (auto w : warnings) warnmsg += " " + w;
log_warning("%s", warnmsg);
} else {
log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
log("FSM state register %s.%s already has fsm_encoding attribute.\n", wire->module, wire);
}
}
else
if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
{
log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
log("Found FSM state register %s.%s.\n", wire->module, wire);
wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
}
else
if (looks_like_state_reg)
{
log("Not marking %s.%s as FSM state register:\n", log_id(wire->module), log_id(wire));
log("Not marking %s.%s as FSM state register:\n", wire->module, wire);
if (is_module_port)
log(" Register is connected to module port.\n");

6
passes/fsm/fsm_expand.cc
View file

@ -189,12 +189,12 @@ struct FsmExpand
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
log_id(cell->module), log_id(cell), log_id(cell->type),
GetSize(input_sig), log_id(fsm_cell->module), log_id(fsm_cell));
cell->module, cell, cell->type.unescape(),
GetSize(input_sig), fsm_cell->module, fsm_cell);
if (GetSize(fsm_data.transition_table) > 10000)
log_warning("Transition table for FSM %s.%s already has %d rows, merging more cells "
"into this FSM might be problematic.\n", log_id(fsm_cell->module), log_id(fsm_cell),
"into this FSM might be problematic.\n", fsm_cell->module, fsm_cell,
GetSize(fsm_data.transition_table));
std::vector<FsmData::transition_t> new_transition_table;

2
passes/fsm/fsm_export.cc
View file

@ -64,7 +64,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_name.assign(attr_it->second.decode_string());
}
else {
kiss_name.assign(log_id(module) + std::string("-") + log_id(cell) + ".kiss2");
kiss_name.assign(module->name.unescape() + std::string("-") + cell->name.unescape() + ".kiss2");
}
log("\n");

2
passes/fsm/fsm_info.cc
View file

@ -50,7 +50,7 @@ struct FsmInfoPass : public Pass {
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm)) {
log("\n");
log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
log("FSM `%s' from module `%s':\n", cell, mod);
FsmData fsm_data;
fsm_data.copy_from_cell(cell);
fsm_data.log_info(cell);

2
passes/fsm/fsm_recode.cc
View file

@ -96,7 +96,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
log_error("FSM encoding `%s' is not supported!\n", encoding);
if (encfile)
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
fprintf(encfile, ".fsm %s %s\n", module->name.unescape().c_str(), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
for (int i = 0; i < int(fsm_data.state_table.size()); i++)

10
passes/hierarchy/flatten.cc
View file

@ -149,7 +149,7 @@ struct FlattenWorker
hier_wire->attributes.erase(ID::hierconn);
if (GetSize(hier_wire) < GetSize(tpl_wire)) {
log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n",
log_id(module), log_id(hier_wire), log_id(tpl), log_id(tpl_wire), log_id(module), log_id(cell));
module, hier_wire, tpl, tpl_wire, module, cell);
hier_wire->width = GetSize(tpl_wire);
}
new_wire = hier_wire;
@ -261,7 +261,7 @@ struct FlattenWorker
if (sigmap(new_conn.first).has_const())
log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n",
log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second));
module, cell, port_it.first.unescape(), log_signal(new_conn.first), log_signal(new_conn.second));
module->connect(new_conn);
sigmap.add(new_conn.first, new_conn.second);
@ -316,12 +316,12 @@ struct FlattenWorker
continue;
if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) {
log("Keeping %s.%s (found keep_hierarchy attribute).\n", log_id(module), log_id(cell));
log("Keeping %s.%s (found keep_hierarchy attribute).\n", module, cell);
used_modules.insert(tpl);
continue;
}
log_debug("Flattening %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log_debug("Flattening %s.%s (%s).\n", module, cell, cell->type.unescape());
// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
@ -443,7 +443,7 @@ struct FlattenPass : public Pass {
if (cleanup && top != nullptr)
for (auto module : design->modules().to_vector())
if (!used_modules[module] && !module->get_blackbox_attribute(worker.ignore_wb)) {
log("Deleting now unused module %s.\n", log_id(module));
log("Deleting now unused module %s.\n", module);
design->remove(module);
}

40
passes/hierarchy/hierarchy.cc
View file

@ -225,7 +225,7 @@ struct IFExpander
// about it and don't set has_interfaces_not_found (to avoid a
// loop).
log_warning("Could not find interface instance for `%s' in `%s'\n",
log_id(interface_name), log_id(&module));
interface_name.unescape(), &module);
}
// Handle an interface connection from the module
@ -268,12 +268,12 @@ struct IFExpander
// Go over all wires in interface, and add replacements to lists.
for (auto mod_wire : mod_replace_ports->wires()) {
std::string signal_name1 = conn_name.str() + "." + log_id(mod_wire->name);
std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire);
std::string signal_name1 = conn_name.str() + "." + mod_wire->name.unescape();
std::string signal_name2 = interface_name.str() + "." + mod_wire->name.unescape();
connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
if(module.wire(signal_name2) == nullptr) {
log_error("Could not find signal '%s' in '%s'\n",
signal_name2.c_str(), log_id(module.name));
signal_name2.c_str(), module.name.unescape());
}
else {
RTLIL::Wire *wire_in_parent = module.wire(signal_name2);
@ -432,7 +432,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
if (id <= 0 || id > GetSize(mod.ports))
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"has only %d ports, requested port %d.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
cell.type.unescape(), &module, &cell,
GetSize(mod.ports), id);
continue;
}
@ -441,8 +441,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
if (!wire || wire->port_id == 0) {
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"does not have a port named '%s'.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
log_id(conn.first));
cell.type.unescape(), &module, &cell,
conn.first.unescape());
}
}
for (auto &param : cell.parameters) {
@ -450,7 +450,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
if (id <= 0 || id > GetSize(mod.avail_parameters))
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"has only %d parameters, requested parameter %d.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
cell.type.unescape(), &module, &cell,
GetSize(mod.avail_parameters), id);
continue;
}
@ -460,8 +460,8 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
strchr(param.first.c_str(), '.') == NULL) {
log_error("Module `%s' referenced in module `%s' in cell `%s' "
"does not have a parameter named '%s'.\n",
log_id(cell.type), log_id(&module), log_id(&cell),
log_id(param.first));
cell.type.unescape(), &module, &cell,
param.first.unescape());
}
}
}
@ -1036,7 +1036,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr)
for (auto mod : design->modules())
if (mod->get_bool_attribute(ID::top)) {
log("Attribute `top' found on module `%s'. Setting top module to %s.\n", log_id(mod), log_id(mod));
log("Attribute `top' found on module `%s'. Setting top module to %s.\n", mod, mod);
top_mod = mod;
}
@ -1057,12 +1057,12 @@ struct HierarchyPass : public Pass {
dict<Module*, int> db;
for (Module *mod : design->selected_modules()) {
int score = find_top_mod_score(design, mod, db);
log("root of %3d design levels: %-20s\n", score, log_id(mod));
log("root of %3d design levels: %-20s\n", score, mod);
if (!top_mod || score > db[top_mod])
top_mod = mod;
}
if (top_mod != nullptr)
log("Automatically selected %s as design top module.\n", log_id(top_mod));
log("Automatically selected %s as design top module.\n", top_mod);
}
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
@ -1162,7 +1162,7 @@ struct HierarchyPass : public Pass {
std::map<RTLIL::Module*, bool> cache;
for (auto mod : design->modules())
if (set_keep_print(cache, mod)) {
log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod));
log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", mod);
mod->set_bool_attribute(ID::keep);
}
}
@ -1171,7 +1171,7 @@ struct HierarchyPass : public Pass {
std::map<RTLIL::Module*, bool> cache;
for (auto mod : design->modules())
if (set_keep_assert(cache, mod)) {
log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod));
log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", mod);
mod->set_bool_attribute(ID::keep);
}
}
@ -1190,7 +1190,7 @@ struct HierarchyPass : public Pass {
src += ": ";
log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `chformal -remove a:unsupported_sva' to ignore.\n",
src, log_id(cell->name), log_id(mod->name));
src, cell->name.unescape(), mod->name.unescape());
}
}
}
@ -1499,7 +1499,7 @@ struct HierarchyPass : public Pass {
bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
if (resize_widths && verific_mod && boxed_params)
log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
log_id(module), log_id(cell), log_id(conn.first)
module, cell, conn.first.unescape()
);
else if (resize_widths) {
if (GetSize(w) < GetSize(conn.second))
@ -1523,14 +1523,14 @@ struct HierarchyPass : public Pass {
}
if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
log_id(conn.first), GetSize(conn.second), GetSize(sig));
log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", module, cell,
conn.first.unescape(), GetSize(conn.second), GetSize(sig));
cell->setPort(conn.first, sig);
}
if (w->port_output && !w->port_input && sig.has_const())
log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
module, cell, conn.first.unescape(), cell->type.unescape(), log_signal(sig));
}
}
}

8
passes/hierarchy/keep_hierarchy.cc
View file

@ -42,7 +42,7 @@ struct ThresholdHierarchyKeeping {
return 0;
if (module->get_blackbox_attribute())
log_error("Missing cost information on instanced blackbox %s\n", log_id(module));
log_error("Missing cost information on instanced blackbox %s\n", module);
if (done.count(module))
return done.at(module);
@ -61,13 +61,13 @@ struct ThresholdHierarchyKeeping {
RTLIL::Module *submodule = design->module(cell->type);
if (!submodule)
log_error("Hierarchy contains unknown module '%s' (instanced as %s in %s)\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
size += visit(submodule);
}
}
if (size > threshold) {
log("Keeping %s (estimated size above threshold: %" PRIu64 " > %" PRIu64 ").\n", log_id(module), size, threshold);
log("Keeping %s (estimated size above threshold: %" PRIu64 " > %" PRIu64 ").\n", module, size, threshold);
module->set_bool_attribute(ID::keep_hierarchy);
size = 0;
}
@ -124,7 +124,7 @@ struct KeepHierarchyPass : public Pass {
worker.visit(top);
} else {
for (auto module : design->selected_modules()) {
log("Marking %s.\n", log_id(module));
log("Marking %s.\n", module);
module->set_bool_attribute(ID::keep_hierarchy);
}
}

6
passes/hierarchy/uniquify.cc
View file

@ -71,7 +71,7 @@ struct UniquifyPass : public Pass {
for (auto cell : module->selected_cells())
{
Module *tmod = design->module(cell->type);
IdString newname = module->name.str() + "." + log_id(cell->name);
IdString newname = module->name.str() + "." + cell->name.unescape();
if (tmod == nullptr)
continue;
@ -82,14 +82,14 @@ struct UniquifyPass : public Pass {
if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name)
continue;
log("Creating module %s from %s.\n", log_id(newname), log_id(tmod));
log("Creating module %s from %s.\n", newname.unescape(), tmod);
auto smod = tmod->clone();
smod->name = newname;
cell->type = newname;
smod->set_bool_attribute(ID::unique);
if (smod->attributes.count(ID::hdlname) == 0)
smod->attributes[ID::hdlname] = string(log_id(tmod->name));
smod->attributes[ID::hdlname] = string(tmod->name.unescape());
design->add(smod);
did_something = true;

66
passes/memory/memory_bram.cc
View file

@ -44,7 +44,7 @@ struct rules_t
void dump_config() const
{
log(" bram %s # variant %d\n", log_id(name), variant);
log(" bram %s # variant %d\n", name.unescape(), variant);
log(" init %d\n", init);
log(" abits %d\n", abits);
log(" dbits %d\n", dbits);
@ -61,16 +61,16 @@ struct rules_t
void check_vectors() const
{
if (groups != GetSize(ports)) log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n", log_id(name), variant, groups, GetSize(ports));
if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", log_id(name), variant, groups, GetSize(wrmode));
if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", log_id(name), variant, groups, GetSize(enable));
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", log_id(name), variant, groups, GetSize(transp));
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", log_id(name), variant, groups, GetSize(clocks));
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", log_id(name), variant, groups, GetSize(clkpol));
if (groups != GetSize(ports)) log_error("Bram %s variant %d has %d groups but only %d entries in 'ports'.\n", name.unescape(), variant, groups, GetSize(ports));
if (groups != GetSize(wrmode)) log_error("Bram %s variant %d has %d groups but only %d entries in 'wrmode'.\n", name.unescape(), variant, groups, GetSize(wrmode));
if (groups != GetSize(enable)) log_error("Bram %s variant %d has %d groups but only %d entries in 'enable'.\n", name.unescape(), variant, groups, GetSize(enable));
if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", name.unescape(), variant, groups, GetSize(transp));
if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", name.unescape(), variant, groups, GetSize(clocks));
if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", name.unescape(), variant, groups, GetSize(clkpol));
int group = 0;
for (auto e : enable)
if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", log_id(name), variant, group, e, dbits);
if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", name.unescape(), variant, group, e, dbits);
}
vector<portinfo_t> make_portinfos() const
@ -100,7 +100,7 @@ struct rules_t
log_assert(name == other.name);
if (groups != other.groups)
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant);
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", name.unescape(), variant, other.variant);
if (abits != other.abits)
variant_params[ID::CFG_ABITS] = abits;
@ -112,7 +112,7 @@ struct rules_t
for (int i = 0; i < groups; i++)
{
if (ports[i] != other.ports[i])
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", log_id(name), variant, other.variant, 'A'+i);
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", name.unescape(), variant, other.variant, 'A'+i);
if (wrmode[i] != other.wrmode[i])
variant_params[stringf("\\CFG_WRMODE_%c", 'A' + i)] = wrmode[i];
if (enable[i] != other.enable[i])
@ -428,7 +428,7 @@ bool replace_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals, const
transp_max = max(transp_max, pi.transp);
}
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
log(" Mapping to bram type %s (variant %d):\n", bram.name.unescape(), bram.variant);
// bram.dump_config();
std::vector<int> shuffle_map;
@ -715,21 +715,21 @@ grow_read_ports:;
for (auto it : match.min_limits) {
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] >= it.second)
continue;
log(" Rule for bram type %s rejected: requirement 'min %s %d' not met.\n",
log_id(match.name), it.first.c_str(), it.second);
match.name.unescape(), it.first.c_str(), it.second);
return false;
}
for (auto it : match.max_limits) {
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] <= it.second)
continue;
log(" Rule for bram type %s rejected: requirement 'max %s %d' not met.\n",
log_id(match.name), it.first.c_str(), it.second);
match.name.unescape(), it.first.c_str(), it.second);
return false;
}
@ -759,13 +759,13 @@ grow_read_ports:;
if (!exists)
ss << "!";
IdString key = std::get<1>(sums.front());
ss << log_id(key);
ss << key.unescape();
const Const &value = rules.map_case(std::get<2>(sums.front()));
if (exists && value != Const(1))
ss << "=\"" << value.decode_string() << "\"";
log(" Rule for bram type %s rejected: requirement 'attribute %s ...' not met.\n",
log_id(match.name), ss.str().c_str());
match.name.unescape(), ss.str().c_str());
return false;
}
}
@ -874,7 +874,7 @@ grow_read_ports:;
for (int dupidx = 0; dupidx < dup_count; dupidx++)
{
Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid, grid_d, grid_a, dupidx)), bram.name);
log(" Creating %s cell at grid position <%d %d %d>: %s\n", log_id(bram.name), grid_d, grid_a, dupidx, log_id(c));
log(" Creating %s cell at grid position <%d %d %d>: %s\n", bram.name.unescape(), grid_d, grid_a, dupidx, c);
for (auto &vp : variant_params)
c->setParam(vp.first, vp.second);
@ -1004,7 +1004,7 @@ grow_read_ports:;
void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
{
log("Processing %s.%s:\n", log_id(mem.module), log_id(mem.memid));
log("Processing %s.%s:\n", mem.module, mem.memid.unescape());
mem.narrow();
bool cell_init = !mem.inits.empty();
@ -1031,7 +1031,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
auto &match = rules.matches.at(i);
if (!rules.brams.count(rules.matches[i].name))
log_error("No bram description for resource %s found!\n", log_id(rules.matches[i].name));
log_error("No bram description for resource %s found!\n", rules.matches[i].name.unescape());
for (int vi = 0; vi < GetSize(rules.brams.at(match.name)); vi++)
{
@ -1047,7 +1047,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
avail_wr_ports += GetSize(bram.ports) < j ? bram.ports.at(j) : 0;
}
log(" Checking rule #%d for bram type %s (variant %d):\n", i+1, log_id(bram.name), bram.variant);
log(" Checking rule #%d for bram type %s (variant %d):\n", i+1, bram.name.unescape(), bram.variant);
log(" Bram geometry: abits=%d dbits=%d wports=%d rports=%d\n", bram.abits, bram.dbits, avail_wr_ports, avail_rd_ports);
int dups = avail_rd_ports ? (match_properties["rports"] + avail_rd_ports - 1) / avail_rd_ports : 1;
@ -1077,11 +1077,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
goto next_match_rule;
log(" Metrics for %s: awaste=%d dwaste=%d bwaste=%d waste=%d efficiency=%d\n",
log_id(match.name), awaste, dwaste, bwaste, waste, efficiency);
match.name.unescape(), awaste, dwaste, bwaste, waste, efficiency);
if (cell_init && bram.init == 0) {
log(" Rule #%d for bram type %s (variant %d) rejected: cannot be initialized.\n",
i+1, log_id(bram.name), bram.variant);
i+1, bram.name.unescape(), bram.variant);
goto next_match_rule;
}
@ -1090,11 +1090,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
continue;
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] >= it.second)
continue;
log(" Rule #%d for bram type %s (variant %d) rejected: requirement 'min %s %d' not met.\n",
i+1, log_id(bram.name), bram.variant, it.first.c_str(), it.second);
i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
goto next_match_rule;
}
@ -1103,11 +1103,11 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
continue;
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
it.first.c_str(), log_id(match.name));
it.first.c_str(), match.name.unescape());
if (match_properties[it.first] <= it.second)
continue;
log(" Rule #%d for bram type %s (variant %d) rejected: requirement 'max %s %d' not met.\n",
i+1, log_id(bram.name), bram.variant, it.first.c_str(), it.second);
i+1, bram.name.unescape(), bram.variant, it.first.c_str(), it.second);
goto next_match_rule;
}
@ -1137,18 +1137,18 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
if (!exists)
ss << "!";
IdString key = std::get<1>(sums.front());
ss << log_id(key);
ss << key.unescape();
const Const &value = rules.map_case(std::get<2>(sums.front()));
if (exists && value != Const(1))
ss << "=\"" << value.decode_string() << "\"";
log(" Rule for bram type %s (variant %d) rejected: requirement 'attribute %s ...' not met.\n",
log_id(bram.name), bram.variant, ss.str().c_str());
bram.name.unescape(), bram.variant, ss.str().c_str());
goto next_match_rule;
}
}
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant);
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, bram.name.unescape(), bram.variant);
if (or_next_if_better || !best_rule_cache.empty())
{
@ -1156,7 +1156,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
log_error("Found 'or_next_if_better' in last match rule.\n");
if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 1)) {
log(" Mapping to bram type %s failed.\n", log_id(match.name));
log(" Mapping to bram type %s failed.\n", match.name.unescape());
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
goto next_match_rule;
}
@ -1183,12 +1183,12 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
auto &best_bram = rules.brams.at(rules.matches.at(best_rule.first).name).at(best_rule.second);
if (!replace_memory(mem, rules, initvals, best_bram, rules.matches.at(best_rule.first), match_properties, 2))
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", log_id(best_bram.name), best_bram.variant);
log_error("Mapping to bram type %s (variant %d) after pre-selection failed.\n", best_bram.name.unescape(), best_bram.variant);
return;
}
if (!replace_memory(mem, rules, initvals, bram, match, match_properties, 0)) {
log(" Mapping to bram type %s failed.\n", log_id(match.name));
log(" Mapping to bram type %s failed.\n", match.name.unescape());
failed_brams.insert(pair<IdString, int>(bram.name, bram.variant));
goto next_match_rule;
}

34
passes/memory/memory_libmap.cc
View file

@ -204,7 +204,7 @@ struct MemMapping {
if (!check_init(rdef))
continue;
if (rdef.prune_rom && mem.wr_ports.empty()) {
log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module->name), log_id(mem.memid), log_id(rdef.id));
log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", mem.module->name.unescape(), mem.memid.unescape(), rdef.id.unescape());
continue;
}
MemConfig cfg;
@ -323,7 +323,7 @@ struct MemMapping {
void log_reject(const Ram &ram, std::string message) {
if(ys_debug(1)) {
rejected_cfg_debug_msgs += stringf("can't map to to %s: ", log_id(ram.id));
rejected_cfg_debug_msgs += stringf("can't map to to %s: ", ram.id.unescape());
rejected_cfg_debug_msgs += message;
rejected_cfg_debug_msgs += "\n";
}
@ -338,7 +338,7 @@ struct MemMapping {
rejected_cfg_debug_msgs += portname;
first = false;
}
rejected_cfg_debug_msgs += stringf("] of %s: ", log_id(ram.id));
rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
rejected_cfg_debug_msgs += message;
rejected_cfg_debug_msgs += "\n";
}
@ -361,7 +361,7 @@ struct MemMapping {
rejected_cfg_debug_msgs += portname;
first = false;
}
rejected_cfg_debug_msgs += stringf("] of %s: ", log_id(ram.id));
rejected_cfg_debug_msgs += stringf("] of %s: ", ram.id.unescape());
rejected_cfg_debug_msgs += message;
rejected_cfg_debug_msgs += "\n";
}
@ -380,7 +380,7 @@ void MemMapping::dump_configs(int stage) {
default:
abort();
}
log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module->name), log_id(mem.memid), stage_name);
log_debug("Memory %s.%s mapping candidates (%s):\n", mem.module->name.unescape(), mem.memid.unescape(), stage_name);
if (logic_ok) {
log_debug("- logic fallback\n");
log_debug(" - cost: %f\n", logic_cost);
@ -391,7 +391,7 @@ void MemMapping::dump_configs(int stage) {
}
void MemMapping::dump_config(MemConfig &cfg) {
log_debug("- %s:\n", log_id(cfg.def->id));
log_debug("- %s:\n", cfg.def->id.unescape());
for (auto &it: cfg.def->options)
log_debug(" - option %s %s\n", it.first, log_const(it.second));
log_debug(" - emulation score: %d\n", cfg.score_emu);
@ -527,7 +527,7 @@ void MemMapping::determine_style() {
auto find_attr = search_for_attribute(mem, ID::lram);
if (find_attr.first && find_attr.second.as_bool()) {
kind = RamKind::Huge;
log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module->name), log_id(mem.memid));
log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", mem.module->name.unescape(), mem.memid.unescape());
return;
}
for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) {
@ -536,7 +536,7 @@ void MemMapping::determine_style() {
Const val = find_attr.second;
if (val == 1) {
kind = RamKind::NotLogic;
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", attr.unescape(), mem.module->name.unescape(), mem.memid.unescape());
return;
}
std::string val_s = val.decode_string();
@ -549,20 +549,20 @@ void MemMapping::determine_style() {
// Nothing.
} else if (val_s == "logic" || val_s == "registers") {
kind = RamKind::Logic;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else if (val_s == "distributed") {
kind = RamKind::Distributed;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
kind = RamKind::Block;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else if (val_s == "huge" || val_s == "ultra") {
kind = RamKind::Huge;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape());
} else {
kind = RamKind::NotLogic;
style = val_s;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid), val_s);
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape(), val_s);
}
return;
}
@ -1991,7 +1991,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
}
void MemMapping::emit(const MemConfig &cfg) {
log("mapping memory %s.%s via %s\n", log_id(mem.module->name), log_id(mem.memid), log_id(cfg.def->id));
log("mapping memory %s.%s via %s\n", mem.module->name.unescape(), mem.memid.unescape(), cfg.def->id.unescape());
// First, handle emulations.
if (cfg.emu_read_first)
mem.emulate_read_first(&worker.initvals);
@ -2252,9 +2252,9 @@ struct MemoryLibMapPass : public Pass {
int best = map.logic_cost;
if (!map.logic_ok) {
if (map.cfgs.empty()) {
log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module->name), log_id(mem.memid));
log_debug("Rejected candidates for mapping memory %s.%s:\n", module->name.unescape(), mem.memid.unescape());
log_debug("%s", map.rejected_cfg_debug_msgs);
log_error("no valid mapping found for memory %s.%s\n", log_id(module->name), log_id(mem.memid));
log_error("no valid mapping found for memory %s.%s\n", module->name.unescape(), mem.memid.unescape());
}
idx = 0;
best = map.cfgs[0].cost;
@ -2266,7 +2266,7 @@ struct MemoryLibMapPass : public Pass {
}
}
if (idx == -1) {
log("using FF mapping for memory %s.%s\n", log_id(module->name), log_id(mem.memid));
log("using FF mapping for memory %s.%s\n", module->name.unescape(), mem.memid.unescape());
} else {
map.emit(map.cfgs[idx]);
// Rebuild indices after modifying module

2
passes/memory/memory_memx.cc
View file

@ -60,7 +60,7 @@ struct MemoryMemxPass : public Pass {
{
if (port.clk_enable)
log_error("Memory %s.%s has a synchronous read port. Synchronous read ports are not supported by memory_memx!\n",
log_id(module), log_id(mem.memid));
module, mem.memid.unescape());
SigSpec addr_ok = make_addr_check(mem, port.addr);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));

6
passes/memory/memory_share.cc
View file

@ -80,7 +80,7 @@ struct MemoryShareWorker
if (GetSize(mem.rd_ports) <= 1)
return false;
log("Consolidating read ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
log("Consolidating read ports of memory %s.%s by address:\n", module, mem.memid.unescape());
bool changed = false;
int abits = 0;
@ -197,7 +197,7 @@ struct MemoryShareWorker
if (GetSize(mem.wr_ports) <= 1)
return false;
log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
log("Consolidating write ports of memory %s.%s by address:\n", module, mem.memid.unescape());
bool changed = false;
int abits = 0;
@ -316,7 +316,7 @@ struct MemoryShareWorker
if (eligible_ports.size() <= 1)
return;
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", module, mem.memid.unescape());
// Group eligible ports by clock domain and width.

4
passes/opt/muxpack.cc
View file

@ -193,7 +193,7 @@ struct MuxpackWorker
{
for (auto cell : candidate_cells)
{
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
SigSpec a_sig = sigmap(cell->getPort(ID::A));
if (cell->type == ID($mux)) {
@ -272,7 +272,7 @@ struct MuxpackWorker
Cell *last_cell = chain[cursor+cases-1];
log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
module, first_cell, module, last_cell, cases);
mux_count += cases;
pmux_count += 1;

4
passes/opt/opt_balance_tree.cc
View file

@ -279,7 +279,7 @@ struct OptBalanceTreeWorker {
if (inner_cells)
{
// Create a tree
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", log_id(head_cell), GetSize(sources), inner_cells);
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells);
// Build a vector of all source signals
vector<SigSpec> source_signals;
@ -369,7 +369,7 @@ struct OptBalanceTreePass : public Pass {
// Log stats
for (auto cell_type : cell_types)
log("Converted %d %s cells into trees.\n", cell_count[cell_type], log_id(cell_type));
log("Converted %d %s cells into trees.\n", cell_count[cell_type], cell_type.unescape());
// Clean up
Yosys::run_pass("clean -purge");

2
passes/opt/opt_clean/inits.cc
View file

@ -109,7 +109,7 @@ bool remove_redundant_inits(ShardedVector<RTLIL::Wire*> wires, bool verbose) {
bool did_something = false;
for (RTLIL::Wire *wire : wires) {
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
log_debug(" removing redundant init attribute on %s.\n", wire);
wire->attributes.erase(ID::init);
did_something = true;
}

2
passes/opt/opt_demorgan.cc
View file

@ -43,7 +43,7 @@ void demorgan_worker(
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->name.unescape(), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)
{

44
passes/opt/opt_dff.cc
View file

@ -301,7 +301,7 @@ struct OptDffWorker
initvals.remove_init(ff.sig_q[i]);
module->connect(ff.sig_q[i], State::S0);
log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
i, cell, cell->type.unescape(), module);
sr_removed = true;
} else if (is_always_active(ff.sig_set[i], ff.pol_set)) {
initvals.remove_init(ff.sig_q[i]);
@ -312,7 +312,7 @@ struct OptDffWorker
else
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, log_id(cell), log_id(cell->type), log_id(module));
i, cell, cell->type.unescape(), module);
sr_removed = true;
} else {
keep_bits.push_back(i);
@ -335,7 +335,7 @@ struct OptDffWorker
if (clr_inactive && signal_all_same(ff.sig_set)) {
log("Removing never-active CLR on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_set;
@ -344,7 +344,7 @@ struct OptDffWorker
changed = true;
} else if (set_inactive && signal_all_same(ff.sig_clr)) {
log("Removing never-active SET on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.pol_arst = ff.pol_clr;
@ -370,7 +370,7 @@ struct OptDffWorker
if (!failed) {
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_sr = false;
ff.has_arst = true;
ff.val_arst = val_arst_builder.build();
@ -389,7 +389,7 @@ struct OptDffWorker
// Converts constant Async Load to ARST
if (is_always_inactive(ff.sig_aload, ff.pol_aload)) {
log("Removing never-active async load on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_aload = false;
changed = true;
return false;
@ -398,7 +398,7 @@ struct OptDffWorker
if (is_active(ff.sig_aload, ff.pol_aload)) {
// ALOAD always active
log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.remove();
if (ff.has_sr) {
@ -433,7 +433,7 @@ struct OptDffWorker
// AD is constant -> ARST
if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {
log("Changing const-value async load to async reset on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_arst = true;
ff.has_aload = false;
ff.sig_arst = ff.sig_aload;
@ -450,12 +450,12 @@ struct OptDffWorker
// Removes ARST if never active or replaces FF if always active
if (is_inactive(ff.sig_arst, ff.pol_arst)) {
log("Removing never-active ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_arst = false;
changed = true;
} else if (is_always_active(ff.sig_arst, ff.pol_arst)) {
log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.remove();
module->connect(ff.sig_q, ff.val_arst);
return true;
@ -469,12 +469,12 @@ struct OptDffWorker
// Removes SRST if never active or forces D to reset value if always active
if (is_inactive(ff.sig_srst, ff.pol_srst)) {
log("Removing never-active SRST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_srst = false;
changed = true;
} else if (is_always_active(ff.sig_srst, ff.pol_srst)) {
log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_srst = false;
if (!ff.ce_over_srst)
ff.has_ce = false;
@ -489,7 +489,7 @@ struct OptDffWorker
if (is_always_inactive(ff.sig_ce, ff.pol_ce)) {
if (ff.has_srst && !ff.ce_over_srst) {
log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.pol_ce = ff.pol_srst;
ff.sig_ce = ff.sig_srst;
ff.has_srst = false;
@ -497,7 +497,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else {
@ -507,7 +507,7 @@ struct OptDffWorker
}
} else if (is_active(ff.sig_ce, ff.pol_ce)) {
log("Removing always-active EN on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = false;
changed = true;
}
@ -517,7 +517,7 @@ struct OptDffWorker
{
if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling const CLK on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_ce = ff.has_clk = ff.has_srst = false;
changed = true;
} else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) {
@ -532,7 +532,7 @@ struct OptDffWorker
// Detect feedback loops where D is hardwired to Q
if (ff.has_clk && ff.has_srst) {
log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
if (ff.has_ce && ff.ce_over_srst) {
SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine);
SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine);
@ -549,7 +549,7 @@ struct OptDffWorker
changed = true;
} else if (!opt.keepdc || ff.val_init.is_fully_def()) {
log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_gclk = ff.has_clk = ff.has_ce = false;
changed = true;
}
@ -627,7 +627,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",
log_id(cell), log_id(cell->type), log_id(module),
cell, cell->type.unescape(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));
}
@ -701,7 +701,7 @@ struct OptDffWorker
dff_cells.push_back(new_cell);
log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",
log_id(cell), log_id(cell->type), log_id(module),
cell, cell->type.unescape(), module,
log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));
}
@ -768,7 +768,7 @@ struct OptDffWorker
if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {
log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
ff.has_aload = false;
changed = true;
}
@ -885,7 +885,7 @@ struct OptDffWorker
}
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n",
val ? 1 : 0, i, log_id(cell), log_id(cell->type), log_id(module));
val ? 1 : 0, i, cell, cell->type.unescape(), module);
// Replace the Q output with the constant value
initvals.remove_init(ff.sig_q[i]);

54
passes/opt/opt_expr.cc
View file

@ -88,7 +88,7 @@ void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
}
}
log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val));
log_debug("Setting undriven signal in %s to constant: %s = %s\n", module, log_signal(sig), log_signal(val));
module->connect(sig, val);
did_something = true;
}
@ -105,11 +105,11 @@ void replace_undriven(RTLIL::Module *module, const NewCellTypes &ct)
initval.set(i, State::Sx);
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
log_debug("Removing init attribute from %s/%s.\n", module, wire);
wire->attributes.erase(ID::init);
did_something = true;
} else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
log_debug("Updating init attribute on %s/%s: %s\n", module, wire, log_signal(initval));
wire->attributes[ID::init] = initval;
did_something = true;
}
@ -196,7 +196,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
return false;
log_debug("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
log_id(cell->type), log_id(cell), log_id(module));
cell->type.unescape(), cell, module);
for (int i = 0; i < GRP_N; i++)
{
@ -224,7 +224,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_a.replace(dict<SigBit,SigBit>{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b);
else log_abort();
}
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), cell->type.unescape(), log_signal(new_a));
module->connect(new_y, new_b);
module->connect(new_conn);
continue;
@ -261,7 +261,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
}
}
if (!undef_y.empty()) {
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_signal(undef_a));
log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), cell->type.unescape(), log_signal(undef_a));
module->connect(undef_y, undef_b);
if (def_y.empty()) {
module->connect(new_conn);
@ -292,7 +292,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
module->connect(new_conn);
log_debug(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
log_debug(" New cell `%s': A=%s", c, log_signal(new_a));
if (b_name == ID::B)
log_debug(", B=%s", log_signal(new_b));
log_debug("\n");
@ -308,7 +308,7 @@ void handle_polarity_inv(Cell *cell, IdString port, IdString param, const SigMap
SigSpec sig = assign_map(cell->getPort(port));
if (invert_map.count(sig)) {
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
port.unescape(), cell->type.unescape(), cell, cell->module,
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->setParam(param, !cell->getParam(param).as_bool());
@ -337,7 +337,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, IdStrin
SigSpec sig = assign_map(cell->getPort(port));
if (invert_map.count(sig)) {
log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
port.unescape(), cell->type.unescape(), cell, cell->module,
log_signal(sig), log_signal(invert_map.at(sig)));
cell->setPort(port, (invert_map.at(sig)));
cell->type = cell->type == type1 ? type2 : type1;
@ -511,7 +511,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!cells.sort()) {
// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", module);
}
for (auto cell : cells.sorted)
@ -631,7 +631,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
{
if (cell->type == ID($reduce_xnor)) {
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type.unescape(), cell->name.unescape(), module);
cell->type = ID($not);
did_something = true;
} else {
@ -651,7 +651,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (a_fully_const != b_fully_const)
{
log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type.unescape(), cell->name.unescape(), module);
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(ID::Y));
@ -932,7 +932,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
@ -988,7 +988,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, cell->type.unescape(), cell, module);
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
@ -1062,7 +1062,7 @@ skip_fine_alu:
}
if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", cell->type.unescape(), cell, module);
RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
@ -1241,7 +1241,7 @@ skip_fine_alu:
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
} else {
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
cell->type = ID($not);
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
@ -1255,8 +1255,8 @@ skip_fine_alu:
if (cell->type.in(ID($eq), ID($ne)) &&
(assign_map(cell->getPort(ID::A)).is_fully_zero() || assign_map(cell->getPort(ID::B)).is_fully_zero()))
{
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", cell->type.unescape(), cell,
module, cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B));
@ -1303,7 +1303,7 @@ skip_fine_alu:
}
log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort(ID::B))), shift_bits, log_id(module), log_signal(sig_y));
cell->type.unescape(), cell, log_signal(assign_map(cell->getPort(ID::B))), shift_bits, module, log_signal(sig_y));
module->connect(cell->getPort(ID::Y), sig_y);
module->remove(cell);
@ -1428,7 +1428,7 @@ skip_identity:
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
@ -1446,7 +1446,7 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
@ -1465,7 +1465,7 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", cell->type.unescape(), cell, module);
cell->setPort(ID::B, cell->getPort(ID::S));
cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
@ -1515,7 +1515,7 @@ skip_identity:
}
if (cell->getPort(ID::S).size() != new_s.size()) {
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
GetSize(cell->getPort(ID::S)) - GetSize(new_s), cell->type.unescape(), cell, module);
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
cell->setPort(ID::S, new_s);
@ -2021,7 +2021,7 @@ skip_alu_split:
Const y_value(cell->type.in(ID($eq), ID($eqx)) ? 0 : 1, GetSize(y_sig));
log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
log_id(cell), log_id(module), log_signal(y_value));
cell, module, log_signal(y_value));
module->connect(y_sig, y_value);
module->remove(cell);
@ -2033,7 +2033,7 @@ skip_alu_split:
if (redundant_bits)
{
log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
redundant_bits, cell->type.unescape(), cell, module);
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
@ -2172,7 +2172,7 @@ skip_alu_split:
if (replace || remove)
{
log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
cell->type.unescape(), cell, condition.c_str(), replacement.c_str());
if (replace)
module->connect(cell->getPort(ID::Y), replace_sig);
module->remove(cell);
@ -2295,7 +2295,7 @@ struct OptExprPass : public Pass {
NewCellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
log("Optimizing module %s.\n", module);
if (undriven) {
did_something = false;

26
passes/opt/opt_hier.cc
View file

@ -101,7 +101,7 @@ struct ModuleIndex {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
log_id(port_name), log_id(instantiation), log_id(module));
port_name.unescape(), instantiation, module);
}
if (port->port_input && port->port_output) {
@ -145,12 +145,12 @@ struct ModuleIndex {
if (nunused > 0) {
log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
nunused, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
if (nconstants > 0) {
log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
nconstants, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
}
@ -189,7 +189,7 @@ struct ModuleIndex {
if (ntie_togethers > 0) {
log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n",
ntie_togethers, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
ntie_togethers, instantiation, instantiation->type.unescape(), parent.module);
changed = true;
}
@ -290,7 +290,7 @@ struct UsageData {
if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
log_error("Port %s connected on instance %s not found in module %s"
" or width is not matching\n",
log_id(port_name), log_id(instance), log_id(module));
port_name.unescape(), instance, module);
}
if (port->port_input && port->port_output) {
@ -347,7 +347,7 @@ struct UsageData {
};
module->rewrite_sigspecs(disconnect_rewrite);
for (auto chunk : disconnect_outputs.chunks()) {
log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), log_id(module));
log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), module);
did_something = true;
module->connect(chunk, SigSpec(RTLIL::Sx, chunk.size()));
}
@ -368,7 +368,7 @@ struct UsageData {
SigSpec const_ = chunk;
const_.replace(constant_inputs);
log("Substituting constant %s for input terminal '%s' in module '%s'\n",
log_signal(const_), log_signal(chunk), log_id(module));
log_signal(const_), log_signal(chunk), module);
}
// Propagate tied-together inputs
@ -397,7 +397,7 @@ struct UsageData {
module->rewrite_sigspecs(ties_rewrite);
if (applied_ties.size()) {
log("Replacing %zu input terminal bits with tie-togethers in module '%s'\n",
applied_ties.size(), log_id(module));
applied_ties.size(), module);
}
return did_something;
}
@ -433,7 +433,7 @@ struct OptHierPass : Pass {
dict<IdString, ModuleIndex> indices;
for (auto module : d->modules()) {
log_debug("Building index for %s\n", log_id(module));
log_debug("Building index for %s\n", module);
indices.emplace(module->name, ModuleIndex(module));
}
@ -442,14 +442,14 @@ struct OptHierPass : Pass {
if (module->get_bool_attribute(ID::top))
continue;
log_debug("Starting usage data for %s\n", log_id(module));
log_debug("Starting usage data for %s\n", module);
usage_datas.emplace(module->name, UsageData(module));
}
for (auto module : d->modules()) {
for (auto cell : module->cells()) {
if (usage_datas.count(cell->type)) {
log_debug("Account for instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
log_debug("Account for instance %s of %s in %s\n", cell, cell->type.unescape(), module);
usage_datas.at(cell->type).refine(cell, indices.at(module->name));
}
}
@ -460,13 +460,13 @@ struct OptHierPass : Pass {
ModuleIndex &parent_index = indices.at(module->name);
if (usage_datas.count(module->name)) {
log_debug("Applying usage data changes to %s\n", log_id(module));
log_debug("Applying usage data changes to %s\n", module);
did_something |= usage_datas.at(module->name).apply_changes(parent_index);
}
for (auto cell : module->cells()) {
if (indices.count(cell->type)) {
log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
log_debug("Applying changes to instance %s of %s in %s\n", cell, cell->type.unescape(), module);
did_something |= indices.at(cell->type).apply_changes(parent_index, cell);
}
}

12
passes/opt/opt_lut.cc
View file

@ -121,7 +121,7 @@ struct OptLutWorker
SigSpec lut_input = cell->getPort(ID::A);
int lut_arity = 0;
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, module, cell);
luts.insert(cell);
// First, find all dedicated logic we're connected to. This results in an overapproximation
@ -162,7 +162,7 @@ struct OptLutWorker
{
if (lut_width <= dlogic_conn.first)
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first);
legal = false;
break;
@ -173,7 +173,7 @@ struct OptLutWorker
if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0]))
{
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));
legal = false;
break;
@ -182,7 +182,7 @@ struct OptLutWorker
if (legal)
{
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second));
log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, module, lut_dlogic.second);
lut_legal_dlogics.insert(lut_dlogic);
for (auto &dlogic_conn : dlogic_map)
lut_dlogic_inputs.insert(dlogic_conn.first);
@ -258,7 +258,7 @@ struct OptLutWorker
if (const0_match || const1_match || input_match != -1)
{
log_debug("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
log_debug("Found redundant cell %s.%s.\n", module, lut);
SigBit value;
if (const0_match)
@ -341,7 +341,7 @@ struct OptLutWorker
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", module, lutA, module, lutB);
if (index.query_is_output(lutA->getPort(ID::Y)))
{

4
passes/opt/opt_lut_ins.cc
View file

@ -64,7 +64,7 @@ struct OptLutInsPass : public Pass {
for (auto module : design->selected_modules())
{
log("Optimizing LUTs in %s.\n", log_id(module));
log("Optimizing LUTs in %s.\n", module);
std::vector<Cell *> remove_cells;
// Gather LUTs.
@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
}
if (!doit)
continue;
log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
log(" Optimizing lut %s (%d -> %d)\n", cell, GetSize(inputs), GetSize(new_inputs));
if (techname == "lattice" || techname == "ecp5") {
// Pad the LUT to 4 inputs, adding consts from the front.
int extra = 4 - GetSize(new_inputs);

6
passes/opt/opt_mem.cc
View file

@ -108,13 +108,13 @@ struct OptMemPass : public Pass {
}
State bit;
if (!always_0[i]) {
log("%s.%s: removing const-1 lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-1 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::S1;
} else if (!always_1[i]) {
log("%s.%s: removing const-0 lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-0 lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::S0;
} else {
log("%s.%s: removing const-x lane %d\n", log_id(module->name), log_id(mem.memid), i);
log("%s.%s: removing const-x lane %d\n", module->name.unescape(), mem.memid.unescape(), i);
bit = State::Sx;
}
// Reconnect read port data.

4
passes/opt/opt_mem_feedback.cc
View file

@ -163,7 +163,7 @@ struct OptMemFeedbackWorker
{
auto &port = mem.wr_ports[i];
log(" Analyzing %s.%s write port %d.\n", log_id(module), log_id(mem.memid), i);
log(" Analyzing %s.%s write port %d.\n", module, mem.memid.unescape(), i);
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
{
@ -232,7 +232,7 @@ struct OptMemFeedbackWorker
// Okay, let's do it.
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid));
log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", module, mem.memid.unescape());
// If a write port has a feedback path that we're about to bypass,
// but also has priority over some other write port, the feedback

2
passes/opt/opt_mem_widen.cc
View file

@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass {
factor_log2 = port.wide_log2;
if (factor_log2 == 0)
continue;
log("Widening base width of memory %s in module %s by factor %d.\n", log_id(mem.memid), log_id(module->name), 1 << factor_log2);
log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), module->name.unescape(), 1 << factor_log2);
total_count++;
// The inits are too messy to expand one-by-one, for they may
// collide with one another after expansion. Just hit it with

12
passes/opt/opt_muxtree.cc
View file

@ -229,7 +229,7 @@ struct OptMuxtreeWorker
for (int mux_idx = 0; mux_idx < GetSize(root_muxes); mux_idx++)
if (root_muxes.at(mux_idx)) {
log_debug(" Root of a mux tree: %s%s\n", log_id(mux2info[mux_idx].cell), root_enable_muxes.at(mux_idx) ? " (pure)" : "");
log_debug(" Root of a mux tree: %s%s\n", mux2info[mux_idx].cell, root_enable_muxes.at(mux_idx) ? " (pure)" : "");
root_mux_rerun.erase(mux_idx);
eval_root_mux(mux_idx);
if (glob_evals_left == 0) {
@ -240,7 +240,7 @@ struct OptMuxtreeWorker
while (!root_mux_rerun.empty()) {
int mux_idx = *root_mux_rerun.begin();
log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", log_id(mux2info[mux_idx].cell));
log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", mux2info[mux_idx].cell);
log_assert(root_enable_muxes.at(mux_idx));
root_mux_rerun.erase(mux_idx);
eval_root_mux(mux_idx);
@ -437,7 +437,7 @@ struct OptMuxtreeWorker
// Ran out of subtree depth, re-eval this input tree in the next re-run
root_mux_rerun.insert(m);
root_enable_muxes.at(m) = true;
log_debug(" Removing pure flag from root mux %s.\n", log_id(mux2info[m].cell));
log_debug(" Removing pure flag from root mux %s.\n", mux2info[m].cell);
} else {
auto new_limits = limits.subtree();
// Since our knowledge includes assumption,
@ -517,8 +517,8 @@ struct OptMuxtreeWorker
}
if (did_something) {
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", log_id(portname),
log_id(muxinfo.cell), log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", portname.unescape(),
muxinfo.cell, log_signal(muxinfo.cell->getPort(portname)), log_signal(sig));
muxinfo.cell->setPort(portname, sig);
}
}
@ -530,7 +530,7 @@ struct OptMuxtreeWorker
glob_evals_left--;
muxinfo_t &muxinfo = mux2info[mux_idx];
log_debug("\t\teval %s (replace %d enable %d)\n", log_id(muxinfo.cell), limits.do_replace_known, limits.do_mark_ports_observable);
log_debug("\t\teval %s (replace %d enable %d)\n", muxinfo.cell, limits.do_replace_known, limits.do_mark_ports_observable);
// set input ports to constants if we find known active or inactive signals
if (limits.do_replace_known) {

4
passes/opt/opt_share.cc
View file

@ -560,9 +560,9 @@ struct OptSharePass : public Pass {
log(" Found cells that share an operand and can be merged by moving the %s %s in front "
"of "
"them:\n",
log_id(shared.mux->type), log_id(shared.mux));
shared.mux->type.unescape(), shared.mux);
for (const auto& op : shared.ports)
log(" %s\n", log_id(op.op));
log(" %s\n", op.op);
log("\n");
merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap);

2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -44,7 +44,7 @@ endmatch
code
log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
log_id(module), log_id(latch), log_id(and_gate));
module, latch, and_gate);
// Add a flip-flop and rewire the AND gate to use the output of this flop
// instead of the latch. We don't delete the latch in case its output is

2
passes/opt/peepopt_muldiv.pmg
View file

@ -32,7 +32,7 @@ code
val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
did_something = true;
log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv pattern in %s: mul=%s, div=%s\n", module, mul, div);
module->connect(div_y, val_y);
autoremove(div);
accept;

2
passes/opt/peepopt_muldiv_c.pmg
View file

@ -119,7 +119,7 @@ code
autoremove(div);
// Log, fixup, accept
log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div);
mul->fixup_parameters();
accept;
endcode

2
passes/opt/peepopt_shiftadd.pmg
View file

@ -112,7 +112,7 @@ code
did_something = true;
log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
log_id(module), log_id(shift), log_id(add), offset);
module, shift, add, offset);
SigSpec new_a;
if(offset<0) {

2
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -99,7 +99,7 @@ code
}
did_something = true;
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

2
passes/opt/peepopt_shiftmul_right.pmg
View file

@ -76,7 +76,7 @@ code
reject;
did_something = true;
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

12
passes/opt/pmux2shiftx.cc
View file

@ -390,7 +390,7 @@ struct Pmux2ShiftxPass : public Pass {
if (verbose) {
printed_pmux_header = true;
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
log("Inspecting $pmux cell %s/%s.\n", module, cell);
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
@ -441,7 +441,7 @@ struct Pmux2ShiftxPass : public Pass {
if (!printed_pmux_header) {
printed_pmux_header = true;
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
log("Inspecting $pmux cell %s/%s.\n", module, cell);
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
@ -714,7 +714,7 @@ struct Pmux2ShiftxPass : public Pass {
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
log(" created $shiftx cell %s.\n", log_id(c));
log(" created $shiftx cell %s.\n", c);
// remove this sig and continue with the next block
seldb.erase(sig);
@ -799,7 +799,7 @@ struct OnehotPass : public Pass {
continue;
if (verbose)
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), module, cell);
if (!onehot_db.query(A)) {
if (verbose)
@ -831,7 +831,7 @@ struct OnehotPass : public Pass {
if (verbose)
log(" replacing with constant 0 driver.\n");
else
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), module, cell);
module->connect(Y, SigSpec(1, GetSize(Y)));
}
else
@ -840,7 +840,7 @@ struct OnehotPass : public Pass {
if (verbose)
log(" replacing with signal %s.\n", log_signal(sig));
else
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), log_id(module), log_id(cell), log_signal(sig));
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), module, cell, log_signal(sig));
sig.extend_u0(GetSize(Y));
module->connect(Y, sig);
}

38
passes/opt/share.cc
View file

@ -958,7 +958,7 @@ struct ShareWorker
optimize_activation_patterns(activation_patterns_cache[cell]);
if (activation_patterns_cache[cell].empty()) {
log("%sFound cell that is never activated: %s\n", indent, log_id(cell));
log("%sFound cell that is never activated: %s\n", indent, cell);
RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell];
module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size())));
cells_to_remove.insert(cell);
@ -1123,7 +1123,7 @@ struct ShareWorker
for (auto &loop : toposort.loops) {
log("### loop ###\n");
for (auto &c : loop)
log("%s (%s)\n", log_id(c), log_id(c->type));
log("%s (%s)\n", c, c->type.unescape());
}
return found_scc;
@ -1240,14 +1240,14 @@ struct ShareWorker
return;
log("Found %d cells in module %s that may be considered for resource sharing.\n",
GetSize(shareable_cells), log_id(module));
GetSize(shareable_cells), module);
while (!shareable_cells.empty() && config.limit != 0)
{
RTLIL::Cell *cell = *shareable_cells.begin();
shareable_cells.erase(cell);
log(" Analyzing resource sharing options for %s (%s):\n", log_id(cell), log_id(cell->type));
log(" Analyzing resource sharing options for %s (%s):\n", cell, cell->type.unescape());
const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " ");
RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
@ -1275,12 +1275,12 @@ struct ShareWorker
log(" Found %d candidates:", GetSize(candidates));
for (auto c : candidates)
log(" %s", log_id(c));
log(" %s", c);
log("\n");
for (auto other_cell : candidates)
{
log(" Analyzing resource sharing with %s (%s):\n", log_id(other_cell), log_id(other_cell->type));
log(" Analyzing resource sharing with %s (%s):\n", other_cell, other_cell->type.unescape());
const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " ");
RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
@ -1332,13 +1332,13 @@ struct ShareWorker
RTLIL::SigSpec all_ctrl_signals;
for (auto &p : filtered_cell_activation_patterns) {
log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
log(" Activation pattern for cell %s: %s = %s\n", cell, log_signal(p.first), log_signal(p.second));
cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
all_ctrl_signals.append(p.first);
}
for (auto &p : filtered_other_cell_activation_patterns) {
log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
log(" Activation pattern for cell %s: %s = %s\n", other_cell, log_signal(p.first), log_signal(p.second));
other_cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));
all_ctrl_signals.append(p.first);
}
@ -1349,13 +1349,13 @@ struct ShareWorker
qcsat.prepare();
if (!qcsat.ez->solve(sub1)) {
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell));
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", cell);
cells_to_remove.insert(cell);
break;
}
if (!qcsat.ez->solve(sub2)) {
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell));
log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", other_cell);
cells_to_remove.insert(other_cell);
shareable_cells.erase(other_cell);
continue;
@ -1391,20 +1391,20 @@ struct ShareWorker
if (restrict_activation_patterns(optimized_cell_activation_patterns, optimized_other_cell_activation_patterns)) {
for (auto &p : optimized_cell_activation_patterns)
log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
log(" Simplified activation pattern for cell %s: %s = %s\n", cell, log_signal(p.first), log_signal(p.second));
for (auto &p : optimized_other_cell_activation_patterns)
log(" Simplified activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
log(" Simplified activation pattern for cell %s: %s = %s\n", other_cell, log_signal(p.first), log_signal(p.second));
}
}
if (find_in_input_cone(cell, other_cell)) {
log(" Sharing not possible: %s is in input cone of %s.\n", log_id(other_cell), log_id(cell));
log(" Sharing not possible: %s is in input cone of %s.\n", other_cell, cell);
continue;
}
if (find_in_input_cone(other_cell, cell)) {
log(" Sharing not possible: %s is in input cone of %s.\n", log_id(cell), log_id(other_cell));
log(" Sharing not possible: %s is in input cone of %s.\n", cell, other_cell);
continue;
}
@ -1424,14 +1424,14 @@ struct ShareWorker
if (cell_select_score <= other_cell_select_score) {
RTLIL::SigSpec act = make_cell_activation_logic(optimized_cell_activation_patterns, supercell_aux);
supercell = make_supercell(cell, other_cell, act, supercell_aux);
log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act));
log(" Activation signal for %s: %s\n", cell, log_signal(act));
} else {
RTLIL::SigSpec act = make_cell_activation_logic(optimized_other_cell_activation_patterns, supercell_aux);
supercell = make_supercell(other_cell, cell, act, supercell_aux);
log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act));
log(" Activation signal for %s: %s\n", other_cell, log_signal(act));
}
log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type));
log(" New cell: %s (%s)\n", supercell, supercell->type.unescape());
cells_to_remove.insert(cell);
cells_to_remove.insert(other_cell);
@ -1476,9 +1476,9 @@ struct ShareWorker
}
if (!cells_to_remove.empty()) {
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), log_id(module));
log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), module);
for (auto c : cells_to_remove) {
log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type));
log(" Removing cell %s (%s).\n", c, c->type.unescape());
remove_cell(c);
}
}

30
passes/opt/wreduce.cc
View file

@ -104,14 +104,14 @@ struct WreduceWorker
sig_removed.append(bits_removed[i]);
if (GetSize(bits_removed) == GetSize(sig_y)) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->connect(sig_y, sig_removed);
module->remove(cell);
return;
}
log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type));
GetSize(sig_removed), GetSize(sig_y), module, cell, cell->type.unescape());
int n_removed = GetSize(sig_removed);
int n_kept = GetSize(sig_y) - GetSize(sig_removed);
@ -204,13 +204,13 @@ struct WreduceWorker
return;
if (GetSize(sig_q) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->remove(cell);
return;
}
log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
for (auto bit : sig_d)
work_queue_bits.insert(bit);
@ -258,7 +258,7 @@ struct WreduceWorker
if (bits_removed) {
log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescape());
cell->setPort(stringf("\\%c", port), sig);
did_something = true;
}
@ -331,7 +331,7 @@ struct WreduceWorker
if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) {
log("Converting cell %s.%s (%s) from unsigned to signed.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 1);
cell->setParam(ID::B_SIGNED, 1);
port_a_signed = true;
@ -339,7 +339,7 @@ struct WreduceWorker
did_something = true;
} else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
@ -359,7 +359,7 @@ struct WreduceWorker
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
@ -372,7 +372,7 @@ struct WreduceWorker
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
module, cell, cell->type.unescape());
cell->setParam(ID::A_SIGNED, 0);
port_a_signed = false;
did_something = true;
@ -431,14 +431,14 @@ struct WreduceWorker
}
if (GetSize(sig) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removed cell %s.%s (%s).\n", module, cell, cell->type.unescape());
module->remove(cell);
return;
}
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
cell->setPort(ID::Y, sig);
did_something = true;
}
@ -510,7 +510,7 @@ struct WreduceWorker
if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)])
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), module, w);
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
@ -603,7 +603,7 @@ struct WreducePass : public Pass {
}
if (original_a_width != GetSize(A)) {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
c->setPort(ID::A, A);
c->setParam(ID::A_WIDTH, GetSize(A));
}
@ -619,7 +619,7 @@ struct WreducePass : public Pass {
}
if (original_b_width != GetSize(B)) {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
c->setPort(ID::B, B);
c->setParam(ID::B_WIDTH, GetSize(B));
}
@ -635,7 +635,7 @@ struct WreducePass : public Pass {
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits,
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid));
module, c, memid.unescape());
c->setParam(ID::ABITS, max_addrbits);
c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
}

4
passes/pmgen/README.md
View file

@ -34,8 +34,8 @@ for the pattern`<pattern_name>` and calls the callback function for each found
match:
pm.run_foobar([&](){
log("found matching 'foo' cell: %s\n", log_id(pm.st.foo));
log(" with 'bar' cell: %s\n", log_id(pm.st.bar));
log("found matching 'foo' cell: %s\n", pm.st.foo);
log(" with 'bar' cell: %s\n", pm.st.bar);
});
The `.pmg` file declares matcher state variables that are accessible via the

4
passes/pmgen/generate.h
View file

@ -106,7 +106,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
if (found_match) {
Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d",
pmclass, pattern, modcnt++));
log("Creating module %s with %d cells.\n", log_id(m), cellcnt);
log("Creating module %s with %d cells.\n", m, cellcnt);
mod->cloneInto(m);
pmtest_addports(m);
mods.push_back(m);
@ -126,7 +126,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
}
Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern));
log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods));
log("Creating module %s with %d cells.\n", m, GetSize(mods));
for (auto mod : mods) {
Cell *c = m->addCell(mod->name, mod->name);
for (auto port : mod->ports) {

16
passes/pmgen/test_pmgen.cc
View file

@ -37,7 +37,7 @@ void reduce_chain(test_pmgen_pm &pm)
if (ud.longest_chain.empty())
return;
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
SigSpec A;
SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y);
@ -51,7 +51,7 @@ void reduce_chain(test_pmgen_pm &pm)
} else {
A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
}
log(" %s\n", log_id(cell));
log(" %s\n", cell);
pm.autoremove(cell);
}
@ -66,7 +66,7 @@ void reduce_chain(test_pmgen_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void reduce_tree(test_pmgen_pm &pm)
@ -81,8 +81,8 @@ void reduce_tree(test_pmgen_pm &pm)
SigSpec Y = st.first->getPort(ID::Y);
pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),
GetSize(A), log_signal(Y), log_id(st.first));
log("Found %s tree with %d leaves for %s (%s).\n", st.first->type.unescape(),
GetSize(A), log_signal(Y), st.first);
Cell *c;
@ -95,7 +95,7 @@ void reduce_tree(test_pmgen_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
void opt_eqpmux(test_pmgen_pm &pm)
@ -109,11 +109,11 @@ void opt_eqpmux(test_pmgen_pm &pm)
SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width);
log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n",
log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
log_signal(Y), st.eq, st.ne, st.pmux);
pm.autoremove(st.pmux);
Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
log(" -> %s (%s)\n", c, c->type.unescape());
}
struct TestPmgenPass : public Pass {

2
passes/proc/proc_arst.cc
View file

@ -215,7 +215,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
RTLIL::SigSpec en = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.enable, memwr.enable);
if (!en.is_fully_zero()) {
log_error("Async reset %s causes memory write to %s.\n",
log_signal(sync->signal), log_id(memwr.memid));
log_signal(sync->signal), memwr.memid.unescape());
}
apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.address, memwr.address);
apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.data, memwr.data);

2
passes/proc/proc_clean.cc
View file

@ -216,7 +216,7 @@ struct ProcCleanPass : public Pass {
if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
proc->root_case.actions.size() == 0) {
if (!quiet)
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name);
log("Removing empty process `%s.%s'.\n", mod, proc->name);
delme.push_back(proc);
}
}

2
passes/proc/proc_dlatch.cc
View file

@ -438,7 +438,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else
log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), log_id(cell));
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
}
offset += width;

2
passes/proc/proc_memwr.cc
View file

@ -75,7 +75,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
cell->setParam(ID::CLK_ENABLE, State::S1);
cell->setParam(ID::CLK_POLARITY, State::S0);
} else {
log_error("process memory write with unsupported sync type in %s.%s", log_id(mod), log_id(proc));
log_error("process memory write with unsupported sync type in %s.%s", mod, proc);
}
}
sr->mem_write_actions.clear();

4
passes/proc/proc_rmdead.cc
View file

@ -154,10 +154,10 @@ struct ProcRmdeadPass : public Pass {
proc_rmdead(switch_it, counter, full_case_counter);
if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter,
log_id(proc), log_id(mod));
proc, mod);
if (full_case_counter > 0)
log("Marked %d switch rules as full_case in process %s in module %s.\n",
full_case_counter, log_id(proc), log_id(mod));
full_case_counter, proc, mod);
total_counter += counter;
}
}

2
passes/sat/assertpmux.cc
View file

@ -148,7 +148,7 @@ struct AssertpmuxWorker
void run(Cell *pmux)
{
log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
log("Adding assert for $pmux cell %s.%s.\n", module, pmux);
int swidth = pmux->getParam(ID::S_WIDTH).as_int();
int cntbits = ceil_log2(swidth+1);

10
passes/sat/async2sync.cc
View file

@ -91,7 +91,7 @@ struct Async2syncPass : public Pass {
int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
if (trg_width > 1)
log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", log_id(cell));
log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", cell);
if (trg_width == 0) {
if (initstate == State::S0)
@ -147,7 +147,7 @@ struct Async2syncPass : public Pass {
ff.unmap_ce_srst();
log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -212,7 +212,7 @@ struct Async2syncPass : public Pass {
ff.unmap_ce_srst();
log("Replacing %s.%s (%s): ALOAD=%s, AD=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type,
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -245,7 +245,7 @@ struct Async2syncPass : public Pass {
ff.unmap_srst();
log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_arst), log_signal(ff.sig_d), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);
@ -279,7 +279,7 @@ struct Async2syncPass : public Pass {
{
// Latch.
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
initvals.remove_init(ff.sig_q);

18
passes/sat/clk2fflogic.cc
View file

@ -173,7 +173,7 @@ struct Clk2fflogicPass : public Pass {
auto &port = mem.rd_ports[i];
if (port.clk_enable)
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(mem.memid), log_id(module));
"Call \"memory\" with -nordff to avoid this error.\n", i, mem.memid.unescape(), module);
}
for (int i = 0; i < GetSize(mem.wr_ports); i++)
@ -184,10 +184,10 @@ struct Clk2fflogicPass : public Pass {
continue;
log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
i, log_id(module), log_id(mem.memid), log_signal(port.clk),
i, module, mem.memid.unescape(), log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_ID, port.clk, past_clk);
@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
module->addFf(NEW_ID, port.en, en_q);
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
module->addFf(NEW_ID, port.addr, addr_q);
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
module->addFf(NEW_ID, port.data, data_q);
port.clk = State::S0;
@ -291,16 +291,16 @@ struct Clk2fflogicPass : public Pass {
if (ff.has_clk) {
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
} else if (ff.has_aload) {
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
} else {
// $sr.
log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
}

8
passes/sat/cutpoint.cc
View file

@ -93,7 +93,7 @@ struct CutpointPass : public Pass {
for (auto module : design->all_selected_modules())
{
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
log("Making all outputs of module %s cut points, removing module contents.\n", module);
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))
module->remove(cell);
@ -125,7 +125,7 @@ struct CutpointPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($anyseq))
continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", module, cell);
for (auto &conn : cell->connections()) {
if (cell->output(conn.first)) {
bool do_cut = true;
@ -171,7 +171,7 @@ struct CutpointPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->port_output) {
log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
log("Making output wire %s.%s a cutpoint.\n", module, wire);
Wire *new_wire = module->addWire(NEW_ID, wire);
module->swap_names(wire, new_wire);
module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire)));
@ -180,7 +180,7 @@ struct CutpointPass : public Pass {
wire->port_output = false;
continue;
}
log("Making wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
log("Making wire %s.%s a cutpoint.\n", module, wire);
for (auto bit : sigmap(wire))
cutpoint_bits.insert(bit);
}

20
passes/sat/eval.cc
View file

@ -149,7 +149,7 @@ struct VlogHammerReporter
for (auto c : module->cells())
if (!satgen.importCell(c))
log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
log_error("Failed to import cell %s (type %s) to SAT database.\n", c->name.unescape(), c->type.unescape());
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
@ -262,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
log_error("Can't read back value for port %s!\n", inputs[i].unescape());
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, inputs[i].unescape(), sig.as_const().as_string());
}
}
if (module->wire(ID(y)) == nullptr)
log_error("No output wire (y) found in module %s!\n", log_id(module->name));
log_error("No output wire (y) found in module %s!\n", module->name.unescape());
RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", module, log_signal(sig), log_signal(undef));
log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), module->name.unescape());
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@ -288,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
log_error("Output (y) has a different width in module %s compared to rtl!\n", module->name.unescape());
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@ -319,10 +319,10 @@ struct VlogHammerReporter
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name, log_id(mod->name));
log_error("Can't find input %s in module %s!\n", name, mod->name.unescape());
RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name, log_id(mod->name));
log_error("Wire %s in module %s is not an input!\n", name, mod->name.unescape());
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
@ -443,7 +443,7 @@ struct EvalPass : public Pass {
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
log_id(module->name), log_id(mod->name));
module->name.unescape(), mod->name.unescape());
module = mod;
}
if (module == NULL)

4
passes/sat/expose.cc
View file

@ -210,7 +210,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", name.unescape());
return module->addWire(name, width);
}
@ -673,7 +673,7 @@ struct ExposePass : public Pass {
}
for (auto cell : delete_cells) {
log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type));
log("Removing cell: %s/%s (%s)\n", module, cell, cell->type.unescape());
module->remove(cell);
}
}

16
passes/sat/fmcombine.cc
View file

@ -77,7 +77,7 @@ struct FmcombineWorker
void import_hier_cell(Cell *cell)
{
if (!cell->parameters.empty())
log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", log_id(original), log_id(cell));
log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", original, cell);
FmcombineWorker sub_worker(design, cell->type, opts);
sub_worker.generate();
@ -95,11 +95,11 @@ struct FmcombineWorker
void generate()
{
if (design->module(combined_type)) {
// log("Combined module %s already exists.\n", log_id(combined_type));
// log("Combined module %s already exists.\n", combined_type.unescape());
return;
}
log("Generating combined module %s from module %s.\n", log_id(combined_type), log_id(orig_type));
log("Generating combined module %s from module %s.\n", combined_type.unescape(), orig_type.unescape());
module = design->addModule(combined_type);
for (auto wire : original->wires()) {
@ -332,15 +332,15 @@ struct FmcombinePass : public Pass {
module = design->module(module_name);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", log_id(module_name));
log_cmd_error("Module %s not found.\n", module_name.unescape());
gold_cell = module->cell(gold_name);
if (gold_cell == nullptr)
log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gold_name), log_id(module));
log_cmd_error("Gold cell %s not found in module %s.\n", gold_name.unescape(), module);
gate_cell = module->cell(gate_name);
if (gate_cell == nullptr)
log_cmd_error("Gate cell %s not found in module %s.\n", log_id(gate_name), log_id(module));
log_cmd_error("Gate cell %s not found in module %s.\n", gate_name.unescape(), module);
}
else
{
@ -363,13 +363,13 @@ struct FmcombinePass : public Pass {
FmcombineWorker worker(design, gold_cell->type, opts);
worker.generate();
IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", log_id(gold_cell), log_id(gate_cell)));
IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", gold_cell, gate_cell));
Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
cell->attributes = gold_cell->attributes;
cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src));
log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
log("Combining cells %s and %s in module %s into new cell %s.\n", gold_cell, gate_cell, module, cell);
for (auto &conn : gold_cell->connections())
cell->setPort(conn.first.str() + "_gold", conn.second);

62
passes/sat/formalff.cc
View file

@ -402,7 +402,7 @@ struct PropagateWorker
sigmap.apply(bit);
if (replaced_clk_bits.count(bit))
log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n",
log_signal(bit), log_id(cell->name), log_id(cell->type), log_id(module));
log_signal(bit), cell->name.unescape(), cell->type.unescape(), module);
}
}
}
@ -436,7 +436,7 @@ struct PropagateWorker
if (it != replaced_clk_bits.end()) {
if (it->second != polarity)
log_error("signal %s from module %s is used as clock with different polarities, run clk2fflogic instead.\n",
log_signal(bit), log_id(module));
log_signal(bit), module);
return;
}
@ -659,7 +659,7 @@ struct FormalFfPass : public Pass {
// XXX $check $print
}
log_debug("%s has %d clk bits\n", log_id(module), GetSize(clk_bits));
log_debug("%s has %d clk bits\n", module, GetSize(clk_bits));
for (auto port : module->ports) {
Wire *wire = module->wire(port);
@ -675,7 +675,7 @@ struct FormalFfPass : public Pass {
}
}
}
log_debug("%s has %d non-input clk bits\n", log_id(module), GetSize(clk_bits));
log_debug("%s has %d non-input clk bits\n", module, GetSize(clk_bits));
if (clk_bits.empty())
continue;
@ -687,21 +687,21 @@ struct FormalFfPass : public Pass {
vector<Cell *> &clocked_cells = clk_bit.second;
if (!clk.is_wire()) {
log_debug("constant clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("constant clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
if (input_bits.count(clk)) {
log_debug("input clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("input clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
auto found = modwalker.signal_drivers.find(clk);
if (found == modwalker.signal_drivers.end() || found->second.empty()) {
log_debug("undriven clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("undriven clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
if (found->second.size() > 1) {
log_debug("multiple drivers for clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
log_debug("multiple drivers for clk bit %s.%s\n", module, log_signal(SigSpec(clk)));
continue;
}
@ -711,9 +711,9 @@ struct FormalFfPass : public Pass {
pol_clk ? driver.cell->type.in(ID($and), ID($_AND_)) : driver.cell->type.in(ID($or), ID($_OR_));
if (!is_gate) {
log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", log_id(module),
log_id(driver.cell), log_id(driver.cell->type), pol_clk ? "posedge" : "negedge",
log_id(module), log_signal(SigSpec(clk)));
log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", module,
driver.cell, driver.cell->type.unescape(), pol_clk ? "posedge" : "negedge",
module, log_signal(SigSpec(clk)));
continue;
}
@ -724,28 +724,28 @@ struct FormalFfPass : public Pass {
for (int i = 0; i < 2; i++) {
std::swap(gate_clock, gate_enable);
log_debug("clock %s.%s for gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_clock)),
log_id(module), log_signal(SigSpec(clk)));
log_debug("enable %s.%s for gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_enable)),
log_id(module), log_signal(SigSpec(clk)));
log_debug("clock %s.%s for gated clk bit %s.%s\n", module, log_signal(SigSpec(gate_clock)),
module, log_signal(SigSpec(clk)));
log_debug("enable %s.%s for gated clk bit %s.%s\n", module, log_signal(SigSpec(gate_enable)),
module, log_signal(SigSpec(clk)));
found = modwalker.signal_drivers.find(gate_enable);
if (found == modwalker.signal_drivers.end() || found->second.empty()) {
log_debug("undriven gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
log_debug("undriven gate enable %s.%s of gated clk bit %s.%s\n", module,
log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)));
continue;
}
if (found->second.size() > 1) {
log_debug("multiple drivers for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
log_debug("multiple drivers for gate enable %s.%s of gated clk bit %s.%s\n", module,
log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)));
continue;
}
auto gate_driver = *found->second.begin();
if (!gate_driver.cell->is_builtin_ff()) {
log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", module,
log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)));
continue;
}
@ -753,8 +753,8 @@ struct FormalFfPass : public Pass {
if (ff.has_gclk || ff.has_ce || ff.has_sr || ff.has_srst || ff.has_arst || (ff.has_aload && ff.has_clk)) {
log_debug(
"FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible type: %s\n",
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)),
log_id(gate_driver.cell->type));
module, log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)),
gate_driver.cell->type.unescape());
continue;
}
@ -770,8 +770,8 @@ struct FormalFfPass : public Pass {
if (!ff.has_clk || sigmap(ff.sig_clk) != gate_clock || ff.pol_clk != pol_clk) {
log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: "
"%s %s.%s\n",
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module),
log_signal(SigSpec(clk)), ff.pol_clk ? "posedge" : "negedge", log_id(module),
module, log_signal(SigSpec(gate_enable)), module,
log_signal(SigSpec(clk)), ff.pol_clk ? "posedge" : "negedge", module,
log_signal(SigSpec(ff.sig_clk)));
continue;
}
@ -781,8 +781,8 @@ struct FormalFfPass : public Pass {
log_debug("found clock gate, rewriting %d cells\n", GetSize(clocked_cells));
for (auto clocked_cell : clocked_cells) {
log_debug("rewriting cell %s.%s (%s)\n", log_id(module), log_id(clocked_cell),
log_id(clocked_cell->type));
log_debug("rewriting cell %s.%s (%s)\n", module, clocked_cell,
clocked_cell->type.unescape());
if (clocked_cell->is_builtin_ff()) {
@ -855,7 +855,7 @@ struct FormalFfPass : public Pass {
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
log_id(module), log_id(cell), log_id(cell->type),
module, cell, cell->type.unescape(),
log_const(before), log_const(ff.val_init));
worker.initvals.set_init(ff.sig_q, ff.val_init);
}
@ -892,10 +892,10 @@ struct FormalFfPass : public Pass {
if (flag_clk2ff && ff.has_clk) {
if (ff.sig_clk.is_fully_const())
log_error("Const CLK on %s (%s) from module %s, run async2sync first.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type, module);
if (ff.has_aload || ff.has_arst || ff.has_sr)
log_error("Async inputs on %s (%s) from module %s, run async2sync first.\n",
log_id(cell), log_id(cell->type), log_id(module));
cell, cell->type.unescape(), module);
auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
@ -912,7 +912,7 @@ struct FormalFfPass : public Pass {
if (!attr.empty() && attr != clk_polarity)
log_error("CLK %s on %s (%s) from module %s also used with opposite polarity, run clk2fflogic instead.\n",
log_id(clk_wire), log_id(cell), log_id(cell->type), log_id(module));
clk_wire, cell, cell->type.unescape(), module);
attr = clk_polarity;
clk_wire->set_bool_attribute(ID::keep);

38
passes/sat/mutate.cc
View file

@ -558,7 +558,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (opts.none) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
log("%s\n", str);
@ -569,20 +569,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &entry : database) {
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -ctrl %s %d %d", opts.ctrl_name.unescape(), opts.ctrl_width, ctrl_value++);
str += stringf(" -mode %s", entry.mode);
if (!entry.module.empty())
str += stringf(" -module %s", log_id(entry.module));
str += stringf(" -module %s", entry.module.unescape());
if (!entry.cell.empty())
str += stringf(" -cell %s", log_id(entry.cell));
str += stringf(" -cell %s", entry.cell.unescape());
if (!entry.port.empty())
str += stringf(" -port %s", log_id(entry.port));
str += stringf(" -port %s", entry.port.unescape());
if (entry.portbit >= 0)
str += stringf(" -portbit %d", entry.portbit);
if (entry.ctrlbit >= 0)
str += stringf(" -ctrlbit %d", entry.ctrlbit);
if (!entry.wire.empty())
str += stringf(" -wire %s", log_id(entry.wire));
str += stringf(" -wire %s", entry.wire.unescape());
if (entry.wirebit >= 0)
str += stringf(" -wirebit %d", entry.wirebit);
for (auto &s : entry.src)
@ -600,7 +600,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
if (ctrl_wire == nullptr)
{
log("Adding ctrl port %s to module %s.\n", log_id(name), log_id(module));
log("Adding ctrl port %s to module %s.\n", name.unescape(), module);
ctrl_wire = module->addWire(name, width);
ctrl_wire->port_input = true;
@ -614,7 +614,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
SigSpec ctrl = mutate_ctrl_sig(mod, name, width);
log("Connecting ctrl port to cell %s in module %s.\n", log_id(cell), log_id(mod));
log("Connecting ctrl port to cell %s in module %s.\n", cell, mod);
cell->setPort(name, ctrl);
}
}
@ -652,13 +652,13 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
if (cell->input(opts.port))
{
log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add input inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
SigBit outbit = module->Not(NEW_ID, bit);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = module->Not(NEW_ID, inbit);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -680,13 +680,13 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
SigBit outbit = one ? State::S1 : State::S0;
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? State::S1 : State::S0;
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -709,13 +709,13 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@ -947,26 +947,26 @@ struct MutatePass : public Pass {
Module *module = design->module(opts.module);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", log_id(opts.module));
log_cmd_error("Module %s not found.\n", opts.module.unescape());
if (opts.cell.empty())
log_cmd_error("Missing -cell argument.\n");
Cell *cell = module->cell(opts.cell);
if (cell == nullptr)
log_cmd_error("Cell %s not found in module %s.\n", log_id(opts.cell), log_id(opts.module));
log_cmd_error("Cell %s not found in module %s.\n", opts.cell.unescape(), opts.module.unescape());
if (opts.port.empty())
log_cmd_error("Missing -port argument.\n");
if (!cell->hasPort(opts.port))
log_cmd_error("Port %s not found on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
log_cmd_error("Port %s not found on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
if (opts.portbit < 0)
log_cmd_error("Missing -portbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
if (opts.mode == "inv") {
mutate_inv(design, opts);
@ -982,7 +982,7 @@ struct MutatePass : public Pass {
log_cmd_error("Missing -ctrlbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", opts.port.unescape(), opts.module.unescape(), opts.cell.unescape());
if (opts.mode == "cnot0" || opts.mode == "cnot1") {
mutate_cnot(design, opts, opts.mode == "cnot1");

2
passes/sat/qbfsat.cc
View file

@ -597,7 +597,7 @@ struct QbfSatPass : public Pass {
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the QBF-SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
log_cmd_error("Only one module must be selected for the QBF-SAT pass! (selected: %s and %s)\n", module, mod);
module = mod;
}
if (module == nullptr)

6
passes/sat/recover_names.cc
View file

@ -641,8 +641,8 @@ struct RecoverNamesWorker {
for (auto gate_bit : gate_bits) {
if (solved_gate.count(gate_bit.bit))
continue;
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", log_id(gold_bit.name), gold_bit.bit,
gate_bit.inverted ? "" : "!", log_id(gate_bit.bit.name), gate_bit.bit.bit);
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", gold_bit.name.unescape(), gold_bit.bit,
gate_bit.inverted ? "" : "!", gate_bit.bit.name.unescape(), gate_bit.bit.bit);
if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted))
continue;
log_debug(" success!\n");
@ -660,7 +660,7 @@ struct RecoverNamesWorker {
break;
}
}
log("Recovered %d net name pairs in module `%s' out.\n", GetSize(gate2gold), log_id(gate_mod));
log("Recovered %d net name pairs in module `%s' out.\n", GetSize(gate2gold), gate_mod);
gate_worker.do_rename(gold_mod, gate2gold, buffer_types);
}

2
passes/sat/sat.cc
View file

@ -1369,7 +1369,7 @@ struct SatPass : public Pass {
RTLIL::Module *module = NULL;
for (auto mod : design->selected_modules()) {
if (module)
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", module, mod);
module = mod;
}
if (module == NULL)

92
passes/sat/sim.cc
View file

@ -250,11 +250,11 @@ struct SimInstance
if (module->get_blackbox_attribute(true))
log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
log_id(module->name), hiername().c_str());
module->name.unescape(), hiername().c_str());
if (module->has_processes())
log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
log_id(module), hiername().c_str());
module, hiername().c_str());
if (parent) {
log_assert(parent->children.count(instance) == 0);
@ -413,9 +413,9 @@ struct SimInstance
std::string hiername() const
{
if (instance != nullptr)
return parent->hiername() + "." + log_id(instance->name);
return parent->hiername() + "." + instance->name.unescape();
return log_id(module->name);
return module->name.unescape();
}
vector<std::string> witness_full_path() const
@ -520,7 +520,7 @@ struct SimInstance
{
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, memid.unescape());
if (state.data[offset] != data) {
state.data.set(offset, data);
dirty_memories.insert(memid);
@ -573,7 +573,7 @@ struct SimInstance
if (has_y) sig_y = cell->getPort(ID::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type));
log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape());
bool err = false;
RTLIL::Const eval_state;
@ -593,7 +593,7 @@ struct SimInstance
err = true;
if (err)
log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
else
set_state(sig_y, eval_state);
return;
@ -602,7 +602,7 @@ struct SimInstance
if (cell->type == ID($print))
return;
log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
}
void update_memory(IdString id) {
@ -616,7 +616,7 @@ struct SimInstance
Const data = Const(State::Sx, mem.width << port.wide_log2);
if (port.clk_enable)
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid));
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, mem.memid.unescape());
if (addr.is_fully_def()) {
int addr_int = addr.as_int();
@ -819,14 +819,14 @@ struct SimInstance
log_assert(cell->module == module);
bool has_src = cell->has_attribute(ID::src);
log("%s %s%s\n", opening_verbiage,
log_id(cell), has_src ? " at" : "");
cell, has_src ? " at" : "");
log_source(cell);
struct SimInstance *sim = this;
while (sim->instance) {
has_src = sim->instance->has_attribute(ID::src);
log(" in instance %s of module %s%s\n", log_id(sim->instance),
log_id(sim->instance->type), has_src ? " at" : "");
log(" in instance %s of module %s%s\n", sim->instance,
sim->instance->type.unescape(), has_src ? " at" : "");
log_source(sim->instance);
sim = sim->parent;
}
@ -927,7 +927,7 @@ struct SimInstance
{
for (auto cell : formal_database)
{
string label = log_id(cell);
string label = cell->name.unescape();
if (cell->attributes.count(ID::src))
label = cell->attributes.at(ID::src).decode_string();
@ -939,17 +939,17 @@ struct SimInstance
}
if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
log("Cover %s.%s (%s) reached.\n", hiername(), log_id(cell), label);
log("Cover %s.%s (%s) reached.\n", hiername(), cell, label);
if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
log("Assumption %s.%s (%s) failed.\n", hiername(), cell, label);
if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
log_cell_w_hierarchy("Failed assertion", cell);
if (shared->serious_asserts)
log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
log_error("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
else
log_warning("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
log_warning("Assertion %s.%s (%s) failed.\n", hiername(), cell, label);
}
}
}
@ -970,7 +970,7 @@ struct SimInstance
{
if (!ff_database.empty() || !mem_database.empty()) {
if (wbmods.count(module))
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), log_id(module));
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), module);
wbmods.insert(module);
}
@ -1061,7 +1061,7 @@ struct SimInstance
for (auto name : hdlname)
exit_scope();
} else
register_signal(log_id(signal.first->name), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
register_signal(signal.first->name.unescape().c_str(), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
}
for (auto &trace_mem : trace_mem_database)
@ -1082,7 +1082,7 @@ struct SimInstance
for (auto name : hdlname)
enter_scope("\\" + name);
} else {
signal_name = log_id(memid);
signal_name = memid.unescape();
}
for (auto &trace_index : trace_mem.second) {
@ -1269,13 +1269,13 @@ struct SimInstance
Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
Const sim_val = get_state(item.first);
if (sim_val.size()!=fst_val.size()) {
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first));
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, item.first);
continue;
}
if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
for(int i=0;i<fst_val.size();i++) {
if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, item.first, log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
@ -1283,14 +1283,14 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
for(int i=0;i<sim_val.size();i++) {
if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, item.first, log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
}
} else {
if (fst_val!=sim_val) {
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope, item.first, log_signal(fst_val), log_signal(sim_val));
retVal = true;
}
}
@ -1409,7 +1409,7 @@ struct SimWorker : SimShared
Wire *w = top->module->wire(portname);
if (w == nullptr)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
top->set_state(w, value);
}
@ -1492,24 +1492,24 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
}
for (auto portname : clockn)
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
}
@ -1630,7 +1630,7 @@ struct SimWorker : SimShared
escaped_s = RTLIL::escape_id(cell_name(symbol));
Cell *c = topmod->cell(escaped_s);
if (!c)
log_warning("Wire/cell %s not present in module %s\n",symbol,log_id(topmod));
log_warning("Wire/cell %s not present in module %s\n",symbol,topmod);
if (c->is_mem_cell()) {
std::string memid = c->parameters.at(ID::MEMID).decode_string();
@ -1829,7 +1829,7 @@ struct SimWorker : SimShared
if (!w) {
Cell *c = topmod->cell(escaped_s);
if (!c)
log_warning("Wire/cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
log_warning("Wire/cell %s not present in module %s\n",escaped_s.unescape(),topmod);
else if (c->type.in(ID($anyconst), ID($anyseq))) {
SigSpec sig_y= c->getPort(ID::Y);
if ((int)parts[1].size() != GetSize(sig_y))
@ -1844,9 +1844,9 @@ struct SimWorker : SimShared
} else {
Cell *c = topmod->cell(escaped_s);
if (!c)
log_error("Cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod));
log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod);
if (!c->is_mem_cell())
log_error("Cell %s is not memory cell in module %s\n",log_id(escaped_s),log_id(topmod));
log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod);
Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
Const data = Const::from_string(parts[2]);
@ -2077,13 +2077,13 @@ struct SimWorker : SimShared
json.entry("version", "Yosys sim summary");
json.entry("generator", yosys_maybe_version());
json.entry("steps", step);
json.entry("top", log_id(top->module->name));
json.entry("top", top->module->name.unescape());
json.name("assertions");
json.begin_array();
for (auto &assertion : triggered_assertions) {
json.begin_object();
json.entry("step", assertion.step);
json.entry("type", log_id(assertion.cell->type));
json.entry("type", assertion.cell->type.unescape());
json.entry("path", assertion.instance->witness_full_path(assertion.cell));
auto src = assertion.cell->get_string_attribute(ID::src);
if (!src.empty()) {
@ -2148,12 +2148,12 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2161,12 +2161,12 @@ struct SimWorker : SimShared
{
Wire *w = topmod->wire(portname);
if (!w)
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module);
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape());
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2359,7 +2359,7 @@ struct VCDWriter : public OutputWriter
vcdfile << stringf("$timescale %s $end\n", worker->timescale);
worker->top->write_output_header(
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", name.unescape()); },
[this]() { vcdfile << stringf("$upscope $end\n");},
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2425,7 +2425,7 @@ struct FSTWriter : public OutputWriter
fstWriterSetRepackOnClose(fstfile, 1);
worker->top->write_output_header(
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
[this]() { fstWriterSetUpscope(fstfile); },
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2488,7 +2488,7 @@ struct AIWWriter : public OutputWriter
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
Wire *w = worker->top->module->wire(escaped_s);
if (!w)
log_error("Wire %s not present in module %s\n",log_id(escaped_s),log_id(worker->top->module));
log_error("Wire %s not present in module %s\n",escaped_s.unescape(),worker->top->module);
if (index < w->start_offset || index > w->start_offset + w->width)
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") {

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