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Simplify check -latchonly calls in synth.

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This commit is contained in:
nella 2026-07-07 10:10:00 +02:00
parent 6675c45e29
commit 362e828dc2
6 changed files with 6 additions and 18 deletions
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4
techlibs/quicklogic/synth_quicklogic.cc
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@ -330,10 +330,8 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (help_mode)
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");