3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00

consty stuff

This commit is contained in:
Emil J. Tywoniak 2024-06-13 12:35:31 +02:00
parent 2d6c45469f
commit 36289ab208
4 changed files with 72 additions and 23 deletions

View file

@ -345,7 +345,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
for (int i = 0; i < GetSize(q); i++) for (int i = 0; i < GetSize(q); i++)
dff_driver[q[i]] = std::make_pair(cell, i); dff_driver[q[i]] = std::make_pair(cell, i);
} }
for (auto &conn : cell->connections()) for (auto &&conn : cell->connections_)
if (!cell->known() || cell->input(conn.first)) if (!cell->known() || cell->input(conn.first))
for (auto bit : (*sigmap)(conn.second)) for (auto bit : (*sigmap)(conn.second))
sigbit_users_count[bit]++; sigbit_users_count[bit]++;

View file

@ -703,7 +703,7 @@ namespace {
res.packed = true; res.packed = true;
res.cell = cell; res.cell = cell;
res.attributes = cell->attributes; res.attributes = cell->attributes;
Const &init = cell->parameters.at(ID::INIT); const Const &init = cell->parameters.at(ID::INIT);
if (!init.is_fully_undef()) { if (!init.is_fully_undef()) {
int pos = 0; int pos = 0;
while (pos < res.size) { while (pos < res.size) {

View file

@ -2154,8 +2154,7 @@ void RTLIL::Module::add(RTLIL::Cell *cell)
log_assert(count_id(cell->name) == 0); log_assert(count_id(cell->name) == 0);
log_assert(refcount_cells_ == 0); log_assert(refcount_cells_ == 0);
cells_[cell->name] = cell; cells_[cell->name] = cell;
// TODO cell->module = this;
// cell->module = this;
} }
void RTLIL::Module::add(RTLIL::Process *process) void RTLIL::Module::add(RTLIL::Process *process)
@ -3475,7 +3474,7 @@ RTLIL::Process::Process() : module(nullptr)
hashidx_ = hashidx_count; hashidx_ = hashidx_count;
} }
RTLIL::Cell::Cell() RTLIL::Cell::Cell() : module(nullptr)
{ {
static unsigned int hashidx_count = 123456789; static unsigned int hashidx_count = 123456789;
hashidx_count = mkhash_xorshift(hashidx_count); hashidx_count = mkhash_xorshift(hashidx_count);
@ -3510,7 +3509,7 @@ void RTLIL::Cell::setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal
throw std::out_of_range("Cell::setPort()"); throw std::out_of_range("Cell::setPort()");
} }
} }
const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) { const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) const {
if (is_legacy()) if (is_legacy())
return legacy->getPort(portname); return legacy->getPort(portname);
@ -3547,19 +3546,49 @@ void RTLIL::Cell::setParam(const RTLIL::IdString &paramname, RTLIL::Const value)
} }
} }
// TODO autogen // // TODO autogen
const RTLIL::Const RTLIL::Cell::getParam(const RTLIL::IdString &paramname) { // const RTLIL::Const RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
// if (is_legacy())
// return legacy->getParam(paramname);
// if (type == ID($not)) {
// if (paramname == ID::A_WIDTH) {
// return RTLIL::Const(not_.a_width);
// } else if (paramname == ID::Y_WIDTH) {
// return RTLIL::Const(not_.y_width);
// } else {
// throw std::out_of_range("Cell::getParam()");
// }
// } else {
// throw std::out_of_range("Cell::getParam()");
// }
// }
const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) {
if (is_legacy()) if (is_legacy())
return legacy->getParam(paramname); return legacy->getParam(paramname);
if (type == ID($not)) { if (type == ID($not)) {
if (paramname == ID::A_WIDTH) { if (paramname == ID::A_WIDTH) {
// Notice using the trivial default constructor return not_.a_width;
// This is to reduce code changes later when we replace Const
// with int/bool where possible in internal cell type variants
return RTLIL::Const(not_.a_width);
} else if (paramname == ID::Y_WIDTH) { } else if (paramname == ID::Y_WIDTH) {
return RTLIL::Const(not_.y_width); return not_.y_width;
} else {
throw std::out_of_range("Cell::getParam()");
}
} else {
throw std::out_of_range("Cell::getParam()");
}
}
const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
if (is_legacy())
return legacy->getParam(paramname);
if (type == ID($not)) {
if (paramname == ID::A_WIDTH) {
return not_.a_width;
} else if (paramname == ID::Y_WIDTH) {
return not_.y_width;
} else { } else {
throw std::out_of_range("Cell::getParam()"); throw std::out_of_range("Cell::getParam()");
} }
@ -3750,7 +3779,7 @@ void RTLIL::Cell::check()
checker.check(); checker.check();
#endif #endif
} }
int bigboy() {return sizeof(RTLIL::Cell);}
void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
{ {
if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") || if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||

View file

@ -1629,7 +1629,8 @@ struct RTLIL::Unary {
}; };
// NewCell // NewCell
struct RTLIL::Cell // TODO attributes
struct RTLIL::Cell : RTLIL::AttrObject
{ {
// TODO huh? // TODO huh?
unsigned int hashidx_; unsigned int hashidx_;
@ -1642,7 +1643,8 @@ struct RTLIL::Cell
public: public:
RTLIL::IdString type; RTLIL::IdString type;
RTLIL::IdString name; // delete? RTLIL::IdString name; // TODO delete?
RTLIL::Module* module; // TODO delete
bool has_attrs; bool has_attrs;
union { union {
RTLIL::Unary not_; RTLIL::Unary not_;
@ -1652,9 +1654,13 @@ public:
}; };
struct FakeParams { struct FakeParams {
RTLIL::Cell* parent; RTLIL::Cell* parent;
RTLIL::Const at(RTLIL::IdString name) { // RTLIL::Const& at(RTLIL::IdString name) {
// return parent->getParam(name);
// }
const RTLIL::Const& at(RTLIL::IdString name) const {
return parent->getParam(name); return parent->getParam(name);
} }
void sort() {}
// Watch out! This is different semantics than what dict has! // Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly // but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker // since its layout is fixed as defined by InternalOldCellChecker
@ -1685,6 +1691,8 @@ public:
bool empty() { bool empty() {
return !size(); return !size();
} }
// The need for this function implies setPort will be used on incompat types
void erase(const RTLIL::IdString& paramname) { (void)paramname; }
// AAA // AAA
class iterator { class iterator {
typedef std::bidirectional_iterator_tag iterator_category; typedef std::bidirectional_iterator_tag iterator_category;
@ -1823,9 +1831,13 @@ public:
}; };
struct FakeConns { struct FakeConns {
RTLIL::Cell* parent; RTLIL::Cell* parent;
RTLIL::SigSpec at(RTLIL::IdString portname) { RTLIL::SigSpec at(RTLIL::IdString name) {
return parent->getPort(portname); return parent->getPort(name);
} }
const RTLIL::SigSpec at(RTLIL::IdString name) const {
return parent->getPort(name);
}
void sort() {}
// Watch out! This is different semantics than what dict has! // Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly // but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker // since its layout is fixed as defined by InternalOldCellChecker
@ -1999,20 +2011,28 @@ public:
// TODO src loc? internal attrs? // TODO src loc? internal attrs?
// Canonical tag // Canonical tag
bool is_legacy() { bool is_legacy() const {
return has_attrs || is_legacy_type(type); return has_attrs || is_legacy_type(type);
}; };
// The weird bits
bool has_memid() { return is_legacy() && legacy->has_memid(); } bool has_memid() { return is_legacy() && legacy->has_memid(); }
bool is_mem_cell() { return is_legacy() && legacy->is_mem_cell(); } bool is_mem_cell() { return is_legacy() && legacy->is_mem_cell(); }
// TODO stub // TODO stub
void set_src_attribute(const std::string &src) { (void)src; }; void set_src_attribute(const std::string &src) { (void)src; };
bool known () {
return is_legacy() ? legacy->known() : true;
}
void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal); void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);
const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname); const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
bool hasPort(const RTLIL::IdString &portname) {
return connections_.count(portname);
}
// The need for this function implies setPort will be used on incompat types
void unsetPort(const RTLIL::IdString& portname) { (void)portname; }
void setParam(const RTLIL::IdString &paramname, RTLIL::Const value); void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
const RTLIL::Const getParam(const RTLIL::IdString &paramname); const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const;
const RTLIL::Const& getParam(const RTLIL::IdString &paramname);
bool hasParam(const RTLIL::IdString &paramname) { bool hasParam(const RTLIL::IdString &paramname) {
return parameters.count(paramname); return parameters.count(paramname);
} }