From 36289ab2082f47ffb2410dcf2601c47ef26caffc Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 13 Jun 2024 12:35:31 +0200 Subject: [PATCH] consty stuff --- kernel/ffmerge.cc | 2 +- kernel/mem.cc | 2 +- kernel/rtlil.cc | 53 ++++++++++++++++++++++++++++++++++++----------- kernel/rtlil.h | 38 +++++++++++++++++++++++++-------- 4 files changed, 72 insertions(+), 23 deletions(-) diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index c65108413..cecc6a835 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -345,7 +345,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_) for (int i = 0; i < GetSize(q); i++) dff_driver[q[i]] = std::make_pair(cell, i); } - for (auto &conn : cell->connections()) + for (auto &&conn : cell->connections_) if (!cell->known() || cell->input(conn.first)) for (auto bit : (*sigmap)(conn.second)) sigbit_users_count[bit]++; diff --git a/kernel/mem.cc b/kernel/mem.cc index 01c866770..bd7910f0a 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -703,7 +703,7 @@ namespace { res.packed = true; res.cell = cell; res.attributes = cell->attributes; - Const &init = cell->parameters.at(ID::INIT); + const Const &init = cell->parameters.at(ID::INIT); if (!init.is_fully_undef()) { int pos = 0; while (pos < res.size) { diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index afc586931..01358a0c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2154,8 +2154,7 @@ void RTLIL::Module::add(RTLIL::Cell *cell) log_assert(count_id(cell->name) == 0); log_assert(refcount_cells_ == 0); cells_[cell->name] = cell; - // TODO - // cell->module = this; + cell->module = this; } void RTLIL::Module::add(RTLIL::Process *process) @@ -3475,7 +3474,7 @@ RTLIL::Process::Process() : module(nullptr) hashidx_ = hashidx_count; } -RTLIL::Cell::Cell() +RTLIL::Cell::Cell() : module(nullptr) { static unsigned int hashidx_count = 123456789; hashidx_count = mkhash_xorshift(hashidx_count); @@ -3510,7 +3509,7 @@ void RTLIL::Cell::setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal throw std::out_of_range("Cell::setPort()"); } } -const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) { +const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) const { if (is_legacy()) return legacy->getPort(portname); @@ -3547,19 +3546,49 @@ void RTLIL::Cell::setParam(const RTLIL::IdString ¶mname, RTLIL::Const value) } } -// TODO autogen -const RTLIL::Const RTLIL::Cell::getParam(const RTLIL::IdString ¶mname) { +// // TODO autogen +// const RTLIL::Const RTLIL::Cell::getParam(const RTLIL::IdString ¶mname) const { +// if (is_legacy()) +// return legacy->getParam(paramname); + +// if (type == ID($not)) { +// if (paramname == ID::A_WIDTH) { +// return RTLIL::Const(not_.a_width); +// } else if (paramname == ID::Y_WIDTH) { +// return RTLIL::Const(not_.y_width); +// } else { +// throw std::out_of_range("Cell::getParam()"); +// } +// } else { +// throw std::out_of_range("Cell::getParam()"); +// } +// } + +const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString ¶mname) { if (is_legacy()) return legacy->getParam(paramname); if (type == ID($not)) { if (paramname == ID::A_WIDTH) { - // Notice using the trivial default constructor - // This is to reduce code changes later when we replace Const - // with int/bool where possible in internal cell type variants - return RTLIL::Const(not_.a_width); + return not_.a_width; } else if (paramname == ID::Y_WIDTH) { - return RTLIL::Const(not_.y_width); + return not_.y_width; + } else { + throw std::out_of_range("Cell::getParam()"); + } + } else { + throw std::out_of_range("Cell::getParam()"); + } +} +const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString ¶mname) const { + if (is_legacy()) + return legacy->getParam(paramname); + + if (type == ID($not)) { + if (paramname == ID::A_WIDTH) { + return not_.a_width; + } else if (paramname == ID::Y_WIDTH) { + return not_.y_width; } else { throw std::out_of_range("Cell::getParam()"); } @@ -3750,7 +3779,7 @@ void RTLIL::Cell::check() checker.check(); #endif } -int bigboy() {return sizeof(RTLIL::Cell);} + void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") || diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e14563055..5a85bcfa7 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1629,7 +1629,8 @@ struct RTLIL::Unary { }; // NewCell -struct RTLIL::Cell +// TODO attributes +struct RTLIL::Cell : RTLIL::AttrObject { // TODO huh? unsigned int hashidx_; @@ -1642,7 +1643,8 @@ struct RTLIL::Cell public: RTLIL::IdString type; - RTLIL::IdString name; // delete? + RTLIL::IdString name; // TODO delete? + RTLIL::Module* module; // TODO delete bool has_attrs; union { RTLIL::Unary not_; @@ -1652,9 +1654,13 @@ public: }; struct FakeParams { RTLIL::Cell* parent; - RTLIL::Const at(RTLIL::IdString name) { + // RTLIL::Const& at(RTLIL::IdString name) { + // return parent->getParam(name); + // } + const RTLIL::Const& at(RTLIL::IdString name) const { return parent->getParam(name); } + void sort() {} // Watch out! This is different semantics than what dict has! // but we rely on RTLIL::Cell always being constructed correctly // since its layout is fixed as defined by InternalOldCellChecker @@ -1685,6 +1691,8 @@ public: bool empty() { return !size(); } + // The need for this function implies setPort will be used on incompat types + void erase(const RTLIL::IdString& paramname) { (void)paramname; } // AAA class iterator { typedef std::bidirectional_iterator_tag iterator_category; @@ -1823,9 +1831,13 @@ public: }; struct FakeConns { RTLIL::Cell* parent; - RTLIL::SigSpec at(RTLIL::IdString portname) { - return parent->getPort(portname); + RTLIL::SigSpec at(RTLIL::IdString name) { + return parent->getPort(name); } + const RTLIL::SigSpec at(RTLIL::IdString name) const { + return parent->getPort(name); + } + void sort() {} // Watch out! This is different semantics than what dict has! // but we rely on RTLIL::Cell always being constructed correctly // since its layout is fixed as defined by InternalOldCellChecker @@ -1999,20 +2011,28 @@ public: // TODO src loc? internal attrs? // Canonical tag - bool is_legacy() { + bool is_legacy() const { return has_attrs || is_legacy_type(type); }; - // The weird bits bool has_memid() { return is_legacy() && legacy->has_memid(); } bool is_mem_cell() { return is_legacy() && legacy->is_mem_cell(); } // TODO stub void set_src_attribute(const std::string &src) { (void)src; }; + bool known () { + return is_legacy() ? legacy->known() : true; + } void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal); - const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname); + const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const; + bool hasPort(const RTLIL::IdString &portname) { + return connections_.count(portname); + } + // The need for this function implies setPort will be used on incompat types + void unsetPort(const RTLIL::IdString& portname) { (void)portname; } void setParam(const RTLIL::IdString ¶mname, RTLIL::Const value); - const RTLIL::Const getParam(const RTLIL::IdString ¶mname); + const RTLIL::Const& getParam(const RTLIL::IdString ¶mname) const; + const RTLIL::Const& getParam(const RTLIL::IdString ¶mname); bool hasParam(const RTLIL::IdString ¶mname) { return parameters.count(paramname); }