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https://github.com/YosysHQ/yosys
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Update kernel to avoid bits()
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parent
67e4a0a48a
commit
360a625785
14 changed files with 151 additions and 122 deletions
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@ -33,10 +33,7 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
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if (arg.size() > 0 && is_signed)
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padding = arg.back();
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while (GetSize(arg) < width)
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arg.bits().push_back(padding);
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arg.bits().resize(width);
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arg.resize(width, padding);
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}
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static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
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@ -79,12 +76,12 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
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{
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mag--;
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for (auto i = 0; i < result_len; i++)
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result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
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result.set(i, mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1);
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}
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else
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{
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for (auto i = 0; i < result_len; i++)
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result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
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result.set(i, mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0);
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}
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}
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@ -140,11 +137,11 @@ RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, boo
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (auto i = 0; i < result_len; i++) {
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if (i >= GetSize(arg1_ext))
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result.bits()[i] = RTLIL::State::S0;
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else if (arg1_ext.bits()[i] == RTLIL::State::S0)
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result.bits()[i] = RTLIL::State::S1;
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else if (arg1_ext.bits()[i] == RTLIL::State::S1)
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result.bits()[i] = RTLIL::State::S0;
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result.set(i, RTLIL::State::S0);
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else if (arg1_ext[i] == RTLIL::State::S0)
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result.set(i, RTLIL::State::S1);
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else if (arg1_ext[i] == RTLIL::State::S1)
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result.set(i, RTLIL::State::S0);
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}
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return result;
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@ -161,9 +158,9 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (auto i = 0; i < result_len; i++) {
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RTLIL::State a = i < GetSize(arg1) ? arg1.bits()[i] : RTLIL::State::S0;
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RTLIL::State b = i < GetSize(arg2) ? arg2.bits()[i] : RTLIL::State::S0;
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result.bits()[i] = logic_func(a, b);
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RTLIL::State a = i < GetSize(arg1) ? arg1[i] : RTLIL::State::S0;
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RTLIL::State b = i < GetSize(arg2) ? arg2[i] : RTLIL::State::S0;
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result.set(i, logic_func(a, b));
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}
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return result;
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@ -197,8 +194,8 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log
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temp = logic_func(temp, arg1[i]);
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RTLIL::Const result(temp);
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -222,9 +219,9 @@ RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Con
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RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
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if (!buffer.empty()) {
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if (buffer.front() == RTLIL::State::S0)
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buffer.bits().front() = RTLIL::State::S1;
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buffer.set(0, RTLIL::State::S1);
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else if (buffer.front() == RTLIL::State::S1)
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buffer.bits().front() = RTLIL::State::S0;
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buffer.set(0, RTLIL::State::S0);
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}
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return buffer;
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}
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@ -239,9 +236,8 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const
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int undef_bit_pos_a = -1;
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BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
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RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -254,9 +250,8 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const
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RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::Const result(logic_and(bit_a, bit_b));
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -269,9 +264,8 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const
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RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::Const result(logic_or(bit_a, bit_b));
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -295,11 +289,11 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
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for (int i = 0; i < result_len; i++) {
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BigInteger pos = BigInteger(i) + offset;
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if (pos < 0)
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result.bits()[i] = vacant_bits;
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result.set(i, vacant_bits);
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else if (pos >= BigInteger(GetSize(arg1)))
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result.bits()[i] = sign_ext ? arg1.back() : vacant_bits;
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result.set(i, sign_ext ? arg1.back() : vacant_bits);
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else
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result.bits()[i] = arg1[pos.toInt()];
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result.set(i, arg1[pos.toInt()]);
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}
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return result;
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@ -346,9 +340,8 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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int undef_bit_pos = -1;
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bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -357,9 +350,8 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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int undef_bit_pos = -1;
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bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -383,7 +375,7 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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matched_status = RTLIL::State::Sx;
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}
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result.bits().front() = matched_status;
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result.set(0, matched_status);
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return result;
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}
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@ -391,9 +383,9 @@ RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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{
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RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len);
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if (result.front() == RTLIL::State::S0)
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result.bits().front() = RTLIL::State::S1;
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result.set(0, RTLIL::State::S1);
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else if (result.front() == RTLIL::State::S1)
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result.bits().front() = RTLIL::State::S0;
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result.set(0, RTLIL::State::S0);
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return result;
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}
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@ -412,7 +404,7 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
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return result;
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}
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result.bits().front() = RTLIL::State::S1;
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result.set(0, RTLIL::State::S1);
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return result;
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}
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@ -420,9 +412,9 @@ RTLIL::Const RTLIL::const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2
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{
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RTLIL::Const result = RTLIL::const_eqx(arg1, arg2, signed1, signed2, result_len);
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if (result.front() == RTLIL::State::S0)
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result.bits().front() = RTLIL::State::S1;
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result.set(0, RTLIL::State::S1);
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else if (result.front() == RTLIL::State::S1)
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result.bits().front() = RTLIL::State::S0;
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result.set(0, RTLIL::State::S0);
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return result;
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}
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@ -431,9 +423,8 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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int undef_bit_pos = -1;
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bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -442,9 +433,8 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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int undef_bit_pos = -1;
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bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (GetSize(result) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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if (GetSize(result) < result_len)
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result.resize(result_len, RTLIL::State::S0);
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return result;
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}
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@ -628,7 +618,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2
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RTLIL::Const ret = arg1;
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for (auto i = 0; i < ret.size(); i++)
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if (ret[i] != arg2[i])
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ret.bits()[i] = State::Sx;
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ret.set(i, State::Sx);
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return ret;
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}
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@ -703,7 +693,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar
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log_assert(arg2.size() == arg1.size());
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RTLIL::Const result(RTLIL::State::S0, arg1.size());
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for (auto i = 0; i < arg1.size(); i++)
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result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0;
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result.set(i, arg1[i] == arg2[i] ? State::S1 : State::S0);
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return result;
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}
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@ -715,7 +705,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
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RTLIL::Const result(RTLIL::State::Sx, arg1.size());
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for (auto i = 0; i < arg1.size(); i++) {
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if (arg3[i] != State::Sx || arg1[i] == arg2[i])
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result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i];
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result.set(i, arg3[i] == State::S1 ? arg2[i] : arg1[i]);
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}
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return result;
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