diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h
index 0e12e6dce..e2071436c 100644
--- a/kernel/bitpattern.h
+++ b/kernel/bitpattern.h
@@ -100,7 +100,7 @@ struct BitPatternPool
 	bits_t sig2bits(RTLIL::SigSpec sig)
 	{
 		bits_t bits;
-		bits.bitdata = sig.as_const().bits();
+		bits.bitdata = sig.as_const().to_bits();
 		for (auto &b : bits.bitdata)
 			if (b > RTLIL::State::S1)
 				b = RTLIL::State::Sa;
diff --git a/kernel/calc.cc b/kernel/calc.cc
index f08c97396..9b0885db9 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -33,10 +33,7 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
 	if (arg.size() > 0 && is_signed)
 		padding = arg.back();
 
-	while (GetSize(arg) < width)
-		arg.bits().push_back(padding);
-
-	arg.bits().resize(width);
+	arg.resize(width, padding);
 }
 
 static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
@@ -79,12 +76,12 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
 		{
 			mag--;
 			for (auto i = 0; i < result_len; i++)
-				result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
+				result.set(i, mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1);
 		}
 		else
 		{
 			for (auto i = 0; i < result_len; i++)
-				result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
+				result.set(i, mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0);
 		}
 	}
 
@@ -140,11 +137,11 @@ RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, boo
 	RTLIL::Const result(RTLIL::State::Sx, result_len);
 	for (auto i = 0; i < result_len; i++) {
 		if (i >= GetSize(arg1_ext))
-			result.bits()[i] = RTLIL::State::S0;
-		else if (arg1_ext.bits()[i] == RTLIL::State::S0)
-			result.bits()[i] = RTLIL::State::S1;
-		else if (arg1_ext.bits()[i] == RTLIL::State::S1)
-			result.bits()[i] = RTLIL::State::S0;
+			result.set(i, RTLIL::State::S0);
+		else if (arg1_ext[i] == RTLIL::State::S0)
+			result.set(i, RTLIL::State::S1);
+		else if (arg1_ext[i] == RTLIL::State::S1)
+			result.set(i, RTLIL::State::S0);
 	}
 
 	return result;
@@ -161,9 +158,9 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
 
 	RTLIL::Const result(RTLIL::State::Sx, result_len);
 	for (auto i = 0; i < result_len; i++) {
-		RTLIL::State a = i < GetSize(arg1) ? arg1.bits()[i] : RTLIL::State::S0;
-		RTLIL::State b = i < GetSize(arg2) ? arg2.bits()[i] : RTLIL::State::S0;
-		result.bits()[i] = logic_func(a, b);
+		RTLIL::State a = i < GetSize(arg1) ? arg1[i] : RTLIL::State::S0;
+		RTLIL::State b = i < GetSize(arg2) ? arg2[i] : RTLIL::State::S0;
+		result.set(i, logic_func(a, b));
 	}
 
 	return result;
@@ -197,8 +194,8 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log
 		temp = logic_func(temp, arg1[i]);
 
 	RTLIL::Const result(temp);
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -222,9 +219,9 @@ RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Con
 	RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
 	if (!buffer.empty()) {
 		if (buffer.front() == RTLIL::State::S0)
-			buffer.bits().front() = RTLIL::State::S1;
+			buffer.set(0, RTLIL::State::S1);
 		else if (buffer.front() == RTLIL::State::S1)
-			buffer.bits().front() = RTLIL::State::S0;
+			buffer.set(0, RTLIL::State::S0);
 	}
 	return buffer;
 }
@@ -239,9 +236,8 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const
 	int undef_bit_pos_a = -1;
 	BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
 	RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -254,9 +250,8 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const
 	RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 	RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 	RTLIL::Const result(logic_and(bit_a, bit_b));
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -269,9 +264,8 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const
 	RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 	RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 	RTLIL::Const result(logic_or(bit_a, bit_b));
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -295,11 +289,11 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
 	for (int i = 0; i < result_len; i++) {
 		BigInteger pos = BigInteger(i) + offset;
 		if (pos < 0)
-			result.bits()[i] = vacant_bits;
+			result.set(i, vacant_bits);
 		else if (pos >= BigInteger(GetSize(arg1)))
-			result.bits()[i] = sign_ext ? arg1.back() : vacant_bits;
+			result.set(i, sign_ext ? arg1.back() : vacant_bits);
 		else
-			result.bits()[i] = arg1[pos.toInt()];
+			result.set(i, arg1[pos.toInt()]);
 	}
 
 	return result;
@@ -346,9 +340,8 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
 	int undef_bit_pos = -1;
 	bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
 	RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -357,9 +350,8 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
 	int undef_bit_pos = -1;
 	bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
 	RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -383,7 +375,7 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
 			matched_status = RTLIL::State::Sx;
 	}
 
-	result.bits().front() = matched_status;
+	result.set(0, matched_status);
 	return result;
 }
 
@@ -391,9 +383,9 @@ RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
 {
 	RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len);
 	if (result.front() == RTLIL::State::S0)
-		result.bits().front() = RTLIL::State::S1;
+		result.set(0, RTLIL::State::S1);
 	else if (result.front() == RTLIL::State::S1)
-		result.bits().front() = RTLIL::State::S0;
+		result.set(0, RTLIL::State::S0);
 	return result;
 }
 
@@ -412,7 +404,7 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
 			return result;
 	}
 
-	result.bits().front() = RTLIL::State::S1;
+	result.set(0, RTLIL::State::S1);
 	return result;
 }
 
@@ -420,9 +412,9 @@ RTLIL::Const RTLIL::const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2
 {
 	RTLIL::Const result = RTLIL::const_eqx(arg1, arg2, signed1, signed2, result_len);
 	if (result.front() == RTLIL::State::S0)
-		result.bits().front() = RTLIL::State::S1;
+		result.set(0, RTLIL::State::S1);
 	else if (result.front() == RTLIL::State::S1)
-		result.bits().front() = RTLIL::State::S0;
+		result.set(0, RTLIL::State::S0);
 	return result;
 }
 
@@ -431,9 +423,8 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
 	int undef_bit_pos = -1;
 	bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
 	RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -442,9 +433,8 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
 	int undef_bit_pos = -1;
 	bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
 	RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
-
-	while (GetSize(result) < result_len)
-		result.bits().push_back(RTLIL::State::S0);
+	if (GetSize(result) < result_len)
+		result.resize(result_len, RTLIL::State::S0);
 	return result;
 }
 
@@ -628,7 +618,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2
 	RTLIL::Const ret = arg1;
 	for (auto i = 0; i < ret.size(); i++)
 		if (ret[i] != arg2[i])
-			ret.bits()[i] = State::Sx;
+			ret.set(i, State::Sx);
 	return ret;
 }
 
@@ -703,7 +693,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar
 	log_assert(arg2.size() == arg1.size());
 	RTLIL::Const result(RTLIL::State::S0, arg1.size());
 	for (auto i = 0; i < arg1.size(); i++)
-		result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0;
+		result.set(i, arg1[i] == arg2[i] ? State::S1 : State::S0);
 
 	return result;
 }
@@ -715,7 +705,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
 	RTLIL::Const result(RTLIL::State::Sx, arg1.size());
 	for (auto i = 0; i < arg1.size(); i++) {
 		if (arg3[i] != State::Sx || arg1[i] == arg2[i])
-			result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i];
+			result.set(i, arg3[i] == State::S1 ? arg2[i] : arg1[i]);
 	}
 
 	return result;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 11640c25f..27d815f4f 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -328,7 +328,7 @@ struct CellTypes
 
 	static RTLIL::Const eval_not(RTLIL::Const v)
 	{
-		for (auto &bit : v.bits())
+		for (auto bit : v)
 			if (bit == State::S0) bit = State::S1;
 			else if (bit == State::S1) bit = State::S0;
 		return v;
@@ -421,16 +421,14 @@ struct CellTypes
 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
 	{
 		if (cell->type == ID($slice)) {
-			RTLIL::Const ret;
 			int width = cell->parameters.at(ID::Y_WIDTH).as_int();
 			int offset = cell->parameters.at(ID::OFFSET).as_int();
-			ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);
-			return ret;
+			return arg1.extract(offset, width);
 		}
 
 		if (cell->type == ID($concat)) {
 			RTLIL::Const ret = arg1;
-			ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());
+			ret.append(arg2);
 			return ret;
 		}
 
diff --git a/kernel/consteval.h b/kernel/consteval.h
index adcf86f8a..b13c7ea5c 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -115,7 +115,7 @@ struct ConstEval
 
 				for (int i = 0; i < GetSize(coval); i++) {
 					carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
-					coval.bits()[i] = carry ? State::S1 : State::S0;
+					coval.set(i, carry ? State::S1 : State::S0);
 				}
 
 				set(sig_co, coval);
@@ -249,7 +249,7 @@ struct ConstEval
 
 			for (int i = 0; i < GetSize(val_y); i++)
 				if (val_y[i] == RTLIL::Sx)
-					val_x.bits()[i] = RTLIL::Sx;
+					val_x.set(i, RTLIL::Sx);
 
 			set(sig_y, val_y);
 			set(sig_x, val_x);
diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc
index b8905d68c..64a89a0db 100644
--- a/kernel/drivertools.cc
+++ b/kernel/drivertools.cc
@@ -260,7 +260,7 @@ bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit)
 		switch (single.type())
 		{
 			case DriveType::CONSTANT: {
-				single.constant().bits().push_back(constant);
+				single.constant().append(RTLIL::Const(constant));
 			} break;
 			case DriveType::WIRE: {
 				single.wire().width += 1;
@@ -295,8 +295,7 @@ bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk)
 		switch (single.type())
 		{
 			case DriveType::CONSTANT: {
-				auto &bits = single.constant().bits();
-				bits.insert(bits.end(), constant.bits().begin(), constant.bits().end());
+				single.constant().append(constant);
 			} break;
 			case DriveType::WIRE: {
 				single.wire().width += width;
@@ -349,7 +348,7 @@ bool DriveChunk::try_append(DriveBit const &bit)
 			none_ += 1;
 			return true;
 		case DriveType::CONSTANT:
-			constant_.bits().push_back(bit.constant());
+			constant_.append(RTLIL::Const(bit.constant()));
 			return true;
 		case DriveType::WIRE:
 			return wire_.try_append(bit.wire());
@@ -375,7 +374,7 @@ bool DriveChunk::try_append(DriveChunk const &chunk)
 			none_ += chunk.none_;
 			return true;
 		case DriveType::CONSTANT:
-			constant_.bits().insert(constant_.bits().end(), chunk.constant_.begin(), chunk.constant_.end());
+			constant_.append(chunk.constant_);
 			return true;
 		case DriveType::WIRE:
 			return wire_.try_append(chunk.wire());
diff --git a/kernel/ff.cc b/kernel/ff.cc
index 8b38b84cb..a72e6a65c 100644
--- a/kernel/ff.cc
+++ b/kernel/ff.cc
@@ -287,6 +287,16 @@ FfData FfData::slice(const std::vector<int> &bits) {
 	res.pol_clr = pol_clr;
 	res.pol_set = pol_set;
 	res.attributes = attributes;
+	std::optional<Const::Builder> arst_bits;
+	if (has_arst)
+		arst_bits.emplace(bits.size());
+	std::optional<Const::Builder> srst_bits;
+	if (has_srst)
+		srst_bits.emplace(bits.size());
+	std::optional<Const::Builder> init_bits;
+	if (initvals)
+		init_bits.emplace(bits.size());
+
 	for (int i : bits) {
 		res.sig_q.append(sig_q[i]);
 		if (has_clk || has_gclk)
@@ -298,12 +308,19 @@ FfData FfData::slice(const std::vector<int> &bits) {
 			res.sig_set.append(sig_set[i]);
 		}
 		if (has_arst)
-			res.val_arst.bits().push_back(val_arst[i]);
+			arst_bits->push_back(val_arst[i]);
 		if (has_srst)
-			res.val_srst.bits().push_back(val_srst[i]);
+			srst_bits->push_back(val_srst[i]);
 		if (initvals)
-			res.val_init.bits().push_back(val_init[i]);
+			init_bits->push_back(val_init[i]);
 	}
+
+	if (has_arst)
+		res.val_arst = arst_bits->build();
+	if (has_srst)
+		res.val_srst = srst_bits->build();
+	if (initvals)
+		res.val_init = init_bits->build();
 	res.width = GetSize(res.sig_q);
 	return res;
 }
@@ -688,10 +705,10 @@ void FfData::flip_rst_bits(const pool<int> &bits) {
 
 	for (auto bit: bits) {
 		if (has_arst)
-			val_arst.bits()[bit] = invert(val_arst[bit]);
+			val_arst.set(bit, invert(val_arst[bit]));
 		if (has_srst)
-			val_srst.bits()[bit] = invert(val_srst[bit]);
-		val_init.bits()[bit] = invert(val_init[bit]);
+			val_srst.set(bit, invert(val_srst[bit]));
+		val_init.set(bit, invert(val_init[bit]));
 	}
 }
 
@@ -760,7 +777,7 @@ void FfData::flip_bits(const pool<int> &bits) {
 
 		Const mask = Const(State::S0, width);
 		for (auto bit: bits)
-			mask.bits()[bit] = State::S1;
+			mask.set(bit, State::S1);
 
 		if (has_clk || has_gclk)
 			sig_d = module->Xor(NEW_ID, sig_d, mask);
diff --git a/kernel/ffinit.h b/kernel/ffinit.h
index 66c13b68f..920fba307 100644
--- a/kernel/ffinit.h
+++ b/kernel/ffinit.h
@@ -74,10 +74,10 @@ struct FfInitVals
 
 	RTLIL::Const operator()(const RTLIL::SigSpec &sig) const
 	{
-		RTLIL::Const res;
+		RTLIL::Const::Builder res_bits(GetSize(sig));
 		for (auto bit : sig)
-			res.bits().push_back((*this)(bit));
-		return res;
+			res_bits.push_back((*this)(bit));
+		return res_bits.build();
 	}
 
 	void set_init(RTLIL::SigBit bit, RTLIL::State val)
@@ -93,12 +93,12 @@ struct FfInitVals
 		initbits[mbit] = std::make_pair(val,abit);
 		auto it2 = abit.wire->attributes.find(ID::init);
 		if (it2 != abit.wire->attributes.end()) {
-			it2->second.bits()[abit.offset] = val;
+			it2->second.set(abit.offset, val);
 			if (it2->second.is_fully_undef())
 				abit.wire->attributes.erase(it2);
 		} else if (val != State::Sx) {
 			Const cval(State::Sx, GetSize(abit.wire));
-			cval.bits()[abit.offset] = val;
+			cval.set(abit.offset, val);
 			abit.wire->attributes[ID::init] = cval;
 		}
 	}
diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc
index 3b361c1c2..632cba05c 100644
--- a/kernel/ffmerge.cc
+++ b/kernel/ffmerge.cc
@@ -42,9 +42,9 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
 			ff.sig_d.append(bit);
 			ff.sig_clr.append(State::Sx);
 			ff.sig_set.append(State::Sx);
-			ff.val_init.bits().push_back(State::Sx);
-			ff.val_srst.bits().push_back(State::Sx);
-			ff.val_arst.bits().push_back(State::Sx);
+			ff.val_init.append(RTLIL::Const(State::Sx));
+			ff.val_srst.append(RTLIL::Const(State::Sx));
+			ff.val_arst.append(RTLIL::Const(State::Sx));
 			continue;
 		}
 
@@ -147,9 +147,9 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
 		ff.sig_q.append(cur_ff.sig_q[idx]);
 		ff.sig_clr.append(ff.has_sr ? cur_ff.sig_clr[idx] : State::S0);
 		ff.sig_set.append(ff.has_sr ? cur_ff.sig_set[idx] : State::S0);
-		ff.val_arst.bits().push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
-		ff.val_srst.bits().push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
-		ff.val_init.bits().push_back(cur_ff.val_init[idx]);
+		ff.val_arst.append(RTLIL::Const(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx));
+		ff.val_srst.append(RTLIL::Const(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx));
+		ff.val_init.append(RTLIL::Const(cur_ff.val_init[idx]));
 		found = true;
 	}
 
@@ -174,9 +174,9 @@ bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair
 			// These two will be fixed up later.
 			ff.sig_clr.append(State::Sx);
 			ff.sig_set.append(State::Sx);
-			ff.val_init.bits().push_back(bit.data);
-			ff.val_srst.bits().push_back(bit.data);
-			ff.val_arst.bits().push_back(bit.data);
+			ff.val_init.append(RTLIL::Const(bit.data));
+			ff.val_srst.append(RTLIL::Const(bit.data));
+			ff.val_arst.append(RTLIL::Const(bit.data));
 			continue;
 		}
 
@@ -274,9 +274,9 @@ bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair
 		ff.sig_q.append(cur_ff.sig_q[idx]);
 		ff.sig_clr.append(ff.has_sr ? cur_ff.sig_clr[idx] : State::S0);
 		ff.sig_set.append(ff.has_sr ? cur_ff.sig_set[idx] : State::S0);
-		ff.val_arst.bits().push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
-		ff.val_srst.bits().push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
-		ff.val_init.bits().push_back(cur_ff.val_init[idx]);
+		ff.val_arst.append(RTLIL::Const(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx));
+		ff.val_srst.append(RTLIL::Const(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx));
+		ff.val_init.append(RTLIL::Const(cur_ff.val_init[idx]));
 		found = true;
 	}
 
diff --git a/kernel/macc.h b/kernel/macc.h
index ceda1dceb..b4c58d20b 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -262,7 +262,7 @@ struct Macc
 
 	bool eval(RTLIL::Const &result) const
 	{
-		for (auto &bit : result.bits())
+		for (auto bit : result)
 			bit = State::S0;
 
 		for (auto &port : terms)
diff --git a/kernel/mem.cc b/kernel/mem.cc
index 67501acfd..a18ceb138 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -131,9 +131,6 @@ void Mem::emit() {
 		cell->parameters[ID::WIDTH] = Const(width);
 		cell->parameters[ID::OFFSET] = Const(start_offset);
 		cell->parameters[ID::SIZE] = Const(size);
-		Const rd_wide_continuation, rd_clk_enable, rd_clk_polarity, rd_transparency_mask, rd_collision_x_mask;
-		Const wr_wide_continuation, wr_clk_enable, wr_clk_polarity, wr_priority_mask;
-		Const rd_ce_over_srst, rd_arst_value, rd_srst_value, rd_init_value;
 		SigSpec rd_clk, rd_en, rd_addr, rd_data;
 		SigSpec wr_clk, wr_en, wr_addr, wr_data;
 		SigSpec rd_arst, rd_srst;
@@ -147,6 +144,15 @@ void Mem::emit() {
 		for (int i = 0; i < GetSize(wr_ports); i++)
 			for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++)
 				wr_port_xlat.push_back(i);
+		Const::Builder rd_wide_continuation_builder;
+		Const::Builder rd_clk_enable_builder;
+		Const::Builder rd_clk_polarity_builder;
+		Const::Builder rd_transparency_mask_builder;
+		Const::Builder rd_collision_x_mask_builder;
+		Const::Builder rd_ce_over_srst_builder;
+		Const::Builder rd_arst_value_builder;
+		Const::Builder rd_srst_value_builder;
+		Const::Builder rd_init_value_builder;
 		for (auto &port : rd_ports) {
 			for (auto attr: port.attributes)
 				if (!cell->has_attribute(attr.first))
@@ -157,10 +163,10 @@ void Mem::emit() {
 			}
 			for (int sub = 0; sub < (1 << port.wide_log2); sub++)
 			{
-				rd_wide_continuation.bits().push_back(State(sub != 0));
-				rd_clk_enable.bits().push_back(State(port.clk_enable));
-				rd_clk_polarity.bits().push_back(State(port.clk_polarity));
-				rd_ce_over_srst.bits().push_back(State(port.ce_over_srst));
+				rd_wide_continuation_builder.push_back(State(sub != 0));
+				rd_clk_enable_builder.push_back(State(port.clk_enable));
+				rd_clk_polarity_builder.push_back(State(port.clk_polarity));
+				rd_ce_over_srst_builder.push_back(State(port.ce_over_srst));
 				rd_clk.append(port.clk);
 				rd_arst.append(port.arst);
 				rd_srst.append(port.srst);
@@ -170,18 +176,27 @@ void Mem::emit() {
 				rd_addr.append(addr);
 				log_assert(GetSize(addr) == abits);
 				for (auto idx : wr_port_xlat) {
-					rd_transparency_mask.bits().push_back(State(bool(port.transparency_mask[idx])));
-					rd_collision_x_mask.bits().push_back(State(bool(port.collision_x_mask[idx])));
+					rd_transparency_mask_builder.push_back(State(bool(port.transparency_mask[idx])));
+					rd_collision_x_mask_builder.push_back(State(bool(port.collision_x_mask[idx])));
 				}
 			}
 			rd_data.append(port.data);
 			for (auto bit : port.arst_value)
-				rd_arst_value.bits().push_back(bit);
+				rd_arst_value_builder.push_back(bit);
 			for (auto bit : port.srst_value)
-				rd_srst_value.bits().push_back(bit);
+				rd_srst_value_builder.push_back(bit);
 			for (auto bit : port.init_value)
-				rd_init_value.bits().push_back(bit);
+				rd_init_value_builder.push_back(bit);
 		}
+		Const rd_wide_continuation = rd_wide_continuation_builder.build();
+		Const rd_clk_enable = rd_clk_enable_builder.build();
+		Const rd_clk_polarity = rd_clk_polarity_builder.build();
+		Const rd_transparency_mask = rd_transparency_mask_builder.build();
+		Const rd_collision_x_mask = rd_collision_x_mask_builder.build();
+		Const rd_ce_over_srst = rd_ce_over_srst_builder.build();
+		Const rd_arst_value = rd_arst_value_builder.build();
+		Const rd_srst_value = rd_srst_value_builder.build();
+		Const rd_init_value = rd_init_value_builder.build();
 		if (rd_ports.empty()) {
 			rd_wide_continuation = State::S0;
 			rd_clk_enable = State::S0;
@@ -212,6 +227,10 @@ void Mem::emit() {
 		cell->setPort(ID::RD_SRST, rd_srst);
 		cell->setPort(ID::RD_ADDR, rd_addr);
 		cell->setPort(ID::RD_DATA, rd_data);
+		Const::Builder wr_wide_continuation_builder;
+		Const::Builder wr_clk_enable_builder;
+		Const::Builder wr_clk_polarity_builder;
+		Const::Builder wr_priority_mask_builder;
 		for (auto &port : wr_ports) {
 			for (auto attr: port.attributes)
 				if (!cell->has_attribute(attr.first))
@@ -222,12 +241,12 @@ void Mem::emit() {
 			}
 			for (int sub = 0; sub < (1 << port.wide_log2); sub++)
 			{
-				wr_wide_continuation.bits().push_back(State(sub != 0));
-				wr_clk_enable.bits().push_back(State(port.clk_enable));
-				wr_clk_polarity.bits().push_back(State(port.clk_polarity));
+				wr_wide_continuation_builder.push_back(State(sub != 0));
+				wr_clk_enable_builder.push_back(State(port.clk_enable));
+				wr_clk_polarity_builder.push_back(State(port.clk_polarity));
 				wr_clk.append(port.clk);
 				for (auto idx : wr_port_xlat)
-					wr_priority_mask.bits().push_back(State(bool(port.priority_mask[idx])));
+					wr_priority_mask_builder.push_back(State(bool(port.priority_mask[idx])));
 				SigSpec addr = port.sub_addr(sub);
 				addr.extend_u0(abits, false);
 				wr_addr.append(addr);
@@ -236,6 +255,10 @@ void Mem::emit() {
 			wr_en.append(port.en);
 			wr_data.append(port.data);
 		}
+		Const wr_wide_continuation = wr_wide_continuation_builder.build();
+		Const wr_clk_enable = wr_clk_enable_builder.build();
+		Const wr_clk_polarity = wr_clk_polarity_builder.build();
+		Const wr_priority_mask = wr_priority_mask_builder.build();
 		if (wr_ports.empty()) {
 			wr_wide_continuation = State::S0;
 			wr_clk_enable = State::S0;
@@ -414,7 +437,7 @@ void Mem::coalesce_inits() {
 			if (!init.en.is_fully_ones()) {
 				for (int i = 0; i < GetSize(init.data); i++)
 					if (init.en[i % width] != State::S1)
-						init.data.bits()[i] = State::Sx;
+						init.data.set(i, State::Sx);
 				init.en = Const(State::S1, width);
 			}
 			continue;
@@ -427,7 +450,7 @@ void Mem::coalesce_inits() {
 			log_assert(offset + GetSize(init.data) <= GetSize(cdata));
 			for (int i = 0; i < GetSize(init.data); i++)
 				if (init.en[i % width] == State::S1)
-					cdata.bits()[i+offset] = init.data[i];
+					cdata.set(i+offset, init.data[i]);
 			init.removed = true;
 		}
 		MemInit new_init;
@@ -446,7 +469,7 @@ Const Mem::get_init_data() const {
 		int offset = (init.addr.as_int() - start_offset) * width;
 		for (int i = 0; i < GetSize(init.data); i++)
 			if (0 <= i+offset && i+offset < GetSize(init_data) && init.en[i % width] == State::S1)
-				init_data.bits()[i+offset] = init.data[i];
+				init_data.set(i+offset, init.data[i]);
 	}
 	return init_data;
 }
@@ -1700,7 +1723,7 @@ MemContents::MemContents(Mem *mem) :
 				RTLIL::Const previous = (*this)[addr + i];
 				for(int j = 0; j < _data_width; j++)
 					if(init.en[j] != State::S1)
-						data.bits()[_data_width * i + j] = previous[j];
+						data.set(_data_width * i + j, previous[j]);
 			}
 			insert_concatenated(init.addr.as_int(), data);
 		}
@@ -1846,7 +1869,7 @@ std::map<MemContents::addr_t, RTLIL::Const>::iterator MemContents::_reserve_rang
 		// we have two different ranges touching at either end, we need to merge them
 		auto upper_end = _range_end(upper_it);
 		// make range bigger (maybe reserve here instead of resize?)
-		lower_it->second.bits().resize(_range_offset(lower_it, upper_end), State::Sx);
+		lower_it->second.resize(_range_offset(lower_it, upper_end), State::Sx);
 		// copy only the data beyond our range
 		std::copy(_range_data(upper_it, end_addr), _range_data(upper_it, upper_end), _range_data(lower_it, end_addr));
 		// keep lower_it, but delete upper_it
@@ -1854,16 +1877,16 @@ std::map<MemContents::addr_t, RTLIL::Const>::iterator MemContents::_reserve_rang
 		return lower_it;
 	} else if (lower_touch) {
 		// we have a range to the left, just make it bigger and delete any other that may exist.
-		lower_it->second.bits().resize(_range_offset(lower_it, end_addr), State::Sx);
+		lower_it->second.resize(_range_offset(lower_it, end_addr), State::Sx);
 		// keep lower_it and upper_it
 		_values.erase(std::next(lower_it), upper_it);
 		return lower_it;
 	} else if (upper_touch) {
 		// we have a range to the right, we need to expand it
 		// since we need to erase and reinsert to a new address, steal the data
-		RTLIL::Const data = std::move(upper_it->second);
 		// note that begin_addr is not in upper_it, otherwise the whole range covered check would have tripped
-		data.bits().insert(data.bits().begin(), (_range_begin(upper_it) - begin_addr) * _data_width, State::Sx);
+		RTLIL::Const data(State::Sx, (_range_begin(upper_it) - begin_addr) * _data_width);
+		data.append(std::move(upper_it->second));
 		// delete lower_it and upper_it, then reinsert
 		_values.erase(lower_it, std::next(upper_it));
 		return _values.emplace(begin_addr, std::move(data)).first;
@@ -1886,7 +1909,7 @@ void MemContents::insert_concatenated(addr_t addr, RTLIL::Const const &values) {
 	std::fill(to_begin + values.size(), to_begin + words * _data_width, State::S0);
 }
 
-std::vector<State>::iterator MemContents::_range_write(std::vector<State>::iterator it, RTLIL::Const const &word) {
+RTLIL::Const::iterator MemContents::_range_write(RTLIL::Const::iterator it, RTLIL::Const const &word) {
 	auto from_end = word.size() <= _data_width ? word.end() : word.begin() + _data_width;
 	auto to_end = std::copy(word.begin(), from_end, it);
 	auto it_next = std::next(it, _data_width);
diff --git a/kernel/mem.h b/kernel/mem.h
index a06f44bd8..b35ea52c7 100644
--- a/kernel/mem.h
+++ b/kernel/mem.h
@@ -255,11 +255,13 @@ private:
 	// return the offset the addr would have in the range at `it`
 	size_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }
 	// assuming _range_contains(it, addr), return an iterator pointing to the data at addr
-	std::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits().begin() + _range_offset(it, addr); }
+	RTLIL::Const::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) {
+		return RTLIL::Const::iterator(it->second, _range_offset(it, addr));
+	}
 	// internal version of reserve_range that returns an iterator to the range
 	std::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);
 	// write a single word at addr, return iterator to next word
-	std::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);
+	RTLIL::Const::iterator _range_write(RTLIL::Const::iterator it, RTLIL::Const const &data);
 public:
 	class range {
 		int _data_width;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index fc007c3bf..f3cc7ada8 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -450,7 +450,7 @@ int RTLIL::Const::get_min_size(bool is_signed) const
 void RTLIL::Const::compress(bool is_signed)
 {
 	auto idx = get_min_size(is_signed);
-	bits().erase(bits().begin() + idx, bits().end());
+	resize(idx, RTLIL::State::S0);
 }
 
 std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc
index e970779d7..a158102bc 100644
--- a/kernel/tclapi.cc
+++ b/kernel/tclapi.cc
@@ -214,18 +214,19 @@ bool mp_int_to_const(mp_int *a, Const &b, bool is_signed)
 	buf.resize(mp_unsigned_bin_size(a));
 	mp_to_unsigned_bin(a, buf.data());
 
-	b.bits().reserve(mp_count_bits(a) + is_signed);
+	Const::Builder b_bits(mp_count_bits(a) + is_signed);
 	for (int i = 0; i < mp_count_bits(a);) {
 		for (int j = 0; j < 8 && i < mp_count_bits(a); j++, i++) {
 			bool bv = ((buf.back() & (1 << j)) != 0) ^ negative;
-			b.bits().push_back(bv ? RTLIL::S1 : RTLIL::S0);
+			b_bits.push_back(bv ? RTLIL::S1 : RTLIL::S0);
 		}
 		buf.pop_back();
 	}
 
 	if (is_signed) {
-		b.bits().push_back(negative ? RTLIL::S1 : RTLIL::S0);
+		b_bits.push_back(negative ? RTLIL::S1 : RTLIL::S0);
 	}
+	b = b_bits.build();
 
 	return true;
 }
diff --git a/kernel/yw.cc b/kernel/yw.cc
index f36212c7f..2ea4cc66e 100644
--- a/kernel/yw.cc
+++ b/kernel/yw.cc
@@ -185,7 +185,6 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const
 	const std::string &bits = steps[t].bits;
 
 	RTLIL::Const result(State::Sa, width);
-	result.bits().reserve(width);
 
 	int read_begin = GetSize(bits) - 1 - bits_offset;
 	int read_end = max(-1, read_begin - width);
@@ -200,7 +199,7 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const
 			default:
 				log_abort();
 		}
-		result.bits()[j] = bit;
+		result.set(j, bit);
 	}
 
 	return result;