mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Merge remote-tracking branch 'origin/master' into xaig_dff

Browse source
This commit is contained in:
Eddie Hung 2019-07-02 12:35:45 -07:00
commit 35fd9b0473
7 changed files with 87 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/verilog/verilog_lexer.l
View file

@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
global state.. its a mess) */
[a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
if (!strcmp(yytext, "default"))
return TOK_DEFAULT;
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_SVA_LABEL;
}