From 2c6aaef3db87fe7955eded675fac452705e5cd48 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 13:32:09 -0700 Subject: [PATCH 01/12] Add test --- tests/various/script.ys | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 tests/various/script.ys diff --git a/tests/various/script.ys b/tests/various/script.ys new file mode 100644 index 000000000..6044ad9b3 --- /dev/null +++ b/tests/various/script.ys @@ -0,0 +1,17 @@ +read_verilog -formal < Date: Fri, 28 Jun 2019 13:36:33 -0700 Subject: [PATCH 02/12] Support ability for "script -select" to take commands from wires --- kernel/yosys.cc | 47 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 94d6d675f..7d4948881 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1254,24 +1254,55 @@ struct HistoryPass : public Pass { #endif struct ScriptCmdPass : public Pass { - ScriptCmdPass() : Pass("script", "execute commands from script file") { } + ScriptCmdPass() : Pass("script", "execute commands from file or wire") { } void help() YS_OVERRIDE { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); + log(" script -select [selection]\n"); log("\n"); - log("This command executes the yosys commands in the specified file.\n"); + log("This command executes the yosys commands in the specified file (default\n"); + log("behaviour), or commands embedded in the constant text value connected to the\n"); + log("selected wires.\n"); log("\n"); - log("The 2nd argument can be used to only execute the section of the\n"); - log("file between the specified labels. An empty from label is synonymous\n"); - log("for the beginning of the file and an empty to label is synonymous\n"); - log("for the end of the file.\n"); + log("In the default (file) case, the 2nd argument can be used to only execute the\n"); + log("section of the file between the specified labels. An empty from label is\n"); + log("synonymous with the beginning of the file and an empty to label is synonymous\n"); + log("with the end of the file.\n"); log("\n"); log("If only one label is specified (without ':') then only the block\n"); log("marked with that label (until the next label) is executed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - if (args.size() < 2) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + bool select_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-select") { + select_mode = true; + continue; + } + break; + } + if (select_mode) { + extra_args(args, argidx, design); + + for (auto mod : design->selected_modules()) + for (auto &c : mod->connections()) { + if (!c.first.is_wire()) + continue; + auto w = c.first.as_wire(); + if (!mod->selected(w)) + continue; + if (!c.second.is_fully_const()) + log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); + auto v = c.second.as_const(); + Pass::call(design, v.decode_string()); + } + } + else if (args.size() < 2) log_cmd_error("Missing script file.\n"); else if (args.size() == 2) run_frontend(args[1], "script", design); From 4e1a4927e29d1b571b88d9be80a0ff2e0716d5fb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 13:39:06 -0700 Subject: [PATCH 03/12] Add to CHANGELOG --- CHANGELOG | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 15dd5d002..af9642d66 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,12 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "script -select" + Yosys 0.8 .. Yosys 0.8-dev -------------------------- From 64f6b0c747eb915be9205b36bd69745a2385aea1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 13:41:32 -0700 Subject: [PATCH 04/12] Try command in another module --- tests/various/script.ys | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/various/script.ys b/tests/various/script.ys index 6044ad9b3..9ccc727eb 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -6,6 +6,9 @@ read_verilog -formal < Date: Mon, 1 Jul 2019 09:46:56 -0700 Subject: [PATCH 05/12] Move CHANGELOG entry from yosys-0.8 to 0.9 --- CHANGELOG | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index b54897d89..818225e56 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,13 +2,6 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.9 .. Yosys 0.9-dev --------------------------- - - * Various - - Added "script -select" - - Yosys 0.9 .. Yosys 0.9-dev -------------------------- @@ -18,6 +11,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) + - Added "script -select" Yosys 0.8 .. Yosys 0.8-dev From 6282a67332e9ca0ffe68b7ae57e93b6248946d4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 11:59:10 -0700 Subject: [PATCH 06/12] Space --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 818225e56..4348b3d7a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,7 @@ List of major changes and improvements between releases ======================================================= + Yosys 0.9 .. Yosys 0.9-dev -------------------------- From d206eca03b8aa7bb982fb2486c02c90a61354066 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Jul 2019 11:36:26 +0200 Subject: [PATCH 07/12] Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d3fd91473..951d9c66f 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some global state.. its a mess) */ [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] { + if (!strcmp(yytext, "default")) + return TOK_DEFAULT; frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); return TOK_SVA_LABEL; } From d45936fe5f2c6fd1e6f371b2fc3d6d820868ef72 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 2 Jul 2019 13:27:37 +0100 Subject: [PATCH 08/12] memory_dff: Fix checking of feedback mux input when more than one mux Signed-off-by: David Shah --- passes/memory/memory_dff.cc | 8 +++++--- tests/memories/read_two_mux.v | 16 ++++++++++++++++ tests/memories/run-test.sh | 4 ++++ 3 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 tests/memories/read_two_mux.v diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 5215cce44..32b97f27a 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -17,6 +17,7 @@ * */ +#include #include "kernel/yosys.h" #include "kernel/sigtools.h" @@ -183,12 +184,12 @@ struct MemoryDffWorker if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)) { RTLIL::SigSpec en; - RTLIL::SigSpec check_q; + std::vector check_q; do { bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); + check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); sig_data = sigmap(mux->getPort("\\Y")); en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); @@ -197,7 +198,8 @@ struct MemoryDffWorker if (sigbit_users_count[bit] > 1) goto skip_ff_after_read_merging; - if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q) + if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && + std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; })) { disconnect_dff(sig_data); cell->setPort("\\CLK", clk_data); diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v new file mode 100644 index 000000000..4f2e7e1cd --- /dev/null +++ b/tests/memories/read_two_mux.v @@ -0,0 +1,16 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-no-rd-clk + +module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata); + +reg [7:0] bram[0:255]; +(* keep *) reg dummy; + +always @(posedge clk) begin + rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata; + if (we) + bram[addr] <= wdata; +end + +endmodule diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index 76acaa9cd..8d1a8b413 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected read clock."; false; } fi + if grep -q expect-no-rd-clk $f; then + grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp || + { echo " ERROR: Expected no read clock."; false; } + fi echo " ok." done From 02ba85b13302f0d20f6b51cc7fdff2fb953421df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:17:26 -0700 Subject: [PATCH 09/12] script -select -> script -scriptwire --- CHANGELOG | 2 +- kernel/yosys.cc | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 4348b3d7a..ae7d28236 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -12,7 +12,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) - - Added "script -select" + - Added "script -scriptwire Yosys 0.8 .. Yosys 0.8-dev diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d4948881..456ad48a0 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); - log(" script -select [selection]\n"); + log(" script -scriptwire [selection]\n"); log("\n"); log("This command executes the yosys commands in the specified file (default\n"); log("behaviour), or commands embedded in the constant text value connected to the\n"); @@ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - bool select_mode = false; + bool scriptwire = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-select") { - select_mode = true; + if (args[argidx] == "-scriptwire") { + scriptwire = true; continue; } break; } - if (select_mode) { + if (scriptwire) { extra_args(args, argidx, design); for (auto mod : design->selected_modules()) From 90382a0f6d1ad7dfd14ced95051e5e76de89491c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:19:23 -0700 Subject: [PATCH 10/12] Update test too --- tests/various/script.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/various/script.ys b/tests/various/script.ys index 9ccc727eb..4152145e8 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -13,8 +13,8 @@ read_verilog -formal < Date: Tue, 2 Jul 2019 08:20:37 -0700 Subject: [PATCH 11/12] Use Pass::call_on_module() as per @cliffordwolf comments --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 456ad48a0..f95c0127b 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass { if (!c.second.is_fully_const()) log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); auto v = c.second.as_const(); - Pass::call(design, v.decode_string()); + Pass::call_on_module(design, mod, v.decode_string()); } } else if (args.size() < 2) From 81a717e9b767792f64535757f905a5061c627fbd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:22:31 -0700 Subject: [PATCH 12/12] Update test for Pass::call_on_module() --- tests/various/script.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/script.ys b/tests/various/script.ys index 4152145e8..66b7b5caa 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -9,7 +9,7 @@ read_verilog -formal <