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tests: test opt_expr for 32 bit unsigned shifts

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George Rennie 2025-05-26 15:28:44 +01:00
parent 33a22b5cd1
commit 353fd0f7f4
1 changed files with 47 additions and 0 deletions
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47
tests/opt/opt_expr_shift.ys
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@ -111,3 +111,50 @@ select -assert-none t:$shr
select -assert-none t:$sshl select -assert-none t:$sshl
select -assert-none t:$sshr select -assert-none t:$sshr
select -assert-none t:$shiftx select -assert-none t:$shiftx
design -reset
read_verilog <<EOT
module top (
input wire [3:0] in,
output wire [7:0] shl,
output wire [7:0] shr,
output wire [7:0] sshl,
output wire [7:0] sshr,
output wire [7:0] shiftx,
output wire [7:0] shl_s,
output wire [7:0] shr_s,
output wire [7:0] sshl_s,
output wire [7:0] sshr_s,
output wire [7:0] shiftx_s,
);
assign shl = in << 32'hffffffff;
assign shr = in >> 32'hffffffff;
assign sshl = in <<< 32'hffffffff;
assign sshr = in >>> 32'hffffffff;
assign shiftx = in[32'hffffffff +: 8];
wire signed [31:0] shamt = 32'hffffffff;
assign shl_s = in << shamt;
assign shr_s = in >> shamt;
assign sshl_s = in <<< shamt;
assign sshr_s = in >>> shamt;
assign shiftx_s = in[shamt +: 8];
endmodule
EOT
select -assert-count 2 t:$shl
select -assert-count 2 t:$shr
select -assert-count 2 t:$sshl
select -assert-count 2 t:$sshr
select -assert-count 1 t:$shiftx
equiv_opt opt_expr
design -load postopt
select -assert-none t:$shl
select -assert-none t:$shr
select -assert-none t:$sshl
select -assert-none t:$sshr
select -assert-none t:$shiftx