diff --git a/tests/opt/opt_expr_shift.ys b/tests/opt/opt_expr_shift.ys index 943d370dc..5a27562f6 100644 --- a/tests/opt/opt_expr_shift.ys +++ b/tests/opt/opt_expr_shift.ys @@ -111,3 +111,50 @@ select -assert-none t:$shr select -assert-none t:$sshl select -assert-none t:$sshr select -assert-none t:$shiftx + +design -reset + +read_verilog <> 32'hffffffff; + assign sshl = in <<< 32'hffffffff; + assign sshr = in >>> 32'hffffffff; + assign shiftx = in[32'hffffffff +: 8]; + + wire signed [31:0] shamt = 32'hffffffff; + assign shl_s = in << shamt; + assign shr_s = in >> shamt; + assign sshl_s = in <<< shamt; + assign sshr_s = in >>> shamt; + assign shiftx_s = in[shamt +: 8]; +endmodule +EOT + +select -assert-count 2 t:$shl +select -assert-count 2 t:$shr +select -assert-count 2 t:$sshl +select -assert-count 2 t:$sshr +select -assert-count 1 t:$shiftx + +equiv_opt opt_expr + +design -load postopt +select -assert-none t:$shl +select -assert-none t:$shr +select -assert-none t:$sshl +select -assert-none t:$sshr +select -assert-none t:$shiftx