mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

changes related to some pull request remarks

Browse source
This commit is contained in:
Artur Swiderski 2020-12-09 14:35:01 +01:00
parent dd9c11c035
commit 349fc479cb
3 changed files with 3 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/intel_alm/common/alm_sim.v
View file

@ -169,7 +169,7 @@ module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`ifdef cyclonev
`ifdef cyclonev
specify
(A => Q) = 510;
(B => Q) = 400;

2
techlibs/intel_le/common/quartus_rename.v
View file

@ -58,7 +58,7 @@ assign Q = ~A;
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO);
module MISTRAL_LE_LUT_ARITH(input A, B, C, D, CI, output SO, CO);
parameter LUT = 16'h0000;
`LCELL #(.lut_mask({LUT}),.sum_lutc_input("cin")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO));

19
techlibs/intel_le/cycloneiv/cells_sim.v
View file

@ -1,21 +1,4 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC