From 349fc479cb275de1f02de9e42ce8bd1114c18752 Mon Sep 17 00:00:00 2001 From: Artur Swiderski Date: Wed, 9 Dec 2020 14:35:01 +0100 Subject: [PATCH] changes related to some pull request remarks --- techlibs/intel_alm/common/alm_sim.v | 2 +- techlibs/intel_le/common/quartus_rename.v | 2 +- techlibs/intel_le/cycloneiv/cells_sim.v | 19 +------------------ 3 files changed, 3 insertions(+), 20 deletions(-) diff --git a/techlibs/intel_alm/common/alm_sim.v b/techlibs/intel_alm/common/alm_sim.v index 9689876c3..906a95b0b 100644 --- a/techlibs/intel_alm/common/alm_sim.v +++ b/techlibs/intel_alm/common/alm_sim.v @@ -169,7 +169,7 @@ module MISTRAL_ALUT3(input A, B, C, output Q); parameter [7:0] LUT = 8'h00; -`ifdef cyclonev +`ifdef cyclonev specify (A => Q) = 510; (B => Q) = 400; diff --git a/techlibs/intel_le/common/quartus_rename.v b/techlibs/intel_le/common/quartus_rename.v index da76a347b..7ad5c6283 100644 --- a/techlibs/intel_le/common/quartus_rename.v +++ b/techlibs/intel_le/common/quartus_rename.v @@ -58,7 +58,7 @@ assign Q = ~A; endmodule -module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO); +module MISTRAL_LE_LUT_ARITH(input A, B, C, D, CI, output SO, CO); parameter LUT = 16'h0000; `LCELL #(.lut_mask({LUT}),.sum_lutc_input("cin")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO)); diff --git a/techlibs/intel_le/cycloneiv/cells_sim.v b/techlibs/intel_le/cycloneiv/cells_sim.v index 48b2651b0..7be70eef5 100644 --- a/techlibs/intel_le/cycloneiv/cells_sim.v +++ b/techlibs/intel_le/cycloneiv/cells_sim.v @@ -1,21 +1,4 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ + module VCC (output V); assign V = 1'b1; endmodule // VCC