mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-21 13:23:40 +00:00
Code Activity

rtlil: rename InternalOldCellChecker back to InternalCellChecker

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-07-10 15:18:49 +02:00
parent 66c629374c
commit 343bc667ba
2 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

8
kernel/rtlil.cc
View file

@ -1018,13 +1018,13 @@ size_t RTLIL::Module::count_id(const RTLIL::IdString& id)
#ifndef NDEBUG #ifndef NDEBUG
namespace { namespace {
struct InternalOldCellChecker struct InternalCellChecker
{ {
RTLIL::Module *module; RTLIL::Module *module;
RTLIL::Cell *cell; RTLIL::Cell *cell;
pool<RTLIL::IdString> expected_params, expected_ports; pool<RTLIL::IdString> expected_params, expected_ports;
InternalOldCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { } InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
void error(int linenr) void error(int linenr)
{ {
@ -1983,7 +1983,7 @@ void RTLIL::Module::check()
// log_assert(!it2.first.empty()); // log_assert(!it2.first.empty());
for (auto it2 : it.second->parameters) for (auto it2 : it.second->parameters)
log_assert(!it2.first.empty()); log_assert(!it2.first.empty());
InternalOldCellChecker checker(this, it.second); InternalCellChecker checker(this, it.second);
checker.check(); checker.check();
if (it.second->has_memid()) { if (it.second->has_memid()) {
log_assert(memories.count(it.second->parameters.at(ID::MEMID).decode_string())); log_assert(memories.count(it.second->parameters.at(ID::MEMID).decode_string()));
@ -3915,7 +3915,7 @@ void RTLIL::OldCell::sort()
void RTLIL::Cell::check() void RTLIL::Cell::check()
{ {
#ifndef NDEBUG #ifndef NDEBUG
InternalOldCellChecker checker(NULL, this); InternalCellChecker checker(NULL, this);
checker.check(); checker.check();
#endif #endif
} }

4
kernel/rtlil.h
View file

@ -1708,7 +1708,7 @@ public:
void reserve(int n) { (void)n; } void reserve(int n) { (void)n; }
// Watch out! This is different semantics than what dict has! // Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly // but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker // since its layout is fixed as defined by InternalCellChecker
RTLIL::Const& operator[](RTLIL::IdString name) { RTLIL::Const& operator[](RTLIL::IdString name) {
// log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str()); // log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str());
return parent->getMutParam(name); return parent->getMutParam(name);
@ -1975,7 +1975,7 @@ public:
void reserve(int n) { (void)n; } void reserve(int n) { (void)n; }
// Watch out! This is different semantics than what dict has! // Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly // but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker // since its layout is fixed as defined by InternalCellChecker
RTLIL::SigSpec& operator[](RTLIL::IdString portname) { RTLIL::SigSpec& operator[](RTLIL::IdString portname) {
// log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str()); // log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str());
return parent->getMutPort(portname); return parent->getMutPort(portname);