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fix proc, reduce warnings

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This commit is contained in:
Emil J. Tywoniak 2024-06-21 11:56:36 +02:00
parent 1be8f8023a
commit 66c629374c
3 changed files with 3 additions and 3 deletions
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2
passes/cmds/glift.cc
View file

@ -343,7 +343,7 @@ private:
//recurse to GLIFT model the child module. However, we need to augment the ports list
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
auto orig_ports = cell->connections();
auto orig_ports = cell->connections().as_dict();
log("Adding cell %s\n", cell_module_def->name.c_str());
for (auto &&it : orig_ports) {
RTLIL::SigSpec port = it.second;

2
passes/proc/proc_mux.cc
View file

@ -252,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
return RTLIL::SigSpec(result_wire);
}
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());

2
passes/tests/test_cell.cc
View file

@ -344,7 +344,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
if (constmode)
{
auto conn_list = cell->connections();
auto conn_list = cell->connections().as_dict();
for (auto conn : conn_list)
{
RTLIL::SigSpec sig = conn.second;