From 338d4adef2529938cbd77f5b8f2b78786ca5ff53 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 19 Jun 2026 10:18:27 +1200 Subject: [PATCH] write_verilog: Fix upto indexing for single bit --- backends/verilog/verilog_backend.cc | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index fd9986144..68e2ee20e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -197,14 +197,22 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) reg_name = id(chunk.wire->name); if (sig.size() != chunk.wire->width) { - if (sig.size() == 1) - reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset); - else if (chunk.wire->upto) - reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset, - (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); + int idx; + if (chunk.wire->upto) + idx = (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset; else - reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1, - chunk.wire->start_offset + chunk.offset); + idx = chunk.wire->start_offset + chunk.offset; + + if (sig.size() == 1) + reg_name += stringf("[%d]", idx); + else { + int left_idx; + if (chunk.wire->upto) + left_idx = (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset; + else + left_idx = chunk.wire->start_offset + chunk.offset + chunk.width - 1; + reg_name += stringf("[%d:%d]", left_idx, idx); + } } return true;