tests: Run async2sync before sat and/or sim to handle $check cells

Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.

tests/various/chformal_coverenable.ys

@@ -13,6 +13,8 @@ EOT
 
 prep -top top
 
+async2sync
+
 select -assert-count 1 t:$cover
 
 chformal -cover -coverenable

tests/various/chparam.sh

@@ -37,14 +37,17 @@ EOT
 
 if ../../yosys -q -p 'verific -sv chparam1.sv'; then
 	../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+			-p 'async2sync' \
 			-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
 			-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
 
 	../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+			-p 'async2sync' \
 			-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
 			-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
 fi
 ../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
+		-p 'async2sync' \
 		-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
 		-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
 

tests/various/const_arg_loop.ys

@@ -3,4 +3,5 @@ hierarchy
 proc
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/various/const_func.ys

@@ -4,4 +4,5 @@ proc
 flatten
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/various/countbits.ys

@@ -4,4 +4,5 @@ proc
 flatten
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/various/param_struct.ys

@@ -47,4 +47,5 @@ end
 endmodule
 EOF
 hierarchy; proc; opt
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/various/struct_access.ys

@@ -2,4 +2,5 @@ read_verilog -sv struct_access.sv
 hierarchy
 proc
 opt
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all