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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
28 lines
467 B
Plaintext
28 lines
467 B
Plaintext
read_verilog -formal <<EOT
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module top(input a, b, c, d);
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always @* begin
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if (a) assert (b == c);
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if (!a) assert (b != c);
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if (b) assume (c);
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if (c) cover (d);
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end
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endmodule
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EOT
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prep -top top
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async2sync
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select -assert-count 1 t:$cover
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chformal -cover -coverenable
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select -assert-count 2 t:$cover
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chformal -assert -coverenable
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select -assert-count 4 t:$cover
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chformal -assume -coverenable
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select -assert-count 5 t:$cover
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