Converting PRESENTATION_ExSyn

docs/resources/PRESENTATION_ExSyn/.gitignore

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+*.dot
+*.pdf

docs/resources/PRESENTATION_ExSyn/Makefile

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+
+TARGETS += proc_01 proc_02 proc_03
+TARGETS += opt_01 opt_02 opt_03 opt_04
+TARGETS += memory_01 memory_02
+TARGETS += techmap_01
+TARGETS += abc_01
+
+all: $(addsuffix .pdf,$(TARGETS))
+
+define make_pdf_template
+$(1).pdf: $(1)*.v $(1)*.ys
+	../../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
+endef
+
+$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
+
+clean:
+	rm -f $(addsuffix .pdf,$(TARGETS))
+	rm -f $(addsuffix .dot,$(TARGETS))
+

docs/resources/PRESENTATION_ExSyn/abc_01.v

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+module test(input clk, a, b, c,
+            output reg y);
+
+	reg [2:0] q1, q2;
+	always @(posedge clk) begin
+		q1 <= { a, b, c };
+		q2 <= q1;
+		y <= ^q2;
+	end
+endmodule

docs/resources/PRESENTATION_ExSyn/abc_01.ys

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+read_verilog abc_01.v
+read_verilog -lib abc_01_cells.v
+hierarchy -check -top test
+proc; opt; techmap
+abc -dff -liberty abc_01_cells.lib;;

docs/resources/PRESENTATION_ExSyn/abc_01_cells.lib

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+// test comment
+/* test comment */
+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+  cell(DFFSR) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D;
+                      preset: S;
+                       clear: R; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+    pin(S) { direction: input; }
+    pin(R) { direction: input; }
+  }
+}

docs/resources/PRESENTATION_ExSyn/abc_01_cells.v

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+
+module BUF(A, Y);
+input A;
+output Y = A;
+endmodule
+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+	Q <= D;
+endmodule
+
+module DFFSR(C, D, Q, S, R);
+input C, D, S, R;
+output reg Q;
+always @(posedge C, posedge S, posedge R)
+	if (S)
+		Q <= 1'b1;
+	else if (R)
+		Q <= 1'b0;
+	else
+		Q <= D;
+endmodule
+

docs/resources/PRESENTATION_ExSyn/memory_01.v

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+module test(input      CLK, ADDR,
+            input      [7:0] DIN,
+	    output reg [7:0] DOUT);
+    reg [7:0] mem [0:1];
+    always @(posedge CLK) begin
+        mem[ADDR] <= DIN;
+	DOUT <= mem[ADDR];
+    end
+endmodule

docs/resources/PRESENTATION_ExSyn/memory_01.ys

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+read_verilog memory_01.v
+hierarchy -check -top test
+proc;; memory; opt

docs/resources/PRESENTATION_ExSyn/memory_02.v

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+module test(
+    input             WR1_CLK,  WR2_CLK,
+    input             WR1_WEN,  WR2_WEN,
+    input      [7:0]  WR1_ADDR, WR2_ADDR,
+    input      [7:0]  WR1_DATA, WR2_DATA,
+    input             RD1_CLK,  RD2_CLK,
+    input      [7:0]  RD1_ADDR, RD2_ADDR,
+    output reg [7:0]  RD1_DATA, RD2_DATA
+);
+
+reg [7:0] memory [0:255];
+
+always @(posedge WR1_CLK)
+    if (WR1_WEN)
+        memory[WR1_ADDR] <= WR1_DATA;
+
+always @(posedge WR2_CLK)
+    if (WR2_WEN)
+        memory[WR2_ADDR] <= WR2_DATA;
+
+always @(posedge RD1_CLK)
+    RD1_DATA <= memory[RD1_ADDR];
+
+always @(posedge RD2_CLK)
+    RD2_DATA <= memory[RD2_ADDR];
+
+endmodule

docs/resources/PRESENTATION_ExSyn/memory_02.ys

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+read_verilog memory_02.v
+hierarchy -check -top test
+proc;; memory -nomap
+opt -mux_undef -mux_bool

docs/resources/PRESENTATION_ExSyn/opt_01.v

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+module test(input A, B, output Y);
+assign Y = A ? A ? B : 1'b1 : B;
+endmodule

docs/resources/PRESENTATION_ExSyn/opt_01.ys

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+read_verilog opt_01.v
+hierarchy -check -top test
+opt

docs/resources/PRESENTATION_ExSyn/opt_02.v

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+module test(input A, output Y, Z);
+assign Y = A == A, Z = A != A;
+endmodule

docs/resources/PRESENTATION_ExSyn/opt_02.ys

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+read_verilog opt_02.v
+hierarchy -check -top test
+opt

docs/resources/PRESENTATION_ExSyn/opt_03.v

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+module test(input  [3:0] A, B,
+            output [3:0] Y, Z);
+assign Y = A + B, Z = B + A;
+endmodule

docs/resources/PRESENTATION_ExSyn/opt_03.ys

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+read_verilog opt_03.v
+hierarchy -check -top test
+opt

docs/resources/PRESENTATION_ExSyn/opt_04.v

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+module test(input CLK, ARST,
+            output [7:0] Q1, Q2, Q3);
+
+wire NO_CLK = 0;
+
+always @(posedge CLK, posedge ARST)
+	if (ARST)
+		Q1 <= 42;
+
+always @(posedge NO_CLK, posedge ARST)
+	if (ARST)
+		Q2 <= 42;
+	else
+		Q2 <= 23;
+
+always @(posedge CLK)
+	Q3 <= 42;
+
+endmodule

docs/resources/PRESENTATION_ExSyn/opt_04.ys

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+read_verilog opt_04.v
+hierarchy -check -top test
+proc; opt

docs/resources/PRESENTATION_ExSyn/proc_01.v

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+module test(input D, C, R, output reg Q);
+    always @(posedge C, posedge R)
+        if (R)
+	    Q <= 0;
+	else
+	    Q <= D;
+endmodule

docs/resources/PRESENTATION_ExSyn/proc_01.ys

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+read_verilog proc_01.v
+hierarchy -check -top test
+proc;;

docs/resources/PRESENTATION_ExSyn/proc_02.v

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+module test(input D, C, R, RV,
+            output reg Q);
+    always @(posedge C, posedge R)
+        if (R)
+	    Q <= RV;
+	else
+	    Q <= D;
+endmodule

docs/resources/PRESENTATION_ExSyn/proc_02.ys

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+read_verilog proc_02.v
+hierarchy -check -top test
+proc;;

docs/resources/PRESENTATION_ExSyn/proc_03.v

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+module test(input A, B, C, D, E,
+            output reg Y);
+    always @* begin
+	Y <= A;
+	if (B)
+	    Y <= C;
+	if (D)
+	    Y <= E;
+    end
+endmodule

docs/resources/PRESENTATION_ExSyn/proc_03.ys

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+read_verilog proc_03.v
+hierarchy -check -top test
+proc;;

docs/resources/PRESENTATION_ExSyn/techmap_01.v

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+module test(input [31:0]  a, b,
+            output [31:0] y);
+assign y = a + b;
+endmodule

docs/resources/PRESENTATION_ExSyn/techmap_01.ys

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+read_verilog techmap_01.v
+hierarchy -check -top test
+techmap -map techmap_01_map.v;;

docs/resources/PRESENTATION_ExSyn/techmap_01_map.v

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+module \$add (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+generate
+  if ((A_WIDTH == 32) && (B_WIDTH == 32))
+    begin
+      wire [16:0] S1 = A[15:0] + B[15:0];
+      wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
+      assign Y = {S2[15:0], S1[15:0]};
+    end
+  else
+    wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule