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https://github.com/YosysHQ/yosys
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Update passes/proc to avoid bits()
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parent
bab72e0af7
commit
32b53f177c
3 changed files with 12 additions and 14 deletions
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@ -97,7 +97,7 @@ struct RomWorker
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log_debug("rejecting switch: lhs not uniform\n");
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return;
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}
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val.bits()[it2->second] = it.second[i].data;
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val.set(it2->second, it.second[i].data);
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}
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}
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for (auto bit: val) {
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@ -114,7 +114,7 @@ struct RomWorker
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}
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Const c = addr.as_const();
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while (GetSize(c) && c.back() == State::S0)
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c.bits().pop_back();
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c.resize(c.size() - 1, State::S0);
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if (GetSize(c) > swsigbits)
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continue;
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if (GetSize(c) > 30) {
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@ -155,22 +155,22 @@ struct RomWorker
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Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
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mem.attributes = sw->attributes;
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Const init_data;
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Const::Builder builder(mem.size * GetSize(lhs));
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for (int i = 0; i < mem.size; i++) {
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auto it = vals.find(i);
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if (it == vals.end()) {
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log_assert(got_default);
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for (auto bit: default_val)
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init_data.bits().push_back(bit);
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builder.push_back(bit);
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} else {
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for (auto bit: it->second)
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init_data.bits().push_back(bit);
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builder.push_back(bit);
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}
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}
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MemInit init;
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init.addr = 0;
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init.data = init_data;
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init.data = builder.build();
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init.en = Const(State::S1, GetSize(lhs));
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mem.inits.push_back(std::move(init));
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