diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 817ced404..c4080ceb8 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -52,17 +52,15 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
 
 						Const value = valuesig.as_const();
 						Const &wireinit = lhs_c.wire->attributes[ID::init];
-
-						while (GetSize(wireinit) < lhs_c.wire->width)
-							wireinit.bits().push_back(State::Sx);
-
+						if (GetSize(wireinit) < lhs_c.wire->width)
+							wireinit.resize(lhs_c.wire->width, State::Sx);
 						for (int i = 0; i < lhs_c.width; i++) {
-							auto &initbit = wireinit.bits()[i + lhs_c.offset];
+							int index = i + lhs_c.offset;
+							State initbit = wireinit[index];
 							if (initbit != State::Sx && initbit != value[i])
 								log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
-							initbit = value[i];
+							wireinit.set(index, value[i]);
 						}
-
 						log("  Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
 					}
 					offset += lhs_c.width;
diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc
index 88aea39bb..a5ae0d6d5 100644
--- a/passes/proc/proc_memwr.cc
+++ b/passes/proc/proc_memwr.cc
@@ -39,7 +39,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
 			Const priority_mask(State::S0, port_id);
 			for (int i = 0; i < GetSize(prev_port_ids); i++)
 				if (memwr.priority_mask[i] == State::S1)
-					priority_mask.bits()[prev_port_ids[i]] = State::S1;
+					priority_mask.set(prev_port_ids[i], State::S1);
 			prev_port_ids.push_back(port_id);
 
 			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));
diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc
index d3b781e60..a7b485194 100644
--- a/passes/proc/proc_rom.cc
+++ b/passes/proc/proc_rom.cc
@@ -97,7 +97,7 @@ struct RomWorker
 						log_debug("rejecting switch: lhs not uniform\n");
 						return;
 					}
-					val.bits()[it2->second] = it.second[i].data;
+					val.set(it2->second, it.second[i].data);
 				}
 			}
 			for (auto bit: val) {
@@ -114,7 +114,7 @@ struct RomWorker
 				}
 				Const c = addr.as_const();
 				while (GetSize(c) && c.back() == State::S0)
-					c.bits().pop_back();
+					c.resize(c.size() - 1, State::S0);
 				if (GetSize(c) > swsigbits)
 					continue;
 				if (GetSize(c) > 30) {
@@ -155,22 +155,22 @@ struct RomWorker
 		Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
 		mem.attributes = sw->attributes;
 
-		Const init_data;
+		Const::Builder builder(mem.size * GetSize(lhs));
 		for (int i = 0; i < mem.size; i++) {
 			auto it = vals.find(i);
 			if (it == vals.end()) {
 				log_assert(got_default);
 				for (auto bit: default_val)
-					init_data.bits().push_back(bit);
+					builder.push_back(bit);
 			} else {
 				for (auto bit: it->second)
-					init_data.bits().push_back(bit);
+					builder.push_back(bit);
 			}
 		}
 
 		MemInit init;
 		init.addr = 0;
-		init.data = init_data;
+		init.data = builder.build();
 		init.en = Const(State::S1, GetSize(lhs));
 		mem.inits.push_back(std::move(init));