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Update passes/proc to avoid bits()
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parent
bab72e0af7
commit
32b53f177c
3 changed files with 12 additions and 14 deletions
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@ -52,17 +52,15 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
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Const value = valuesig.as_const();
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Const &wireinit = lhs_c.wire->attributes[ID::init];
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while (GetSize(wireinit) < lhs_c.wire->width)
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wireinit.bits().push_back(State::Sx);
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if (GetSize(wireinit) < lhs_c.wire->width)
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wireinit.resize(lhs_c.wire->width, State::Sx);
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for (int i = 0; i < lhs_c.width; i++) {
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auto &initbit = wireinit.bits()[i + lhs_c.offset];
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int index = i + lhs_c.offset;
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State initbit = wireinit[index];
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if (initbit != State::Sx && initbit != value[i])
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log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
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initbit = value[i];
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wireinit.set(index, value[i]);
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}
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log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
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}
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offset += lhs_c.width;
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