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Progress in memory_bram
This commit is contained in:
Clifford Wolf
parent
94e6b70736
commit
327a5d42b6
4 changed files with 127 additions and 15 deletions
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@ -250,14 +250,14 @@ namespace RTLIL
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// of cell types). the following functions helps with that.
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template<typename T, typename... Args>
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bool in(T first, Args... rest) {
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bool in(T first, Args... rest) const {
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return in(first) || in(rest...);
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}
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bool in(IdString rhs) { return *this == rhs; }
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bool in(const char *rhs) { return *this == rhs; }
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bool in(const std::string &rhs) { return *this == rhs; }
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bool in(const pool<IdString> &rhs) { return rhs.count(*this) != 0; }
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bool in(IdString rhs) const { return *this == rhs; }
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bool in(const char *rhs) const { return *this == rhs; }
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bool in(const std::string &rhs) const { return *this == rhs; }
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bool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }
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};
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static inline std::string escape_id(std::string str) {
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@ -137,6 +137,8 @@ YOSYS_NAMESPACE_BEGIN
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using std::vector;
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using std::string;
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using std::pair;
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using hashlib::mkhash;
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using hashlib::mkhash_init;
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using hashlib::mkhash_add;
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@ -221,6 +223,8 @@ YOSYS_NAMESPACE_END
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YOSYS_NAMESPACE_BEGIN
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using RTLIL::State;
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namespace hashlib {
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template<> struct hash_ops<RTLIL::State> : hash_ops<int> {};
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}
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@ -24,10 +24,33 @@ PRIVATE_NAMESPACE_BEGIN
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struct rules_t
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{
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struct portinfo_t {
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int group, index;
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int wrmode, enable, transp, clocks, clkpol;
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};
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struct bram_t {
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IdString name;
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int groups, abits, dbits, init;
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vector<int> wports, rports, wenabl, transp, clocks, clkpol;
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vector<int> ports, wrmode, enable, transp, clocks, clkpol;
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vector<portinfo_t> make_portinfos() const
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{
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vector<portinfo_t> portinfos;
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for (int i = 0; i < groups && i < GetSize(ports); i++)
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for (int j = 0; j < ports[i]; j++) {
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portinfo_t pi;
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pi.group = i;
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pi.index = j;
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pi.wrmode = i < GetSize(wrmode) ? wrmode[i] : 0;
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pi.enable = i < GetSize(enable) ? enable[i] : 0;
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pi.transp = i < GetSize(transp) ? transp[i] : 0;
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pi.clocks = i < GetSize(clocks) ? clocks[i] : 0;
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pi.clkpol = i < GetSize(clkpol) ? clkpol[i] : 0;
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portinfos.push_back(pi);
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}
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return portinfos;
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}
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};
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struct match_t {
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@ -80,7 +103,7 @@ struct rules_t
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if (GetSize(tokens) >= 2 && tokens[0] == stmt) {
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value.resize(GetSize(tokens)-1);
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for (int i = 1; i < GetSize(tokens); i++)
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value[i] = atoi(tokens[i].c_str());
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value[i-1] = atoi(tokens[i].c_str());
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return true;
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}
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return false;
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@ -113,13 +136,13 @@ struct rules_t
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if (parse_single_int("init", data.init))
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continue;
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if (parse_int_vect("wports", data.wports))
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if (parse_int_vect("ports", data.ports))
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continue;
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if (parse_int_vect("rports", data.rports))
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if (parse_int_vect("wrmode", data.wrmode))
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continue;
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if (parse_int_vect("wenabl", data.wenabl))
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if (parse_int_vect("enable", data.enable))
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continue;
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if (parse_int_vect("transp", data.transp))
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@ -187,9 +210,85 @@ struct rules_t
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}
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};
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void replace_cell(Cell*, const rules_t::bram_t&, const rules_t::match_t&)
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bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_t&)
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{
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auto portinfos = bram.make_portinfos();
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dict<int, pair<SigBit, bool>> clock_domains;
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vector<int> mapped_wr_ports;
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log(" Mapping to bram type %s:\n", log_id(bram.name));
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int wr_ports_n = cell->getParam("\\WR_PORTS").as_int();
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auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE"));
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auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY"));
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wr_clken.extend_u0(wr_ports_n);
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wr_clkpol.extend_u0(wr_ports_n);
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SigSpec wr_clk = cell->getPort("\\WR_CLK");
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SigSpec wr_en = cell->getPort("\\WR_EN");
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for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < wr_ports_n; cell_port_i++)
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{
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bool clken = wr_clken[cell_port_i] == State::S1;
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auto clkpol = wr_clkpol[cell_port_i] == State::S1;
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auto clksig = wr_clk[cell_port_i];
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pair<SigBit, bool> clkdom(clksig, clkpol);
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if (!clken)
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clkdom = pair<SigBit, bool>(State::S1, false);
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log(" Write port #%d is in clock domain %s%s.\n",
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cell_port_i, clkdom.second ? "" : "!",
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clken ? log_signal(clkdom.first) : "~async~");
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for (; bram_port_i < GetSize(portinfos); bram_port_i++)
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{
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auto &pi = portinfos[bram_port_i];
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if (pi.wrmode != 1)
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skip_bram_wport:
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continue;
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if (clken) {
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if (pi.clocks == 0) {
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log(" Bram port %c%d has incompatible clock type.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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if (clock_domains.count(pi.clocks) && clock_domains.at(pi.clocks) != clkdom) {
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log(" Bram port %c%d is in a different clock domain.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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} else {
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if (pi.clocks != 0) {
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log(" Bram port %c%d has incompatible clock type.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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}
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SigBit last_en_bit = State::S1;
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for (int i = 0; i < bram.dbits; i++) {
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if (pi.enable && i % (bram.dbits / pi.enable) == 0)
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last_en_bit = wr_en[i];
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if (last_en_bit != wr_en[i]) {
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log(" Bram port %c%d has incompatible enable structure.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_wport;
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}
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}
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log(" Mapped to bram port %c%d.\n", pi.group + 'A', pi.index + 1);
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if (clken)
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clock_domains[pi.clocks] = clkdom;
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mapped_wr_ports.push_back(bram_port_i);
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goto mapped_port;
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}
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log(" Failed to map write port #%d.\n", cell_port_i);
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return false;
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mapped_port:;
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}
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log(" FIXME: The core of memory_bram is not implemented yet.\n");
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return false;
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}
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void handle_cell(Cell *cell, const rules_t &rules)
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@ -210,8 +309,13 @@ void handle_cell(Cell *cell, const rules_t &rules)
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log(" %s=%d", it.first.c_str(), it.second);
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log("\n");
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pool<IdString> failed_brams;
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for (int i = 0; i < GetSize(rules.matches); i++)
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{
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if (rules.matches[i].name.in(failed_brams))
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continue;
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for (auto it : rules.matches[i].min_limits) {
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if (!mem_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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@ -237,7 +341,11 @@ void handle_cell(Cell *cell, const rules_t &rules)
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if (!rules.brams.count(rules.matches[i].name))
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log_error("No bram description for resource %s found!\n", log_id(rules.matches[i].name));
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replace_cell(cell, rules.brams.at(rules.matches[i].name), rules.matches[i]);
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if (!replace_cell(cell, rules.brams.at(rules.matches[i].name), rules.matches[i])) {
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log(" Mapping to bram type %s failed.\n", log_id(rules.matches[i].name));
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failed_brams.insert(rules.matches[i].name);
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goto next_match_rule;
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}
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return;
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next_match_rule:;
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@ -7,9 +7,9 @@ bram XILINX_RAMB36_SDP32
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abits 10
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dbits 32
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groups 2
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wports 1 0
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rports 0 1
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wenabl 2 0
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ports 1 1
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wrmode 1 0
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enable 4 0
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transp 0 2
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clocks 1 2
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endbram
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