From 319b9e2a4f363ae6299ebbf8f8610073c0face9d Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 17 Mar 2026 17:35:57 +0100
Subject: [PATCH] signorm: disable passes that use rewrite_sigspecs

---
 passes/cmds/splitnets.cc    | 3 +++
 passes/equiv/equiv_miter.cc | 3 +++
 passes/sat/freduce.cc       | 2 ++
 passes/techmap/abc9_ops.cc  | 1 +
 passes/techmap/constmap.cc  | 3 +++
 passes/techmap/hilomap.cc   | 3 +++
 6 files changed, 15 insertions(+)

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index d61a99ec0..f943127de 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -145,6 +145,9 @@ struct SplitnetsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		// module_ports_db[module_name][old_port_name] = new_port_name_list
 		dict<IdString, dict<IdString, vector<IdString>>> module_ports_db;
 
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index 6acfe85a9..ead6ea7a4 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -319,6 +319,9 @@ struct EquivMiterPass : public Pass {
 		worker.miter_name = RTLIL::escape_id(args[argidx++]);
 		extra_args(args, argidx, design);
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		if (design->module(worker.miter_name))
 			log_cmd_error("Miter module %s already exists.\n", log_id(worker.miter_name));
 
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 4b0669c25..7abc661c1 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -827,6 +827,8 @@ struct FreducePass : public Pass {
 			break;
 		}
 		extra_args(args, argidx, design);
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
 
 		int bitcount = 0;
 		for (auto module : design->selected_modules()) {
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 0fcd90258..7f0490c59 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1894,6 +1894,7 @@ struct Abc9OpsPass : public Pass {
 		extra_args(args, argidx, design);
 
 		// TODO Disabled signorm because swap_names breaks fanout logic
+		// TODO disable signorm due to rewrite_sigspecs assert
 		design->sigNormalize(false);
 
 		if (!valid)
diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc
index 1df50e47d..225bca81b 100644
--- a/passes/techmap/constmap.cc
+++ b/passes/techmap/constmap.cc
@@ -74,6 +74,9 @@ struct ConstmapPass : public Pass {
 		if (celltype.empty())
 			log_cmd_error("Missing required option -cell.\n");
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		if (design->has(celltype)) {
 			Module *existing = design->module(celltype);
 			bool has_port = false;
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index c1b947221..0cd81ded4 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -105,6 +105,9 @@ struct HilomapPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		// TODO disable signorm due to rewrite_sigspecs assert
+		design->sigNormalize(false);
+
 		for (auto mod : design->selected_modules())
 		{
 			module = mod;