mirror of
https://github.com/YosysHQ/yosys
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48 lines
1.3 KiB
Verilog
48 lines
1.3 KiB
Verilog
/* Generated by Yosys 0.66+154 (git sha1 23aadd92a-dirty, Release, Clang /nix/store/mw4gasdvwgscgpxpzihjgchfhs3hhqhn-clang-wrapper-21.1.8/bin/clang++ 21.1.8) [git@github.com:YosysHQ/yosys at nella/x-wildcard] */
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(* top = 1 *)
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(* src = "<<EOT:1.1-12.10" *)
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module top(y, clk, wire0);
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(* src = "<<EOT:2.15-2.16" *)
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output y;
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wire y;
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(* src = "<<EOT:3.14-3.17" *)
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input clk;
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wire clk;
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(* src = "<<EOT:4.21-4.26" *)
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input signed wire0;
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wire signed wire0;
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(* src = "<<EOT:9.3-11.6" *)
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wire _0_;
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(* src = "<<EOT:6.7-6.15" *)
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wire _1_;
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(* src = "<<EOT:7.7-7.15" *)
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wire _2_;
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(* src = "<<EOT:10.21-10.31" *)
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wire _3_;
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(* src = "<<EOT:10.45-10.50" *)
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wire _4_;
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(* src = "<<EOT:10.55-10.70" *)
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wire _5_;
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(* src = "<<EOT:10.13-10.71" *)
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wire _6_;
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(* src = "<<EOT:5.7-5.11" *)
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reg reg1;
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(* src = "<<EOT:6.7-6.11" *)
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wire var2;
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(* src = "<<EOT:7.7-7.11" *)
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wire var3;
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assign _3_ = $signed(wire0) <= (* src = "<<EOT:10.21-10.31" *) $signed(32'd0);
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(* src = "<<EOT:9.3-11.6" *)
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always @(posedge clk)
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reg1 <= _6_;
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assign _6_ = _3_ ? (* src = "<<EOT:10.13-10.71" *) 1'h0 : 1'h1;
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assign y = reg1;
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assign _2_ = 1'h0;
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assign _1_ = 1'h0;
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assign _0_ = _6_;
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assign var3 = 1'h0;
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assign var2 = 1'h0;
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assign _4_ = var3;
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assign _5_ = 1'h1;
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endmodule
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