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gowin: Fix X output of $alu techmap

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This commit is contained in:
Ralf Fuest 2023-05-01 17:56:41 +02:00
parent cee3cb31b9
commit 30f1d10948
3 changed files with 30 additions and 1 deletions
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tests/arch/gowin/compare.ys Normal file
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read_verilog compare.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 5 t:ALU