mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

anlogic: Use dfflegalize.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2020-07-03 00:22:44 +02:00
parent 3d8d98d709
commit 3050454d6e
4 changed files with 49 additions and 62 deletions
Download patch file Download diff file Expand all files Collapse all files

26
tests/arch/anlogic/latches.ys
View file

@ -3,31 +3,33 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
design -load postopt
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_LUT3 %% t:* %D
select -assert-count 1 t:AL_MAP_SEQ
select -assert-count 1 t:AL_MAP_LUT1
select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT1 %% t:* %D
design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
design -load postopt
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_LUT3 %% t:* %D
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
design -load postopt
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT5
select -assert-none t:AL_MAP_LUT5 %% t:* %D
select -assert-count 1 t:AL_MAP_SEQ
select -assert-count 2 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT3 %% t:* %D