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36 lines
994 B
Plaintext
36 lines
994 B
Plaintext
read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
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design -load postopt
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-count 1 t:AL_MAP_LUT1
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select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT1 %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
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design -load postopt
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_SEQ %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic
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design -load postopt
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-count 2 t:AL_MAP_LUT3
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select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT3 %% t:* %D
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