mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-09 15:47:31 +00:00
Code Activity

rtlil: add source tracking to CaseRule actions

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:25:42 +01:00
parent c45a035ebf
commit 304757c881
6 changed files with 15 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/proc/proc_rom.cc
View file

@ -197,16 +197,16 @@ struct RomWorker
if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->actions.push_back({lhs, rdata});
cs->actions.push_back({lhs, rdata, std::move(action_src)});
sw->cases.push_back(cs);
} else {
sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back({lhs, rdata});
cs->actions.push_back({lhs, rdata, action_src});
sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->actions.push_back({lhs, default_val});
cs2->actions.push_back({lhs, default_val, std::move(action_src)});
sw->cases.push_back(cs2);
}