diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 858714b5b..5c9f17710 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -441,7 +441,7 @@ struct AST_INTERNAL::ProcessGenerator
 				RTLIL::SigSpec lhs = init_lvalue_c;
 				RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
 				remove_unwanted_lvalue_bits(lhs, rhs);
-				sync->actions.push_back({lhs, rhs});
+				sync->actions.push_back({lhs, rhs, Const("")});
 				offset += lhs.size();
 			}
 		}
@@ -573,7 +573,7 @@ struct AST_INTERNAL::ProcessGenerator
 			if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
 				rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
 			remove_unwanted_lvalue_bits(lhs, rhs);
-			actions.push_back({lhs, rhs});
+			actions.push_back({lhs, rhs, ast ? ast->loc_string() : ""});
 			offset += lhs.size();
 		}
 	}
@@ -613,7 +613,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 				removeSignalFromCaseTree(lvalue, current_case);
 				remove_unwanted_lvalue_bits(lvalue, rvalue);
-				current_case->actions.push_back({lvalue, rvalue});
+				current_case->actions.push_back({lvalue, rvalue, ast->loc_string()});
 			}
 			break;
 
@@ -729,8 +729,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
 				set_src_attr(en, ast);
-				proc->root_case.actions.push_back({en, SigSpec(false)});
-				current_case->actions.push_back({en, SigSpec(true)});
+				proc->root_case.actions.push_back({en, SigSpec(false), ast->loc_string()});
+				current_case->actions.push_back({en, SigSpec(true), ast->loc_string()});
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const::Builder polarity_builder;
@@ -827,8 +827,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
 				set_src_attr(en, ast);
-				proc->root_case.actions.push_back({en, SigSpec(false)});
-				current_case->actions.push_back({en, SigSpec(true)});
+				proc->root_case.actions.push_back({en, SigSpec(false), ast->loc_string()});
+				current_case->actions.push_back({en, SigSpec(true), ast->loc_string()});
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const::Builder polarity_builder;
diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc
index d5cf84d9c..991f02017 100644
--- a/frontends/rtlil/rtlil_frontend.cc
+++ b/frontends/rtlil/rtlil_frontend.cc
@@ -624,7 +624,7 @@ struct RTLILFrontendWorker {
 						"The assign statement is reordered to come before all switch statements.");
 				RTLIL::SigSpec s1 = parse_sigspec();
 				RTLIL::SigSpec s2 = parse_sigspec();
-				current_case->actions.push_back({std::move(s1), std::move(s2)});
+				current_case->actions.push_back({std::move(s1), std::move(s2), Const("")});
 				expect_eol();
 			} else
 				return;
@@ -715,7 +715,7 @@ struct RTLILFrontendWorker {
 				if (try_parse_keyword("update")) {
 					RTLIL::SigSpec s1 = parse_sigspec();
 					RTLIL::SigSpec s2 = parse_sigspec();
-					rule->actions.push_back({std::move(s1), std::move(s2)});
+					rule->actions.push_back({std::move(s1), std::move(s2), Const("")});
 					expect_eol();
 					continue;
 				}
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 16e80ce60..46477d6b2 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -2241,6 +2241,7 @@ struct RTLIL::SyncAction
 {
 	RTLIL::SigSpec lhs;
 	RTLIL::SigSpec rhs;
+	RTLIL::Const src;
 };
 
 struct RTLIL::SyncRule
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 56938ff7f..105c894ac 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -311,7 +311,7 @@ struct ProcArstPass : public Pass {
 							if (arst_sig.size()) {
 								log("Added global reset to process %s: %s <- %s\n",
 										proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val));
-								arst_actions.push_back({arst_sig, arst_val});
+								arst_actions.push_back({arst_sig, arst_val, act.src});
 							}
 						}
 				if (!arst_actions.empty()) {
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index d764a20af..a4c7d927c 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -224,7 +224,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			single_async_rule.type = RTLIL::SyncType::ST1;
 			single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
 			// TODO
-			single_async_rule.actions.push_back({sig, rstval});
+			single_async_rule.actions.push_back({sig, rstval, Const("")});
 
 			// Replace existing rules with this new rule
 			async_rules.clear();
diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc
index 07aeacd36..e6b67abd8 100644
--- a/passes/proc/proc_rom.cc
+++ b/passes/proc/proc_rom.cc
@@ -197,16 +197,16 @@ struct RomWorker
 		if (abits == GetSize(sw->signal)) {
 			sw->signal = SigSpec();
 			RTLIL::CaseRule *cs = new RTLIL::CaseRule;
-			cs->actions.push_back({lhs, rdata});
+			cs->actions.push_back({lhs, rdata, std::move(action_src)});
 			sw->cases.push_back(cs);
 		} else {
 			sw->signal = sw->signal.extract_end(abits);
 			RTLIL::CaseRule *cs = new RTLIL::CaseRule;
 			cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
-			cs->actions.push_back({lhs, rdata});
+			cs->actions.push_back({lhs, rdata, action_src});
 			sw->cases.push_back(cs);
 			RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
-			cs2->actions.push_back({lhs, default_val});
+			cs2->actions.push_back({lhs, default_val, std::move(action_src)});
 			sw->cases.push_back(cs2);
 		}