mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-07 06:46:06 +00:00
Code Activity

rtlil: add source tracking to CaseRule actions

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:25:42 +01:00
parent c45a035ebf
commit 304757c881
6 changed files with 15 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/proc/proc_arst.cc
View file

@ -311,7 +311,7 @@ struct ProcArstPass : public Pass {
if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n",
proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back({arst_sig, arst_val});
arst_actions.push_back({arst_sig, arst_val, act.src});
}
}
if (!arst_actions.empty()) {

2
passes/proc/proc_dff.cc
View file

@ -224,7 +224,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
single_async_rule.type = RTLIL::SyncType::ST1;
single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
// TODO
single_async_rule.actions.push_back({sig, rstval});
single_async_rule.actions.push_back({sig, rstval, Const("")});
// Replace existing rules with this new rule
async_rules.clear();

6
passes/proc/proc_rom.cc
View file

@ -197,16 +197,16 @@ struct RomWorker
if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->actions.push_back({lhs, rdata});
cs->actions.push_back({lhs, rdata, std::move(action_src)});
sw->cases.push_back(cs);
} else {
sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back({lhs, rdata});
cs->actions.push_back({lhs, rdata, action_src});
sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->actions.push_back({lhs, default_val});
cs2->actions.push_back({lhs, default_val, std::move(action_src)});
sw->cases.push_back(cs2);
}