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xilinx_srl: keep the clock enable on FDRE shift registers

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run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
This commit is contained in:
drewbabel 2026-07-20 23:59:40 -07:00
parent e2c27aaafa
commit 3006280d70
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2 changed files with 47 additions and 1 deletions
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techlibs/xilinx/xilinx_srl.cc
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@ -77,7 +77,7 @@ void run_fixed(xilinx_srl_pm &pm)
}
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1)))
c->setParam(ID(ENPOL), 1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
c->setParam(ID(ENPOL), 0);