From 3006280d709c901ff108d94b423b4f7549422edc Mon Sep 17 00:00:00 2001
From: drewbabel <122849144+drewbabel@users.noreply.github.com>
Date: Mon, 20 Jul 2026 23:59:40 -0700
Subject: [PATCH] xilinx_srl: keep the clock enable on FDRE shift registers

run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
---
 techlibs/xilinx/xilinx_srl.cc          |  2 +-
 tests/arch/xilinx/xilinx_srl_enable.ys | 46 ++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 tests/arch/xilinx/xilinx_srl_enable.ys

diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc
index e23062eb7..10aa789e5 100644
--- a/techlibs/xilinx/xilinx_srl.cc
+++ b/techlibs/xilinx/xilinx_srl.cc
@@ -77,7 +77,7 @@ void run_fixed(xilinx_srl_pm &pm)
 		}
 		else
 			log_abort();
-		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1)))
 			c->setParam(ID(ENPOL), 1);
 		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
 			c->setParam(ID(ENPOL), 0);
diff --git a/tests/arch/xilinx/xilinx_srl_enable.ys b/tests/arch/xilinx/xilinx_srl_enable.ys
new file mode 100644
index 000000000..c95a849aa
--- /dev/null
+++ b/tests/arch/xilinx/xilinx_srl_enable.ys
@@ -0,0 +1,46 @@
+# Regression test for a xilinx_srl bug where a fixed shift register inferred
+# from FDRE cells dropped the clock enable. FDRE has an active high clock
+# enable but run_fixed assigned it ENPOL 2 (no enable) instead of ENPOL 1,
+# so the resulting shift register shifted every cycle and ignored stalls.
+read_verilog <<EOT
+module xilinx_srl_enable_test(input i, clk, ce, output q);
+reg [3:0] shift = 4'b0000;
+always @(posedge clk)
+    if (ce)
+        shift <= {shift[2:0], i};
+assign q = shift[3];
+endmodule
+
+module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
+parameter CLKPOL = 1;
+parameter ENPOL = 1;
+parameter DEPTH = 2;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+wire ce = (ENPOL == 2) ? 1'b1 : (ENPOL == 1) ? E : ~E;
+always @(posedge C)
+    if (ce)
+        r <= { r[DEPTH-2:0], D };
+assign Q = r[L];
+endmodule
+EOT
+design -copy-to model $__XILINX_SHREG_
+hierarchy -top xilinx_srl_enable_test
+prep
+design -save gold
+
+synth_xilinx -noiopad -noclkbuf -run begin:map_luts
+opt_expr -mux_undef -noclkinv
+techmap -map +/xilinx/ff_map.v
+xilinx_srl -fixed
+opt
+
+select -assert-count 1 t:$__XILINX_SHREG_
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
+prep
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 6 miter