From 2ed89e02daca1d841235e2aa2b267dc8b6f0b549 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Mon, 5 Jan 2026 23:26:02 +0530 Subject: [PATCH] move outside of VERIFIC_SYSTEMVERILOG_SUPPORT --- backends/verilog/verilog_backend.cc | 17 +++++++++++++++++ frontends/verific/verific.cc | 5 +++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 8d77160fd..38a3a11da 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -386,14 +386,31 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) f << "{0{1'b0}}"; return; } + if (sig.is_fully_const() && GetSize(sig) > 8192) { + f << stringf("{ "); + int i = 0; + auto chunks = sig.chunks(); + for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) { + dump_const(f, it->data, 1, 0); + if (it != chunks.rbegin()) + f << stringf(", "); + if (i++ % 20 == 19) + f << stringf("\n"); + } + f << stringf(" }"); + return; + } if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); } else { f << stringf("{ "); + int i = 0; auto chunks = sig.chunks(); for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) { if (it != chunks.rbegin()) f << stringf(", "); + if (i++ % 20 == 19) + f << stringf("\n"); dump_sigchunk(f, *it, true); } f << stringf(" }"); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9580e6fc0..b2b83f105 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3694,11 +3694,12 @@ struct VerificPass : public Pass { break; } -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") { verific_no_split_complex_ports = true; - continue; + goto check_error; } + +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED;