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Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
This commit is contained in:
Clifford Wolf
GitHub
commit
2a681909df
6 changed files with 173 additions and 27 deletions
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@ -9,4 +9,4 @@ OBJS += passes/equiv/equiv_induct.o
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OBJS += passes/equiv/equiv_struct.o
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OBJS += passes/equiv/equiv_purge.o
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OBJS += passes/equiv/equiv_mark.o
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OBJS += passes/equiv/equiv_opt.o
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167
passes/equiv/equiv_opt.cc
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167
passes/equiv/equiv_opt.cc
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@ -0,0 +1,167 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivOptPass : public ScriptPass
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{
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EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_opt [options] [command]\n");
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log("\n");
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log("This command checks circuit equivalence before and after an optimization pass.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to the start of the command list, and empty to\n");
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log(" label is synonymous to the end of the command list.\n");
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log("\n");
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log(" -map <filename>\n");
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log(" expand the modules in this file before proving equivalence. this is\n");
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log(" useful for handling architecture-specific primitives.\n");
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log("\n");
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log(" -assert\n");
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log(" produce an error if the circuits are not equivalent\n");
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log("\n");
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log("The following commands are executed by this verification command:\n");
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help_script();
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log("\n");
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}
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std::string command, techmap_opts;
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bool assert;
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void clear_flags() YS_OVERRIDE
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{
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command = "";
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techmap_opts = "";
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assert = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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techmap_opts += " -map " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-assert") {
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assert = true;
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continue;
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}
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break;
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}
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for (; argidx < args.size(); argidx++)
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{
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if (command.empty())
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{
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if (args[argidx].substr(0, 1) == "-")
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cmd_error(args, argidx, "Unknown option.");
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}
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else
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{
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command += " ";
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}
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command += args[argidx];
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}
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if (command.empty())
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log_cmd_error("No optimization pass specified!\n");
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing EQUIV_OPT pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("run_pass"))
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{
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run("hierarchy -auto-top");
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run("design -save preopt");
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if (help_mode)
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run("[command]");
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else
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run(command);
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run("design -stash postopt");
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}
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if (check_label("prepare"))
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{
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run("design -copy-from preopt -as gold A:top");
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run("design -copy-from postopt -as gate A:top");
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}
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if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)"))
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{
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string opts;
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if (help_mode)
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opts = " -map <filename> ...";
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else
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opts = techmap_opts;
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run("techmap -D EQUIV -autoproc" + opts);
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}
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if (check_label("prove"))
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{
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run("equiv_make gold gate equiv");
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run("equiv_induct equiv");
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if (help_mode)
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run("equiv_status [-assert] equiv");
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else if(assert)
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run("equiv_status -assert equiv");
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else
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run("equiv_status equiv");
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}
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if (check_label("restore"))
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{
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run("design -load preopt");
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}
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}
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} EquivOptPass;
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PRIVATE_NAMESPACE_END
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@ -947,6 +947,7 @@ module SB_SPRAM256KA (
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output reg [15:0] DATAOUT
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);
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`ifndef BLACKBOX
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`ifndef EQUIV
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reg [15:0] mem [0:16383];
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wire off = SLEEP || !POWEROFF;
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integer i;
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@ -973,6 +974,7 @@ module SB_SPRAM256KA (
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end
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end
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`endif
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`endif
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endmodule
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(* blackbox *)
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@ -1,13 +1,4 @@
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design -save preopt
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simplemap
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techmap -map +/gate2lut.v -D LUT_WIDTH=4
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equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
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design -load postopt
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select -assert-count 1 t:$lut
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design -stash postopt
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design -copy-from preopt -as preopt top
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design -copy-from postopt -as postopt top
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equiv_make preopt postopt equiv
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prep -flatten -top equiv
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equiv_induct
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equiv_status -assert
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@ -1,3 +0,0 @@
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module SB_CARRY (output CO, input I0, I1, CI);
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assign CO = (I0 && I1) || ((I0 || I1) && CI);
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endmodule
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@ -1,15 +1,4 @@
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read_verilog opt_lut.v
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synth_ice40
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ice40_unlut
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design -save preopt
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opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
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design -stash postopt
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design -copy-from preopt -as preopt top
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design -copy-from postopt -as postopt top
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equiv_make preopt postopt equiv
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techmap -map ice40_carry.v
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prep -flatten -top equiv
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equiv_induct
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equiv_status -assert
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equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
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