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This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
5 lines
130 B
Plaintext
5 lines
130 B
Plaintext
read_verilog opt_lut.v
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synth_ice40
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ice40_unlut
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equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
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