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Merge branch 'main' into emil/turbo-celltypes

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nella 2026-02-25 12:29:06 +01:00 • committed by GitHub
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265 changed files with 11258 additions and 3014 deletions
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47
tests/unit/kernel/modindexTest.cc Normal file
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#include <gtest/gtest.h>
#include "kernel/modtools.h"
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
TEST(ModIndexSwapTest, has)
{
Design* d = new Design;
Module* m = d->addModule("$m");
Wire* o = m->addWire("$o", 2);
o->port_input = true;
Wire* i = m->addWire("$i", 2);
i->port_input = true;
m->fixup_ports();
m->addNot("$not", i, o);
auto mi = ModIndex(m);
mi.reload_module();
for (auto [sb, info] : mi.database) {
EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
}
m->swap_names(i, o);
for (auto [sb, info] : mi.database) {
EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
}
}
TEST(ModIndexDeleteTest, has)
{
if (log_files.empty()) log_files.emplace_back(stdout);
Design* d = new Design;
Module* m = d->addModule("$m");
Wire* w = m->addWire("$w");
Wire* o = m->addWire("$o");
o->port_output = true;
m->fixup_ports();
Cell* not_ = m->addNotGate("$not", w, o);
auto mi = ModIndex(m);
mi.reload_module();
mi.dump_db();
Wire* a = m->addWire("\\a");
not_->setPort(ID::A, a);
EXPECT_TRUE(mi.ok());
}
YOSYS_NAMESPACE_END

61
tests/unit/kernel/rtlilStringTest.cc Normal file
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#include <gtest/gtest.h>
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
YOSYS_NAMESPACE_BEGIN
namespace RTLIL {
TEST(RtlilStrTest, DesignToString) {
Design design;
Module *mod = design.addModule(ID(my_module));
mod->addWire(ID(my_wire), 1);
std::string design_str = design.to_rtlil_str();
EXPECT_NE(design_str.find("module \\my_module"), std::string::npos);
EXPECT_NE(design_str.find("end"), std::string::npos);
}
TEST(RtlilStrTest, ModuleToString) {
Design design;
Module *mod = design.addModule(ID(test_mod));
Wire *wire = mod->addWire(ID(clk), 1);
wire->port_input = true;
std::string mod_str = mod->to_rtlil_str();
EXPECT_NE(mod_str.find("module \\test_mod"), std::string::npos);
EXPECT_NE(mod_str.find("wire"), std::string::npos);
EXPECT_NE(mod_str.find("\\clk"), std::string::npos);
EXPECT_NE(mod_str.find("input"), std::string::npos);
}
TEST(RtlilStrTest, WireToString) {
Design design;
Module *mod = design.addModule(ID(m));
Wire *wire = mod->addWire(ID(data), 8);
std::string wire_str = wire->to_rtlil_str();
EXPECT_NE(wire_str.find("wire"), std::string::npos);
EXPECT_NE(wire_str.find("width 8"), std::string::npos);
EXPECT_NE(wire_str.find("\\data"), std::string::npos);
}
TEST(RtlilStrTest, CellToString) {
Design design;
Module *mod = design.addModule(ID(m));
Cell *cell = mod->addCell(ID(u1), ID(my_cell_type));
std::string cell_str = cell->to_rtlil_str();
EXPECT_NE(cell_str.find("cell"), std::string::npos);
EXPECT_NE(cell_str.find("\\my_cell_type"), std::string::npos);
EXPECT_NE(cell_str.find("\\u1"), std::string::npos);
}
}
YOSYS_NAMESPACE_END