diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index f754d16c7..2c1483345 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -6,6 +6,8 @@ body: attributes: value: > + Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html#reporting-bugs) about how to report bugs. We fix well-reported bugs the fastest. + If you have a general question, please ask it on the [Discourse forum](https://yosyshq.discourse.group/). diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 60fe481e7..c9dc5fc22 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -42,7 +42,7 @@ runs: if: runner.os == 'Linux' && inputs.get-build-deps == 'true' uses: awalsh128/cache-apt-pkgs-action@v1.6.0 with: - packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev + packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev version: ${{ inputs.runs-on }}-buildys - name: Linux docs dependencies @@ -52,15 +52,6 @@ runs: packages: graphviz xdot version: ${{ inputs.runs-on }}-docsys - # if updating test dependencies, make sure to update - # docs/source/yosys_internals/extending_yosys/test_suites.rst to match. - - name: Linux test dependencies - if: runner.os == 'Linux' && inputs.get-test-deps == 'true' - uses: awalsh128/cache-apt-pkgs-action@v1.6.0 - with: - packages: libgtest-dev - version: ${{ inputs.runs-on }}-testys - - name: Install macOS Dependencies if: runner.os == 'macOS' shell: bash diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index b22a399db..8af99def8 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check @@ -37,7 +38,7 @@ jobs: persist-credentials: false - run: sudo apt-get install libfl-dev - name: Build - run: make vcxsrc YOSYS_VER=latest + run: make vcxsrc YOSYS_COMPILER="Visual Studio" VCX_DIR_NAME=yosys-win32-vcxsrc-latest - uses: actions/upload-artifact@v4 with: name: vcxsrc @@ -102,6 +103,7 @@ jobs: ENABLE_ZLIB := 0 CXXFLAGS += -I$(pwd)/flex-prefix/include + LINKFLAGS += -Wl,-z,stack-size=8388608 -Wl,--stack-first -Wl,--strip-all END make -C build -f ../Makefile CXX=clang -j$(nproc) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index f19b1c7af..e3d917942 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -1,6 +1,6 @@ name: Build docs artifact with Verific -on: [push, pull_request] +on: [push, pull_request, merge_group] jobs: check_docs_rebuild: diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 8c1a3bbd2..ebdeb15d8 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check @@ -71,6 +72,7 @@ jobs: cd build make -f ../Makefile config-$CC make -f ../Makefile -j$procs + make -f ../Makefile unit-test -j$procs - name: Log yosys-config output run: | @@ -80,7 +82,7 @@ jobs: shell: bash run: | cd build - tar -cvf ../build.tar share/ yosys yosys-* + tar -cvf ../build.tar share/ yosys yosys-* libyosys.so - name: Store build artifact uses: actions/upload-artifact@v4 @@ -130,7 +132,7 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC + make -j$procs vanilla-test TARGETS= EXTRA_TARGETS= CONFIG=$CC - name: Report errors if: ${{ failure() }} diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 31c8bccf6..000d1c400 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 4c8e3ec51..7650470c3 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # ignore PRs due to time needed # allow triggering tests, ignores skip check workflow_dispatch: @@ -64,7 +65,7 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs test TARGETS= EXTRA_TARGETS= + make -j$procs vanilla-test TARGETS= EXTRA_TARGETS= - name: Report errors if: ${{ failure() }} @@ -72,7 +73,3 @@ jobs: run: | find tests/**/*.err -print -exec cat {} \; - - name: Run unit tests - shell: bash - run: | - make -j$procs unit-test ENABLE_LIBYOSYS=1 diff --git a/.github/workflows/test-verific-cfg.yml b/.github/workflows/test-verific-cfg.yml new file mode 100644 index 000000000..232ca6bd7 --- /dev/null +++ b/.github/workflows/test-verific-cfg.yml @@ -0,0 +1,109 @@ +name: Build various Verific configurations + +on: + workflow_dispatch: + +jobs: + test-verific-cfg: + if: github.repository_owner == 'YosysHQ' + runs-on: [self-hosted, linux, x64, fast] + steps: + - name: Checkout Yosys + uses: actions/checkout@v4 + with: + persist-credentials: false + submodules: true + - name: Runtime environment + run: | + echo "procs=$(nproc)" >> $GITHUB_ENV + + - name: verific [SV] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [VHDL] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + VHDL] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + HIER] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [VHDL + HIER] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + VHDL + HIER] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 0" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs + + - name: verific [SV + VHDL + HIER + EDIF + LIBERTY] + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_SYSTEMVERILOG := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_VHDL := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_HIER_TREE := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j$procs diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 6619e1124..cd2545cc8 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -5,6 +5,7 @@ on: push: branches: - main + merge_group: # test PRs pull_request: # allow triggering tests, ignores skip check @@ -67,7 +68,7 @@ jobs: - name: Run Yosys tests run: | - make -j$procs test + make -j$procs vanilla-test - name: Run Verific specific Yosys tests run: | @@ -79,11 +80,6 @@ jobs: run: | make -C sby run_ci - - name: Run unit tests - shell: bash - run: | - make -j$procs unit-test ENABLE_LTO=1 ENABLE_LIBYOSYS=1 - test-pyosys: needs: pre-job if: ${{ needs.pre-job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} diff --git a/.github/workflows/update-flake-lock.yml b/.github/workflows/update-flake-lock.yml deleted file mode 100644 index b32498baf..000000000 --- a/.github/workflows/update-flake-lock.yml +++ /dev/null @@ -1,25 +0,0 @@ -name: update-flake-lock -on: - workflow_dispatch: # allows manual triggering - schedule: - - cron: '0 0 * * 0' # runs weekly on Sunday at 00:00 - -jobs: - lockfile: - if: github.repository == 'YosysHQ/Yosys' - runs-on: ubuntu-latest - steps: - - name: Checkout repository - uses: actions/checkout@v4 - with: - persist-credentials: false - - name: Install Nix - uses: DeterminateSystems/nix-installer-action@main - - name: Update flake.lock - uses: DeterminateSystems/update-flake-lock@main - with: - token: ${{CI_CREATE_PR_TOKEN}} - pr-title: "Update flake.lock" # Title of PR to be created - pr-labels: | # Labels to be set on the PR - dependencies - automated diff --git a/.github/workflows/version.yml b/.github/workflows/version.yml deleted file mode 100644 index 78d34db46..000000000 --- a/.github/workflows/version.yml +++ /dev/null @@ -1,34 +0,0 @@ -name: Bump version - -on: - workflow_dispatch: - schedule: - - cron: '0 0 * * *' - -jobs: - bump-version: - if: github.repository == 'YosysHQ/Yosys' - runs-on: ubuntu-latest - steps: - - name: Checkout - uses: actions/checkout@v4 - with: - fetch-depth: 0 - submodules: true - persist-credentials: false - - name: Take last commit - id: log - run: echo "message=$(git log --no-merges -1 --oneline)" >> $GITHUB_OUTPUT - - name: Bump version - if: ${{ !contains(steps.log.outputs.message, 'Bump version') }} - run: | - make bumpversion - git config --local user.email "41898282+github-actions[bot]@users.noreply.github.com" - git config --local user.name "github-actions[bot]" - git add Makefile - git commit -m "Bump version" - - name: Push changes # push the output folder to your repo - if: ${{ !contains(steps.log.outputs.message, 'Bump version') }} - uses: ad-m/github-push-action@master - with: - github_token: ${{ secrets.GITHUB_TOKEN }} diff --git a/CHANGELOG b/CHANGELOG index 6cefcc3ac..e345a8514 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,9 +2,54 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.59 .. Yosys 0.60-dev +Yosys 0.62 .. Yosys 0.63-dev -------------------------- +Yosys 0.61 .. Yosys 0.62 +-------------------------- + * Various + - verific: Added "-sv2017" flag option to support System + Verilog 2017. + - verific: Added VHDL related flags to "-f" and "-F" and + support reading VHDL file from file lists. + - Updated cell libs with proper module declaration where + non standard (...) style was used. + + * New commands and options + - Added "-word" option to "lut2mux" pass to enable emitting + word level cells. + - Added experimental "opt_balance_tree" pass to convert + cascaded cells into tree of cells to improve timing. + - Added "-gatesi" option to "write_blif" pass to init gates + under gates_mode in BLIF format. + - Added "-on" and "-off" options to "debug" pass for + persistent debug logging. + - Added "linux_perf" pass to control performance recording. + +Yosys 0.60 .. Yosys 0.61 +-------------------------- + * Various + - Removed "cover" pass for coverage tracking. + - Avoid merging formal properties with "opt_merge" pass. + - Parallelize "opt_merge" pass. + + * New commands and options + - Added "design_equal" pass to support fuzz-test comparison. + - Added "lut2bmux" pass to convert $lut to $bmux. + - Added "-legalize" option to "read_rtlil" pass to prevent + semantic errors. + +Yosys 0.59 .. Yosys 0.60 +-------------------------- + * Various + - read_verilog: suport unsized parameters. + - Added static library compile option. + + * New commands and options + - Added "sdc" pass for reading SDC files. + - Added experimental "sdc_expand" and "opensta" for OpenSTA integration. + - Added "icell_liberty" pass for used internal cells. + Yosys 0.58 .. Yosys 0.59 -------------------------- * Various diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 403292b0b..6eadbec31 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,70 +1,63 @@ -# Introduction +# Contributing to Yosys -Thanks for thinking about contributing to the Yosys project. If this is your +Thanks for considering helping out. If this is your first time contributing to an open source project, please take a look at the -following guide: +following guide about the basics: https://opensource.guide/how-to-contribute/#orienting-yourself-to-a-new-project. -Information about the Yosys coding style is available on our Read the Docs: -https://yosys.readthedocs.io/en/latest/yosys_internals/extending_yosys/contributing.html. +## Asking questions -# Using the issue tracker - -The [issue tracker](https://github.com/YosysHQ/yosys/issues) is used for -tracking bugs or other problems with Yosys or its documentation. It is also the -place to go for requesting new features. -When [creating a new issue](https://github.com/YosysHQ/yosys/issues/new/choose), -we have a few templates available. Please make use of these! It will make it -much easier for someone to respond and help. - -### Bug reports - -Before you submit an issue, please check out the [how-to guide for -`bugpoint`](https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html). -This guide will take you through the process of using the [`bugpoint` -command](https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html) in Yosys to -produce a [minimal, complete and verifiable -example](https://stackoverflow.com/help/minimal-reproducible-example) (MVCE). -Providing an MVCE with your bug report drastically increases the likelihood that -someone will be able to help resolve your issue. - - -# Using pull requests - -If you are working on something to add to Yosys, or fix something that isn't -working quite right, make a [PR](https://github.com/YosysHQ/yosys/pulls)! An -open PR, even as a draft, tells everyone that you're working on it and they -don't have to. It can also be a useful way to solicit feedback on in-progress -changes. See below to find the best way to [ask us -questions](#asking-questions). - -In general, all changes to the code are done as a PR, with [Continuous -Integration (CI)](https://github.com/YosysHQ/yosys/actions) tools that -automatically run the full suite of tests compiling and running Yosys. Please -make use of this! If you're adding a feature: add a test! Not only does it -verify that your feature is working as expected, but it can also be a handy way -for people to see how the feature is used. If you're fixing a bug: add a test! -If you can, do this first; it's okay if the test starts off failing - you -already know there is a bug. CI also helps to make sure that your changes still -work under a range of compilers, settings, and targets. - - -### Labels - -We use [labels](https://github.com/YosysHQ/yosys/labels) to help categorise -issues and PRs. If a label seems relevant to your work, please do add it; this -also includes the labels beggining with 'status-'. The 'merge-' labels are used -by maintainers for tracking and communicating which PRs are ready and pending -merge; please do not use these labels if you are not a maintainer. - - -# Asking questions - -If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/) or in our [discussions -page](https://github.com/YosysHQ/yosys/discussions). +If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/). The Discourse is also a great place to ask questions about developing or contributing to Yosys. We have open [dev 'jour fixe' (JF) meetings](https://docs.google.com/document/d/1SapA6QAsJcsgwsdKJDgnGR2mr97pJjV4eeXg_TVJhRU/edit?usp=sharing) where developers from YosysHQ and the community come together to discuss open issues and PRs. This is also a good place to talk to us about how to implement larger PRs. + +## Using the issue tracker + +The [issue tracker](https://github.com/YosysHQ/yosys/issues) is used for +tracking bugs or other problems with Yosys or its documentation. It is also the +place to go for requesting new features. + +### Bug reports + +Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html#reporting-bugs) about how to report bugs. We fix well-reported bugs the fastest. + +## Contributing code + +If you're adding complex functionality, or modifying core parts of Yosys, +we highly recommend discussing your motivation and approach +ahead of time on the [Discourse forum](https://yosyshq.discourse.group/). + +### Using pull requests + +If you are working on something to add to Yosys, or fix something that isn't +working quite right, +make a [pull request (PR)](https://github.com/YosysHQ/yosys/pulls). + +An open PR, even as a draft, tells everyone that you're working on it and they +don't have to. It can also be a useful way to solicit feedback on in-progress +changes. See above to find the best way to [ask us questions](#asking-questions). + +### Continuous integration + +[Continuous Integration (CI)](https://github.com/YosysHQ/yosys/actions) tools +automatically compile Yosys and run it with the full suite of tests. +If you're a first time contributor, a maintainer has to trigger a run for you. +We test on various platforms, compilers. Sanitizer builds are only tested +on the main branch. + +### Labels + +We use [labels](https://github.com/YosysHQ/yosys/labels) to help categorise +issues and PRs. If a label seems relevant to your work, please do add it; this +also includes the labels beginning with 'status-'. The 'merge-' labels are used +by maintainers for tracking and communicating which PRs are ready and pending +merge; please do not use these labels if you are not a maintainer. + + +### Coding style + +Learn more [here](https://yosys.readthedocs.io/en/latest/yosys_internals/extending_yosys/contributing.html). diff --git a/COPYING b/COPYING index 2d962dddc..a3ca45b42 100644 --- a/COPYING +++ b/COPYING @@ -1,6 +1,6 @@ ISC License -Copyright (C) 2012 - 2025 Claire Xenia Wolf +Copyright (C) 2012 - 2026 Claire Xenia Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above diff --git a/Dockerfile b/Dockerfile deleted file mode 100644 index 9806696e0..000000000 --- a/Dockerfile +++ /dev/null @@ -1,58 +0,0 @@ -ARG IMAGE="python:3-slim-buster" - -#--- - -FROM $IMAGE AS base - -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - ca-certificates \ - clang \ - lld \ - curl \ - libffi-dev \ - libreadline-dev \ - tcl-dev \ - graphviz \ - xdot \ - && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && update-ca-certificates \ - && rm -rf /var/lib/apt/lists - -#--- - -FROM base AS build - -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - bison \ - flex \ - gawk \ - gcc \ - git \ - iverilog \ - pkg-config \ - && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && rm -rf /var/lib/apt/lists - -COPY . /yosys - -ENV PREFIX /opt/yosys - -RUN cd /yosys \ - && make \ - && make install \ - && make test - -#--- - -FROM base - -COPY --from=build /opt/yosys /opt/yosys - -ENV PATH /opt/yosys/bin:$PATH - -RUN useradd -m yosys -USER yosys - -CMD ["yosys"] diff --git a/Makefile b/Makefile index f34b43563..f6c37d613 100644 --- a/Makefile +++ b/Makefile @@ -21,8 +21,8 @@ ENABLE_VERIFIC_HIER_TREE := 1 ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0 ENABLE_VERIFIC_EDIF := 0 ENABLE_VERIFIC_LIBERTY := 0 -ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 +ENABLE_LIBYOSYS_STATIC := 0 ENABLE_ZLIB := 1 ENABLE_HELP_SOURCE := 0 @@ -161,7 +161,19 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.59+110 +YOSYS_VER := 0.62 + +ifneq (, $(shell command -v git 2>/dev/null)) +ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) + GIT_COMMIT_COUNT := $(or $(shell git rev-list --count v$(YOSYS_VER)..HEAD 2>/dev/null),0) + ifneq ($(GIT_COMMIT_COUNT),0) + YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) + endif +else + YOSYS_VER := $(YOSYS_VER)+post +endif +endif + YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -177,15 +189,14 @@ CXXFLAGS += -DYOSYS_VER=\\"$(YOSYS_VER)\\" \ TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit) ifneq ($(findstring Format:,$(TARBALL_GIT_REV)),) GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN) +GIT_DIRTY := $(shell GIT_DIR=$(YOSYS_SRC)/.git git diff --exit-code --quiet 2>/dev/null; if [ $$? -ne 0 ]; then echo "-dirty"; fi) else GIT_REV := $(TARBALL_GIT_REV) +GIT_DIRTY := "" endif OBJS = kernel/version_$(GIT_REV).o -bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 03eb220.. | wc -l`/;" Makefile - ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) # set ABCEXTERNAL = to use an external ABC instance @@ -248,9 +259,6 @@ ifneq ($(SANITIZER),) $(info [Clang Sanitizer] $(SANITIZER)) CXXFLAGS += -g -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=$(SANITIZER) LINKFLAGS += -g -fsanitize=$(SANITIZER) -ifneq ($(findstring address,$(SANITIZER)),) -ENABLE_COVER := 0 -endif ifneq ($(findstring memory,$(SANITIZER)),) CXXFLAGS += -fPIE -fsanitize-memory-track-origins LINKFLAGS += -fPIE -fsanitize-memory-track-origins @@ -342,6 +350,9 @@ endif ifeq ($(ENABLE_LIBYOSYS),1) TARGETS += libyosys.so +ifeq ($(ENABLE_LIBYOSYS_STATIC),1) +TARGETS += libyosys.a +endif endif PY_WRAPPER_FILE = pyosys/wrappers @@ -474,6 +485,9 @@ else ifeq ($(ABCEXTERNAL),) TARGETS := $(PROGRAM_PREFIX)yosys-abc$(EXE) $(TARGETS) endif +ifeq ($(DISABLE_SPAWN),1) +$(error ENABLE_ABC=1 requires either LINK_ABC=1 or DISABLE_SPAWN=0) +endif endif endif @@ -541,10 +555,6 @@ LIBS_VERIFIC += -Wl,--whole-archive $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VE endif endif -ifeq ($(ENABLE_COVER),1) -CXXFLAGS += -DYOSYS_ENABLE_COVER -endif - ifeq ($(ENABLE_CCACHE),1) CXX := ccache $(CXX) else @@ -638,6 +648,7 @@ $(eval $(call add_include_file,kernel/yosys_common.h)) $(eval $(call add_include_file,kernel/yw.h)) $(eval $(call add_include_file,libs/ezsat/ezsat.h)) $(eval $(call add_include_file,libs/ezsat/ezminisat.h)) +$(eval $(call add_include_file,libs/ezsat/ezcmdline.h)) ifeq ($(ENABLE_ZLIB),1) $(eval $(call add_include_file,libs/fst/fstapi.h)) endif @@ -645,8 +656,6 @@ $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,libs/json11/json11.hpp)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,passes/techmap/libparse.h)) -$(eval $(call add_include_file,frontends/ast/ast.h)) -$(eval $(call add_include_file,frontends/ast/ast_binding.h)) $(eval $(call add_include_file,frontends/blif/blifparse.h)) $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) @@ -685,6 +694,7 @@ OBJS += libs/json11/json11.o OBJS += libs/ezsat/ezsat.o OBJS += libs/ezsat/ezminisat.o +OBJS += libs/ezsat/ezcmdline.o OBJS += libs/minisat/Options.o OBJS += libs/minisat/SimpSolver.o @@ -723,7 +733,6 @@ OBJS += passes/hierarchy/hierarchy.o OBJS += passes/cmds/select.o OBJS += passes/cmds/show.o OBJS += passes/cmds/stat.o -OBJS += passes/cmds/cover.o OBJS += passes/cmds/design.o OBJS += passes/cmds/plugin.o @@ -773,6 +782,9 @@ else $(P) $(CXX) -o libyosys.so -shared -Wl,-soname,libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) endif +libyosys.a: $(filter-out kernel/driver.o,$(OBJS)) + $(P) $(AR) rcs $@ $^ + %.o: %.cc $(Q) mkdir -p $(dir $@) $(P) $(CXX) -o $@ -c $(CPPFLAGS) $(CXXFLAGS) $< @@ -791,12 +803,34 @@ endif $(Q) mkdir -p $(dir $@) $(P) $(CXX) -o $@ -c $(CPPFLAGS) $(CXXFLAGS) $< -YOSYS_VER_STR := Yosys $(YOSYS_VER) (git sha1 $(GIT_REV), $(notdir $(CXX)) $(shell \ - $(CXX) --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1) $(filter -f% -m% -O% -DNDEBUG,$(CXXFLAGS))) +YOSYS_REPO := +ifneq (, $(shell command -v git 2>/dev/null)) +ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) + GIT_REMOTE := $(strip $(shell git config --get remote.origin.url 2>/dev/null | $(AWK) '{print tolower($$0)}')) + ifneq ($(strip $(GIT_REMOTE)),) + YOSYS_REPO := $(strip $(shell echo $(GIT_REMOTE) | $(AWK) -F '[:/]' '{gsub(/\.git$$/, "", $$NF); printf "%s/%s", $$(NF-1), $$NF}')) + endif + ifeq ($(strip $(YOSYS_REPO)),yosyshq/yosys) + YOSYS_REPO := + endif + GIT_BRANCH := $(shell git rev-parse --abbrev-ref HEAD 2>/dev/null) + ifeq ($(filter main HEAD release/v%,$(GIT_BRANCH)),) + YOSYS_REPO := $(YOSYS_REPO) at $(GIT_BRANCH) + endif + YOSYS_REPO := $(strip $(YOSYS_REPO)) +endif +endif + +YOSYS_GIT_STR := $(GIT_REV)$(GIT_DIRTY) +YOSYS_COMPILER := $(notdir $(CXX)) $(shell $(CXX) --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1) $(filter -f% -m% -O% -DNDEBUG,$(CXXFLAGS)) +YOSYS_VER_STR := Yosys $(YOSYS_VER) (git sha1 $(YOSYS_GIT_STR), $(YOSYS_COMPILER)) +ifneq ($(strip $(YOSYS_REPO)),) + YOSYS_VER_STR := $(YOSYS_VER_STR) [$(YOSYS_REPO)] +endif kernel/version_$(GIT_REV).cc: $(YOSYS_SRC)/Makefile $(P) rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc - $(Q) mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"$(YOSYS_VER_STR)\"; }" > kernel/version_$(GIT_REV).cc + $(Q) mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"$(YOSYS_VER_STR)\"; const char *yosys_git_hash_str=\"$(YOSYS_GIT_STR)\"; }" > kernel/version_$(GIT_REV).cc ifeq ($(ENABLE_VERIFIC),1) CXXFLAGS_NOVERIFIC = $(foreach v,$(CXXFLAGS),$(if $(findstring $(VERIFIC_DIR),$(v)),,$(v))) @@ -976,9 +1010,11 @@ makefile-tests/%: %/run-test.mk $(TARGETS) $(EXTRA_TARGETS) $(MAKE) -C $* -f run-test.mk +@echo "...passed tests in $*" -test: makefile-tests abcopt-tests seed-tests +test: vanilla-test unit-test + +vanilla-test: makefile-tests abcopt-tests seed-tests @echo "" - @echo " Passed \"make test\"." + @echo " Passed \"make vanilla-test\"." ifeq ($(ENABLE_VERIFIC),1) ifeq ($(YOSYS_NOVERIFIC),1) @echo " Ran tests without verific support due to YOSYS_NOVERIFIC=1." @@ -1010,11 +1046,11 @@ ystests: $(TARGETS) $(EXTRA_TARGETS) # Unit test unit-test: libyosys.so - @$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CC="$(CC)" CPPFLAGS="$(CPPFLAGS)" \ + @$(MAKE) -f $(UNITESTPATH)/Makefile CXX="$(CXX)" CC="$(CC)" CPPFLAGS="$(CPPFLAGS)" \ CXXFLAGS="$(CXXFLAGS)" LINKFLAGS="$(LINKFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)" clean-unit-test: - @$(MAKE) -C $(UNITESTPATH) clean + @$(MAKE) -f $(UNITESTPATH)/Makefile clean install-dev: $(PROGRAM_PREFIX)yosys-config share $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR) @@ -1024,7 +1060,7 @@ install-dev: $(PROGRAM_PREFIX)yosys-config share install: $(TARGETS) $(EXTRA_TARGETS) $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR) - $(INSTALL_SUDO) cp $(filter-out libyosys.so,$(TARGETS)) $(DESTDIR)$(BINDIR) + $(INSTALL_SUDO) cp $(filter-out libyosys.so libyosys.a,$(TARGETS)) $(DESTDIR)$(BINDIR) ifneq ($(filter $(PROGRAM_PREFIX)yosys,$(TARGETS)),) if [ -n "$(STRIP)" ]; then $(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys; fi endif @@ -1040,13 +1076,18 @@ ifeq ($(ENABLE_LIBYOSYS),1) $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(LIBDIR) $(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(LIBDIR)/ if [ -n "$(STRIP)" ]; then $(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(LIBDIR)/libyosys.so; fi +ifeq ($(ENABLE_LIBYOSYS_STATIC),1) + $(INSTALL_SUDO) cp libyosys.a $(DESTDIR)$(LIBDIR)/ +endif ifeq ($(ENABLE_PYOSYS),1) $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys $(INSTALL_SUDO) cp $(YOSYS_SRC)/pyosys/__init__.py $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/__init__.py $(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/libyosys.so $(INSTALL_SUDO) cp -r share $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys ifeq ($(ENABLE_ABC),1) - $(INSTALL_SUDO) cp yosys-abc $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/yosys-abc +ifeq ($(ABCEXTERNAL),) + $(INSTALL_SUDO) cp $(PROGRAM_PREFIX)yosys-abc$(EXE) $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/yosys-abc$(EXE) +endif endif endif endif @@ -1062,6 +1103,9 @@ uninstall: $(INSTALL_SUDO) rm -rvf $(DESTDIR)$(DATDIR) ifeq ($(ENABLE_LIBYOSYS),1) $(INSTALL_SUDO) rm -vf $(DESTDIR)$(LIBDIR)/libyosys.so +ifeq ($(ENABLE_LIBYOSYS_STATIC),1) + $(INSTALL_SUDO) rm -vf $(DESTDIR)$(LIBDIR)/libyosys.a +endif ifeq ($(ENABLE_PYOSYS),1) $(INSTALL_SUDO) rm -vf $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/libyosys.so $(INSTALL_SUDO) rm -vf $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/__init__.py @@ -1160,7 +1204,7 @@ clean-py: rm -f $(PY_WRAPPER_FILE).inc.cc $(PY_WRAPPER_FILE).cc rm -f $(PYTHON_OBJECTS) rm -f *.whl - rm -f libyosys.so + rm -f libyosys.so libyosys.a rm -rf kernel/*.pyh clean-abc: @@ -1194,15 +1238,17 @@ qtcreator: { echo .; find backends frontends kernel libs passes -type f \( -name '*.h' -o -name '*.hh' \) -printf '%h\n' | sort -u; } > qtcreator.includes touch qtcreator.creator -vcxsrc: $(GENFILES) $(EXTRA_TARGETS) - rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip} +VCX_DIR_NAME := yosys-win32-vcxsrc-$(YOSYS_VER) +vcxsrc: $(GENFILES) $(EXTRA_TARGETS) kernel/version_$(GIT_REV).cc + rm -rf $(VCX_DIR_NAME){,.zip} + cp -f kernel/version_$(GIT_REV).cc kernel/version.cc set -e; for f in `ls $(filter %.cc %.cpp,$(GENFILES)) $(addsuffix .cc,$(basename $(OBJS))) $(addsuffix .cpp,$(basename $(OBJS))) 2> /dev/null`; do \ echo "Analyse: $$f" >&2; cpp -std=c++17 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt echo "libs/fst/fst_win_unistd.h" >> srcfiles.txt - bash misc/create_vcxsrc.sh yosys-win32-vcxsrc $(YOSYS_VER) $(GIT_REV) - echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys (Version Information Unavailable)\"; }" > kernel/version.cc - zip yosys-win32-vcxsrc-$(YOSYS_VER)/genfiles.zip $(GENFILES) kernel/version.cc - zip -r yosys-win32-vcxsrc-$(YOSYS_VER).zip yosys-win32-vcxsrc-$(YOSYS_VER)/ + echo "kernel/version.cc" >> srcfiles.txt + bash misc/create_vcxsrc.sh $(VCX_DIR_NAME) $(YOSYS_VER) + zip $(VCX_DIR_NAME)/genfiles.zip $(GENFILES) kernel/version.cc + zip -r $(VCX_DIR_NAME).zip $(VCX_DIR_NAME)/ rm -f srcfiles.txt kernel/version.cc config-clean: clean diff --git a/README.md b/README.md index 427d59c9e..df65a6a10 100644 --- a/README.md +++ b/README.md @@ -114,8 +114,8 @@ To build Yosys simply type 'make' in this directory. $ sudo make install Tests are located in the tests subdirectory and can be executed using the test -target. Note that you need gawk as well as a recent version of iverilog (i.e. -build from git). Then, execute tests via: +target. Note that you need gawk, a recent version of iverilog, and gtest. +Execute tests via: $ make test @@ -246,6 +246,8 @@ Building the documentation Note that there is no need to build the manual if you just want to read it. Simply visit https://yosys.readthedocs.io/en/latest/ instead. +If you're offline, you can read the sources, replacing `.../en/latest` +with `docs/source`. In addition to those packages listed above for building Yosys from source, the following are used for building the website: diff --git a/abc b/abc index 1c5ed1ce3..c18b835ef 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 1c5ed1ce378cc04beac30bb31abc4c37c8467042 +Subproject commit c18b835ef140217c84a26ba510f98f69d54dd48e diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0b2f06959..5f7e71a3a 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -24,6 +24,7 @@ #include "kernel/register.h" #include "kernel/celltypes.h" +#include "kernel/rtlil.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -847,11 +848,14 @@ struct XAigerAnalysis : Index { return false; int max = 1; - for (auto wire : mod->wires()) - if (wire->port_input && !wire->port_output) - for (int i = 0; i < wire->width; i++) { - int ilevel = visit(cursor, driver->getPort(wire->name)[i]); - max = std::max(max, ilevel + 1); + for (auto wire : mod->wires()) { + if (wire->port_input && !wire->port_output) { + SigSpec port = driver->getPort(wire->name); + for (int i = 0; i < std::min(wire->width, port.size()); i++) { + int ilevel = visit(cursor, port[i]); + max = std::max(max, ilevel + 1); + } + } } lits[idx] = max; diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index be7287917..cc339bcbc 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -44,6 +44,7 @@ struct BlifDumperConfig bool iattr_mode; bool blackbox_mode; bool noalias_mode; + bool gatesi_mode; std::string buf_type, buf_in, buf_out; std::map> unbuf_types; @@ -51,7 +52,7 @@ struct BlifDumperConfig BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false), cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false), - blackbox_mode(false), noalias_mode(false) { } + blackbox_mode(false), noalias_mode(false), gatesi_mode(false) { } }; struct BlifDumper @@ -118,16 +119,21 @@ struct BlifDumper return str; } - const std::string str_init(RTLIL::SigBit sig) + template const std::string str_init(RTLIL::SigBit sig) { sigmap.apply(sig); - if (init_bits.count(sig) == 0) - return " 2"; + if (init_bits.count(sig) == 0) { + if constexpr (Space) + return " 2"; + else + return "2"; + } - string str = stringf(" %d", init_bits.at(sig)); - - return str; + if constexpr (Space) + return stringf(" %d", init_bits.at(sig)); + else + return stringf("%d", init_bits.at(sig)); } const char *subckt_or_gate(std::string cell_type) @@ -469,6 +475,11 @@ struct BlifDumper f << stringf(".names %s %s\n1 1\n", str(rhs_bit), str(lhs_bit)); } + if (config->gatesi_mode) { + for (auto &&init_bit : init_bits) + f << stringf(".gateinit %s=%s\n", str(init_bit.first), str_init(init_bit.first)); + } + f << stringf(".end\n"); } @@ -550,6 +561,9 @@ struct BlifBackend : public Backend { log(" -impltf\n"); log(" do not write definitions for the $true, $false and $undef wires.\n"); log("\n"); + log(" -gatesi\n"); + log(" write initial bit(s) with .gateinit for gates that needs to be initialized.\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -640,6 +654,10 @@ struct BlifBackend : public Backend { config.noalias_mode = true; continue; } + if (args[argidx] == "-gatesi") { + config.gatesi_mode = true; + continue; + } break; } extra_args(f, filename, args, argidx); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index d575b5879..71913d2db 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -756,7 +756,7 @@ struct CxxrtlWorker { // 1b. Generated identifiers for internal names (beginning with `$`) start with `i_`. // 2. An underscore is escaped with another underscore, i.e. `__`. // 3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`. - std::string mangle_name(const RTLIL::IdString &name) + std::string mangle_name(RTLIL::IdString name) { std::string mangled; bool first = true; @@ -786,7 +786,7 @@ struct CxxrtlWorker { return mangled; } - std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false) + std::string mangle_module_name(RTLIL::IdString name, bool is_blackbox = false) { // Class namespace. if (is_blackbox) @@ -794,19 +794,19 @@ struct CxxrtlWorker { return mangle_name(name); } - std::string mangle_memory_name(const RTLIL::IdString &name) + std::string mangle_memory_name(RTLIL::IdString name) { // Class member namespace. return "memory_" + mangle_name(name); } - std::string mangle_cell_name(const RTLIL::IdString &name) + std::string mangle_cell_name(RTLIL::IdString name) { // Class member namespace. return "cell_" + mangle_name(name); } - std::string mangle_wire_name(const RTLIL::IdString &name) + std::string mangle_wire_name(RTLIL::IdString name) { // Class member namespace. return mangle_name(name); diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index 8abfe3e41..73e1b48c6 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -188,20 +188,27 @@ struct SmtrModule { Functional::IR ir; SmtrScope scope; std::string name; - + bool use_assoc_list_helpers; + std::optional input_helper_name; + std::optional output_helper_name; + SmtrStruct input_struct; SmtrStruct output_struct; SmtrStruct state_struct; - SmtrModule(Module *module) - : ir(Functional::IR::from_module(module)) - , scope() - , name(scope.unique_name(module->name)) - , input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope) - , output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope) - , state_struct(scope.unique_name(module->name.str() + "_State"), scope) + SmtrModule(Module *module, bool assoc_list_helpers) + : ir(Functional::IR::from_module(module)), scope(), name(scope.unique_name(module->name)), use_assoc_list_helpers(assoc_list_helpers), + input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope), + output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope), + state_struct(scope.unique_name(module->name.str() + "_State"), scope) { scope.reserve(name + "_initial"); + if (assoc_list_helpers) { + input_helper_name = scope.unique_name(module->name.str() + "_inputs_helper"); + scope.reserve(*input_helper_name); + output_helper_name = scope.unique_name(module->name.str() + "_outputs_helper"); + scope.reserve(*output_helper_name); + } for (auto input : ir.inputs()) input_struct.insert(input->name, input->sort); for (auto output : ir.outputs()) @@ -257,6 +264,45 @@ struct SmtrModule { w.pop(); } + void write_assoc_list_helpers(SExprWriter &w) + { + log_assert(output_helper_name && input_helper_name); + + // Input struct keyword-based constructor. + w.push(); + w.open(list("define")); + const auto inputs_name = "inputs"; + w.open(list(*input_helper_name, inputs_name)); + w.close(); + w.open(list(input_struct.name)); + for (auto input : ir.inputs()) { + w.push(); + w.open(list("let")); + w.push(); + w.open(list()); + w.open(list("assoc-result")); + w << list("assoc", "\"" + RTLIL::unescape_id(input->name) + "\"", inputs_name); + w.pop(); + w.open(list("if", "assoc-result")); + w << list("cdr", "assoc-result"); + w.open(list("begin")); + w << list("fprintf", list("current-error-port"), "\"%s not found in inputs\""); + w << "'not-found"; + w.pop(); + } + w.pop(); + // Output struct keyword-based destructuring + w.push(); + w.open(list("define")); + const auto outputs_name = "outputs"; + w << list(*output_helper_name, outputs_name); + w.open(list("list")); + for (auto output : ir.outputs()) { + w << list("cons", "\"" + RTLIL::unescape_id(output->name) + "\"", output_struct.access("outputs", output->name)); + } + w.pop(); + } + void write(std::ostream &out) { SExprWriter w(out); @@ -265,6 +311,10 @@ struct SmtrModule { output_struct.write_definition(w); state_struct.write_definition(w); + if (use_assoc_list_helpers) { + write_assoc_list_helpers(w); + } + write_eval(w); write_initial(w); } @@ -282,12 +332,16 @@ struct FunctionalSmtrBackend : public Backend { log("\n"); log(" -provides\n"); log(" include 'provide' statement(s) for loading output as a module\n"); + log(" -assoc-list-helpers\n"); + log(" provide helper functions which convert inputs/outputs from/to association lists\n"); + log(" \n"); log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { auto provides = false; + auto assoc_list_helpers = false; log_header(design, "Executing Functional Rosette Backend.\n"); @@ -296,6 +350,8 @@ struct FunctionalSmtrBackend : public Backend { { if (args[argidx] == "-provides") provides = true; + else if (args[argidx] == "-assoc-list-helpers") + assoc_list_helpers = true; else break; } @@ -307,8 +363,8 @@ struct FunctionalSmtrBackend : public Backend { } for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name); - SmtrModule smtr(module); + log("Processing module `%s`.\n", module->name.c_str()); + SmtrModule smtr(module, assoc_list_helpers); smtr.write(*f); } } diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index 4e47117b3..9dfbd2a25 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -735,6 +735,12 @@ def ywfile_signal(sig, step, mask=None): output = [] + def ywfile_signal_error(reason, detail=None): + msg = f"Yosys witness signal mismatch for {sig.pretty()}: {reason}" + if detail: + msg += f" ({detail})" + raise ValueError(msg) + if sig.path in smt_wires: for wire in smt_wires[sig.path]: width, offset = wire["width"], wire["offset"] @@ -765,6 +771,12 @@ def ywfile_signal(sig, step, mask=None): for mem in smt_mems[sig.memory_path]: width, size, bv = mem["width"], mem["size"], mem["statebv"] + if sig.memory_addr is not None and sig.memory_addr >= size: + ywfile_signal_error( + "memory address out of bounds", + f"address={sig.memory_addr} size={size}", + ) + smt_expr = smt.net_expr(topmod, f"s{step}", mem["smtpath"]) if bv: @@ -781,18 +793,34 @@ def ywfile_signal(sig, step, mask=None): smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr) output.append((0, sig.width, smt_expr)) + else: + ywfile_signal_error("memory not found in design") output.sort() output = [chunk for chunk in output if chunk[0] != chunk[1]] + if not output: + if sig.memory_path: + ywfile_signal_error("memory signal has no matching bits in design") + else: + ywfile_signal_error("signal not found in design") + pos = 0 for start, end, smt_expr in output: - assert start == pos + if start != pos: + ywfile_signal_error( + "signal width/offset mismatch", + f"expected coverage at bit {pos}", + ) pos = end - assert pos == sig.width + if pos != sig.width: + ywfile_signal_error( + "signal width/offset mismatch", + f"covered {pos} of {sig.width} bits", + ) if len(output) == 1: return output[0][-1] diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 8d77160fd..73ffcbf3e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -95,7 +95,8 @@ bool VERILOG_BACKEND::id_is_verilog_escaped(const std::string &str) { PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, + noparallelcase, default_params; int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter; dict auto_name_map; std::set reg_wires; @@ -421,6 +422,13 @@ void dump_attributes(std::ostream &f, std::string indent, dictattributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); @@ -2143,6 +2151,9 @@ void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs) bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) { + if (sw->cases.empty()) + return true; + for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { if ((*it)->compare.size() == 0) { break; @@ -2435,6 +2446,10 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << indent + " " << "reg " << id(initial_id) << " = 0;\n"; } + if (default_params) + for (auto p : module->parameter_default_values) + dump_parameter(f, indent + " ", p.first, p.second); + // first dump input / output according to their order in module->ports for (auto port : module->ports) dump_wire(f, indent + " ", module->wire(port)); @@ -2542,6 +2557,10 @@ struct VerilogBackend : public Backend { log(" use 'defparam' statements instead of the Verilog-2001 syntax for\n"); log(" cell parameters.\n"); log("\n"); + log(" -default_params\n"); + log(" emit module parameter declarations from\n"); + log(" parameter_default_values.\n"); + log("\n"); log(" -blackboxes\n"); log(" usually modules with the 'blackbox' attribute are ignored. with\n"); log(" this option set only the modules with the 'blackbox' attribute\n"); @@ -2579,6 +2598,7 @@ struct VerilogBackend : public Backend { siminit = false; simple_lhs = false; noparallelcase = false; + default_params = false; auto_prefix = ""; bool blackboxes = false; @@ -2639,6 +2659,10 @@ struct VerilogBackend : public Backend { defparam = true; continue; } + if (arg == "-defaultparams") { + default_params = true; + continue; + } if (arg == "-decimal") { decimal = true; continue; diff --git a/docs/source/code_examples/macro_commands/prep.ys b/docs/source/code_examples/macro_commands/prep.ys index 1bec907f6..7ec7c7af8 100644 --- a/docs/source/code_examples/macro_commands/prep.ys +++ b/docs/source/code_examples/macro_commands/prep.ys @@ -17,6 +17,7 @@ coarse: opt_clean memory_collect opt -noff -keepdc -fast + sort check: stat diff --git a/docs/source/conf.py b/docs/source/conf.py index fb106bddb..a7da22d97 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -5,8 +5,8 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' -copyright ='2025 YosysHQ GmbH' -yosys_ver = "0.59" +copyright ='2026 YosysHQ GmbH' +yosys_ver = "0.62" # select HTML theme html_theme = 'furo-ys' diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst index a557360b7..ef52bfc25 100644 --- a/docs/source/using_yosys/verilog.rst +++ b/docs/source/using_yosys/verilog.rst @@ -355,6 +355,9 @@ from SystemVerilog: design with `read_verilog`, all its packages are available to SystemVerilog files being read into the same design afterwards. + - nested packages are currently not supported (i.e. calling ``import`` inside + a ``package`` .. ``endpackage`` block) + - typedefs are supported (including inside packages) - type casts are currently not supported diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 70170fc48..458d7dc36 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -1,57 +1,16 @@ Contributing to Yosys ===================== -.. note:: - - For information on making a pull request on github, refer to our - |CONTRIBUTING|_ file. - -.. |CONTRIBUTING| replace:: :file:`CONTRIBUTING.md` -.. _CONTRIBUTING: https://github.com/YosysHQ/yosys/blob/main/CONTRIBUTING.md - -Coding Style ------------- - -Formatting of code -~~~~~~~~~~~~~~~~~~ - -- Yosys code is using tabs for indentation. Tabs are 8 characters. - -- A continuation of a statement in the following line is indented by two - additional tabs. - -- Lines are as long as you want them to be. A good rule of thumb is to break - lines at about column 150. - -- Opening braces can be put on the same or next line as the statement opening - the block (if, switch, for, while, do). Put the opening brace on its own line - for larger blocks, especially blocks that contains blank lines. - -- Otherwise stick to the `Linux Kernel Coding Style`_. - -.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst - - -C++ Language -~~~~~~~~~~~~ - -Yosys is written in C++17. - -In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings -for implicit type casts, always use ``GetSize(foobar)`` instead of -``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) - -Use range-based for loops whenever applicable. - - Reporting bugs -------------- -- use the `bug report template`_ +A good bug report includes the following information: -.. _bug report template: https://github.com/YosysHQ/yosys/issues/new?template=bug_report.yml -- short title briefly describing the issue, e.g. +Title +~~~~~ + +briefly describe the issue, for example: techmap of wide mux with undefined inputs raises error during synth_xilinx @@ -64,10 +23,18 @@ Reporting bugs Reproduction Steps ~~~~~~~~~~~~~~~~~~ -- ideally a code-block (starting and ending with triple backquotes) containing - the minimized design (Verilog or RTLIL), followed by a code-block containing - the minimized yosys script OR a command line call to yosys with - code-formatting (starting and ending with single backquotes) +The reproduction steps should be a minimal, complete and verifiable +example `MVCE`_. +Providing an MVCE with your bug report drastically increases the likelihood that +someone will be able to help resolve your issue. +One way to minimize a design is to use the `bugpoint_` command. +You can learn more in the `how-to guide for bugpoint_`. + +The reproduction steps are ideally a code-block (starting and ending with +triple backquotes) containing +the minimized design (Verilog or RTLIL), followed by a code-block containing +the minimized yosys script OR a command line call to yosys with +code-formatting (starting and ending with single backquotes). .. code-block:: markdown @@ -86,9 +53,9 @@ Reproduction Steps `yosys -p ': minimum sequence of commands;' min.v` -- alternatively can provide a single code-block which includes the minimized - design as a "here document" followed by the sequence of commands which - reproduce the error +Alternatively, you can provide a single code-block which includes the minimized +design as a "here document" followed by the sequence of commands which +reproduce the error + see :doc:`/using_yosys/more_scripting/load_design` for more on heredocs. @@ -101,7 +68,9 @@ Reproduction Steps # minimum sequence of commands ``` -- any environment variables or command line options should also be mentioned +Don't forget to mention: + +- any important environment variables or command line options - if the problem occurs for a range of values/designs, what is that range - if you're using an external tool, such as ``valgrind``, to detect the issue, what version of that tool are you using and what options are you giving it @@ -115,46 +84,58 @@ Reproduction Steps around Yosys such as OpenLane; you should instead minimize your input and reproduction steps to just the Yosys part. -"Expected Behaviour" -~~~~~~~~~~~~~~~~~~~~ +.. _MVCE: https://stackoverflow.com/help/minimal-reproducible-example +.. _bugpoint: https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html +.. _how-to guide for bugpoint: https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html -- if you have a similar design/script that doesn't give the error, include it - here as a reference -- if the bug is that an error *should* be raised but isn't, are there any other - commands with similar error messages - - -"Actual Behaviour" +Expected Behaviour ~~~~~~~~~~~~~~~~~~ -- any error messages go here -- any details relevant to the crash that were found with ``--trace`` or - ``--debug`` flags -- if you identified the point of failure in the source code, you could mention - it here, or as a comment below +Describe what you'd expect to happen when we follow the reproduction steps +if the bug was fixed. - + if possible, use a permalink to the source on GitHub - + you can browse the source repository for a certain commit with the failure +If you have a similar design/script that doesn't give the error, include it +here as a reference. If the bug is that an error *should* be raised but isn't, +note if there are any other commands with similar error messages. + + +Actual Behaviour +~~~~~~~~~~~~~~~~ + +Describe what you actually see when you follow the reproduction steps. + +This can include: + +* any error messages +* any details relevant to the crash that were found with ``--trace`` or + ``--debug`` flags +* the part of the source code that triggers the bug + + * if possible, use a permalink to the source on GitHub + * you can browse the source repository for a certain commit with the failure and open the source file, select the relevant lines (click on the line number for the first relevant line, then while holding shift click on the line number for the last relevant line), click on the ``...`` that appears and select "Copy permalink" - + should look something like + * should look something like ``https://github.com/YosysHQ/yosys/blob//path/to/file#L139-L147`` - + clicking on "Preview" should reveal a code block containing the lines of + * clicking on "Preview" should reveal a code block containing the lines of source specified, with a link to the source file at the given commit -Additional details +Additional Details ~~~~~~~~~~~~~~~~~~ -- once you have created the issue, any additional details can be added as a - comment on that issue -- could include any additional context as to what you were doing when you first - encountered the bug -- was this issue discovered through the use of a fuzzer -- if you've minimized the script, consider including the `bugpoint` script you - used, or the original script, e.g. +Anything else you think might be helpful or relevant when verifying or fixing +the bug. + +Once you have created the issue, any additional details can be added as a +comment on that issue. You can include any additional context as to what you +were doing when you first encountered the bug. + +If this issue discovered through the use of a fuzzer, ALWAYS declare that. +If you've minimized the script, consider including the `bugpoint` script you +used, or the original script, for example: .. code-block:: markdown @@ -171,8 +152,226 @@ Additional details Minimized from `yosys -p ': original sequence of commands to produce error;' design.v` -- if you're able to, it may also help to share the original un-minimized design - - + if the design is too big for a comment, consider turning it into a `Gist`_ +If possible, it may also help to share the original un-minimized design. +If the design is too big for a comment, consider turning it into a `Gist`_ .. _Gist: https://gist.github.com/ + +Contributing code +----------------- + +Code that matters +~~~~~~~~~~~~~~~~~ + +If you're adding complex functionality, or modifying core parts of yosys, +we highly recommend discussing your motivation and approach +ahead of time on the `Discourse forum`_. Please, be as explicit and concrete +as possible when explaining the motivation for what you're building. +Additionally, if you do so on the forum first before you starting hacking +away at C++, you might solve your problem without writing a single line +of code! + +PRs are considered for relevance, priority, and quality +based on their descriptions first, code second. + +Before you build or fix something, also search for existing `issues`_. + +.. _`Discourse forum`: https://yosyshq.discourse.group/ +.. _`issues`: https://github.com/YosysHQ/yosys/issues + +Making sense +~~~~~~~~~~~~ + +Given enough effort, the behavior of any code can be figured out to any +desired extent. However, the author of the code is by far in the best +position to make this as easy as possible. + +Yosys is a long-standing project and has accumulated a lot of C-style code +that's not written to be read, just written to run. We improve this bit +by bit when opportunities arise, but it is what it is. +New additions are expected to be a lot cleaner. + +The purpose and behavior of the code changed should be described clearly. +Your change should contain exactly what it needs to match that description. +This means: + +* nothing more than that - no dead code, no undocumented features +* nothing missing - if something is partially built, that's fine, + but you have to make that clear. For example, some passes + only support some types of cells + +Here are some software engineering approaches that help: + +* Use abstraction to model the problem and hide details + + * Maximize the usage of types (structs over loose variables), + not necessarily in an object-oriented way + * Use functions, scopes, type aliases + +* In new passes, make sure the logic behind how and why it works is actually provided + in coherent comments, and that variable and type naming is consistent with the terms + you use in the description. +* The logic of the implementation should be described in mathematical + or algorithm theory terms. Correctness, termination, computational complexity. + Make it clear if you're re-implementing a classic data structure for logic synthesis + or graph traversal etc. + +* There's various ways of traversing the design with use-def indices (for getting + drivers and driven signals) available in Yosys. They have advantages and sometimes + disadvantages. Prefer not re-implementing these +* Prefer references over pointers, and smart pointers over raw pointers +* Aggressively deduplicate code. Within functions, within passes, + across passes, even against existing code +* Prefer declaring things ``const`` +* Prefer range-based for loops over C-style + +Common mistakes +~~~~~~~~~~~~~~~ + +* Deleting design objects invalidates iterators. Defer deletions or hold a copy + of the list of pointers to design objects +* Deleting wires can get sketchy and is intended to be done solely by + the ``opt_clean`` pass so just don't do it +* Iterating over an entire design and checking if things are selected is more + inefficient than using the ``selected_*`` methods +* Remember to call ``fixup_ports`` at the end if you're modifying module interfaces + +Testing your change +~~~~~~~~~~~~~~~~~~~ + +Untested code can't be maintained. Inevitable codebase-wide changes +are likely to break anything untested. Tests also help reviewers understand +the purpose of the code change in practice. + +Your code needs to come with tests. If it's a feature, a test that covers +representative examples of the added behavior. If it's a bug fix, it should +reproduce the original isolated bug. But in some situations, adding a test +isn't viable. If you can't provide a test, explain this decision. + +Prefer writing unit tests (:file:`tests/unit`) for isolated tests to +the internals of more serious code changes, like those to the core of yosys, +or more algorithmic ones. + +The rest of the test suite is mostly based on running Yosys on various Yosys +and Tcl scripts that manually call Yosys commands. +See :doc:`/yosys_internals/extending_yosys/test_suites` for more information +about how our test suite is structured. +The basic test writing approach is checking +for the presence of some kind of object or pattern with ``-assert-count`` in +:doc:`/using_yosys/more_scripting/selections`. + +It's often best to use equivalence checking with ``equiv_opt -assert`` +or similar to prove that the changes done to the design by a modified pass +preserve equivalence. But some code isn't meant to preserve equivalence. +Sometimes proving equivalence takes an impractically long time for larger +inputs. Also beware, the ``equiv_`` passes are a bit quirky and might even +have incorrect results in unusual situations. + +.. Changes to core parts of Yosys or passes that are included in synthesis flows +.. can change runtime and memory usage - for the better or for worse. This strongly +.. depends on the design involved. Such risky changes should then be benchmarked +.. with various designs. + +.. TODO Emil benchmarking + +Coding style +~~~~~~~~~~~~ + +Yosys is written in C++17. + +In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings +for implicit type casts, always use ``GetSize(foobar)`` instead of +``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) + +For auto formatting code, a :file:`.clang-format` file is present top-level. +Yosys code is using tabs for indentation. A tab is 8 characters wide, +but prefer not relying on it. A continuation of a statement +in the following line is indented by two additional tabs. Lines are +as long as you want them to be. A good rule of thumb is to break lines +at about column 150. Opening braces can be put on the same or next line +as the statement opening the block (if, switch, for, while, do). +Put the opening brace on its own line for larger blocks, especially +blocks that contains blank lines. Remove trailing whitespace on sight. + +Otherwise stick to the `Linux Kernel Coding Style`_. + +.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst + +Git style +~~~~~~~~~ + +We don't have a strict commit message style. + +Some style hints: + +* Refactor and document existing code if you touch it, + but in separate commits from your functional changes +* Prefer smaller commits organized by good chunks. Git has a lot of features + like fixup commits, interactive rebase with autosquash + +Reviewing PRs +------------- + +Reviewing PRs is a totally valid form of external contributing to the project! + +Who's the reviewer? +~~~~~~~~~~~~~~~~~~~ + +Yosys HQ is a company with the inherited mandate to make decisions on behalf +of the open source project. As such, we at HQ are collectively the maintainers. +Within HQ, we allocate reviews based on expertise with the topic at hand +as well as member time constraints. + +If you're intimately acquainted with a part of the codebase, we will be happy +to defer to your experience and have you review PRs. The official way we like +is our CODEOWNERS file in the git repository. What we're looking for in code +owners is activity and trust. For activity, if you're only interested in +a yosys pass for example for the time you spend writing a thesis, it might be +better to focus on writing good tests and docs in the PRs you submit rather than +to commit to code ownership and therefore to be responsible for fixing things +and reviewing other people's PRs at various unexpected points later. If you're +prolific in some part of the codebase and not a code owner, we still value your +experience and may tag you in PRs. + +As a matter of fact, the purpose of code ownership is to avoid maintainer +burnout by removing orphaned parts of the codebase. If you become a code owner +and stop being responsive, in the future, we might decide to remove such code +if convenient and costly to maintain. It's simply more respectful of the users' +time to explicitly cut something out than let it "bitrot". Larger projects like +LLVM or linux could not survive without such things, but Yosys is far smaller, +and there are expectations + +.. TODO this deserves its own section elsewhere I think? But it would be distracting elsewhere + +Sometimes, multiple maintainers may add review comments. This is considered +healthy collaborative even if it might create disagreement at times. If +somebody is already reviewing a PR, others, even non-maintainers are free to +leave comments with extra observations and alternate perspectives in a +collaborative spirit. + +How to review +~~~~~~~~~~~~~ + +First, read everything above about contributing. Those are the values you +should gently enforce as a reviewer. They're ordered by importance, but +explicitly, descriptions are more important than code, long-form comments +describing the design are more important than piecemeal comments, etc. + +If a PR is poorly described, incomplete, tests are broken, or if the +author is not responding, please don't feel pressured to take over their +role by reverse engineering the code or fixing things for them, unless +there are good reasons to do so. + +If a PR author submits LLM outputs they haven't understood themselves, +they will not be able to implement feedback. Take this into consideration +as well. We do not ban LLM code from the codebase, we ban bad code. + +Reviewers may have diverse styles of communication while reviewing - one +may do one thorough review, another may prefer a back and forth with the +basics out the way before digging into the code. Generally, PRs may have +several requests for modifications and long discussions, but often +they just are good enough to merge as-is. + +The CI is required to go green for merging. New contributors need a CI +run to be triggered by a maintainer before their PRs take up computing +resources. It's a single click from the github web interface. diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 81a79e77f..d3422b23a 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -8,7 +8,44 @@ Running the included test suite The Yosys source comes with a test suite to avoid regressions and keep everything working as expected. Tests can be run by calling ``make test`` from -the root Yosys directory. +the root Yosys directory. By default, this runs vanilla and unit tests. + +Vanilla tests +~~~~~~~~~~~~~ + +These make up the majority of our testing coverage. +They can be run with ``make vanilla-test`` and are based on calls to +make subcommands (``make makefile-tests``) and shell scripts +(``make seed-tests`` and ``make abcopt-tests``). Both use ``run-test.sh`` +files, but make-based tests only call ``tests/gen-tests-makefile.sh`` +to generate a makefile appropriate for the given directory, so only +afterwards when make is invoked do the tests actually run. + +Usually their structure looks something like this: +you write a .ys file that gets automatically run, +which runs a frontend like ``read_verilog`` or ``read_rtlil`` with +a relative path or a heredoc, then runs some commands including the command +under test, and then uses :doc:`/using_yosys/more_scripting/selections` +with ``-assert-count``. Usually it's unnecessary to "register" the test anywhere +as if it's being added to an existing directory, depending +on how the ``run-test.sh`` in that directory works. + +Unit tests +~~~~~~~~~~ + +Running the unit tests requires the following additional packages: + +.. tab:: Ubuntu + + .. code:: console + + sudo apt-get install libgtest-dev + +.. tab:: macOS + + No additional requirements. + +Unit tests can be run with ``make unit-test``. Functional tests ~~~~~~~~~~~~~~~~ @@ -41,23 +78,6 @@ instructions `_. Then, set the :makevar:`ENABLE_FUNCTIONAL_TESTS` make variable when calling ``make test`` and the functional tests will be run as well. -Unit tests -~~~~~~~~~~ - -Running the unit tests requires the following additional packages: - -.. tab:: Ubuntu - - .. code:: console - - sudo apt-get install libgtest-dev - -.. tab:: macOS - - No additional requirements. - -Unit tests can be run with ``make unit-test``. - Docs tests ~~~~~~~~~~ diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 2c7780420..9931ef78f 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -286,10 +286,15 @@ end_of_header: RTLIL::IdString escaped_s = stringf("\\%s", s); RTLIL::Wire* wire; - if (c == 'i') wire = inputs[l1]; - else if (c == 'l') wire = latches[l1]; - else if (c == 'o') { + if (c == 'i') { + log_assert(l1 < inputs.size()); + wire = inputs[l1]; + } else if (c == 'l') { + log_assert(l1 < latches.size()); + wire = latches[l1]; + } else if (c == 'o') { wire = module->wire(escaped_s); + log_assert(l1 < outputs.size()); if (wire) { // Could have been renamed by a latch module->swap_names(wire, outputs[l1]); @@ -297,9 +302,9 @@ end_of_header: goto next; } wire = outputs[l1]; - } - else if (c == 'b') wire = bad_properties[l1]; - else log_abort(); + } else if (c == 'b') { + wire = bad_properties[l1]; + } else log_abort(); module->rename(wire, escaped_s); } @@ -652,6 +657,9 @@ void AigerReader::parse_aiger_binary() unsigned l1, l2, l3; std::string line; + if (M != I + L + A) + log_error("Binary AIGER input is malformed: maximum variable index M is %u, but number of inputs, latches and AND gates adds up to %u.\n", M, I + L + A); + // Parse inputs int digits = decimal_digits(I); for (unsigned i = 1; i <= I; ++i) { diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index d983f8c41..510da0be8 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -110,7 +110,8 @@ struct Xaiger2Frontend : public Frontend { for (int i = 0; i < (int) O; i++) { int po; *f >> po; - log_assert(f->get() == '\n'); + int c = f->get(); + log_assert(c == '\n'); outputs.push_back(po); } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index c26750c98..d9eb51a9c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -844,6 +844,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); set_src_attr(cell, ast); + cell->set_bool_attribute(ID(keep)); for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first); @@ -2084,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) check_unique_id(current_module, id, this, "cell"); RTLIL::Cell *cell = current_module->addCell(id, ""); set_src_attr(cell, this); - // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass - cell->set_bool_attribute(ID::module_not_derived); for (auto it = children.begin(); it != children.end(); it++) { auto* child = it->get(); @@ -2148,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } log_abort(); } + + // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass + if (cell->type.isPublic()) + cell->set_bool_attribute(ID::module_not_derived); + for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) input_error("Attribute `%s' with non-constant value.\n", attr.first); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 83174e963..a5b8c77ac 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -879,7 +879,7 @@ static void check_auto_nosync(AstNode *node) } // remove the attributes we've "consumed" - for (const RTLIL::IdString &str : attrs_to_drop) { + for (RTLIL::IdString str : attrs_to_drop) { auto it = node->attributes.find(str); node->attributes.erase(it); } @@ -4690,6 +4690,7 @@ void AstNode::expand_genblock(const std::string &prefix) switch (child->type) { case AST_WIRE: + case AST_AUTOWIRE: case AST_MEMORY: case AST_STRUCT: case AST_UNION: @@ -4718,6 +4719,93 @@ void AstNode::expand_genblock(const std::string &prefix) } break; + case AST_IDENTIFIER: + if (!child->str.empty() && prefix.size() > 0) { + bool is_resolved = false; + std::string identifier_str = child->str; + if (current_ast_mod != nullptr && identifier_str.compare(0, current_ast_mod->str.size(), current_ast_mod->str) == 0) { + if (identifier_str.at(current_ast_mod->str.size()) == '.') { + identifier_str = '\\' + identifier_str.substr(current_ast_mod->str.size()+1, identifier_str.size()); + } + } + // search starting in the innermost scope and then stepping outward + for (size_t ppos = prefix.size() - 1; ppos; --ppos) { + if (prefix.at(ppos) != '.') continue; + + std::string new_prefix = prefix.substr(0, ppos + 1); + auto attempt_resolve = [&new_prefix](const std::string &ident) -> std::string { + std::string new_name = prefix_id(new_prefix, ident); + if (current_scope.count(new_name)) + return new_name; + return {}; + }; + + // attempt to resolve the full identifier + std::string resolved = attempt_resolve(identifier_str); + if (!resolved.empty()) { + is_resolved = true; + break; + } + // attempt to resolve hierarchical prefixes within the identifier, + // as the prefix could refer to a local scope which exists but + // hasn't yet been elaborated + for (size_t spos = identifier_str.size() - 1; spos; --spos) { + if (identifier_str.at(spos) != '.') continue; + resolved = attempt_resolve(identifier_str.substr(0, spos)); + if (!resolved.empty()) { + is_resolved = true; + identifier_str = resolved + identifier_str.substr(spos); + ppos = 1; // break outer loop + break; + } + } + if (current_scope.count(identifier_str) == 0) { + AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; + for (auto& node : current_scope_ast->children) { + switch (node->type) { + case AST_PARAMETER: + case AST_LOCALPARAM: + case AST_WIRE: + case AST_AUTOWIRE: + case AST_GENVAR: + case AST_MEMORY: + case AST_FUNCTION: + case AST_TASK: + case AST_DPI_FUNCTION: + if (prefix_id(new_prefix, identifier_str) == node->str) { + is_resolved = true; + current_scope[node->str] = node.get(); + } + break; + case AST_ENUM: + current_scope[node->str] = node.get(); + for (auto& enum_node : node->children) { + log_assert(enum_node->type==AST_ENUM_ITEM); + if (prefix_id(new_prefix, identifier_str) == enum_node->str) { + is_resolved = true; + current_scope[enum_node->str] = enum_node.get(); + } + } + break; + default: + break; + } + } + } + } + if ((current_scope.count(identifier_str) == 0) && is_resolved == false) { + if (current_ast_mod == nullptr) { + input_error("Identifier `%s' is implicitly declared outside of a module.\n", child->str.c_str()); + } else if (flag_autowire || identifier_str == "\\$global_clock") { + auto auto_wire = std::make_unique(child->location, AST_AUTOWIRE); + auto_wire->str = identifier_str; + children.push_back(std::move(auto_wire)); + } else { + input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", identifier_str.c_str()); + } + } + } + break; default: break; } diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 0aa3a173d..350d7cafe 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -245,7 +245,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (undef_wire != nullptr) module->rename(undef_wire, stringf("$undef$%d", ++blif_maxnum)); - autoidx = std::max(autoidx, blif_maxnum+1); + autoidx.ensure_at_least(blif_maxnum+1); blif_maxnum = 0; } @@ -470,6 +470,27 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool continue; } + if (!strcmp(cmd, ".gateinit")) + { + char *p = strtok(NULL, " \t\r\n"); + if (p == NULL) + goto error; + + char *n = strtok(p, "="); + char *init = strtok(NULL, "="); + if (n == NULL || init == NULL) + goto error; + if (init[0] != '0' && init[0] != '1') + goto error; + + if (blif_wire(n)->attributes.find(ID::init) == blif_wire(n)->attributes.end()) + blif_wire(n)->attributes.emplace(ID::init, Const(init[0] == '1' ? 1 : 0, 1)); + else + blif_wire(n)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1); + + continue; + } + if (!strcmp(cmd, ".names")) { char *p; @@ -608,6 +629,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto try_next_value; } } + log_assert(i < lutptr->size()); lutptr->set(i, !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1); try_next_value:; } diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 743ac5d9e..803931f32 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -302,6 +302,9 @@ void json_import(Design *design, string &modname, JsonNode *node) if (node->data_dict.count("attributes")) json_parse_attr_param(module->attributes, node->data_dict.at("attributes")); + if (node->data_dict.count("parameter_default_values")) + json_parse_attr_param(module->parameter_default_values, node->data_dict.at("parameter_default_values")); + dict signal_bits; if (node->data_dict.count("ports")) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 80553347c..0aa1cee09 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -40,14 +40,14 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& expr[id_len] == '_' || expr[id_len] == '[' || expr[id_len] == ']') id_len++; if (id_len == 0) - log_error("Expected identifier at `%s'.\n", expr); + log_error("Expected identifier at `%s' in %s.\n", expr, RTLIL::unescape_id(module->name)); if (id_len == 1 && (*expr == '0' || *expr == '1')) return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; std::string id = RTLIL::escape_id(std::string(expr, id_len)); if (!module->wires_.count(id)) - log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id)); + log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), RTLIL::unescape_id(module->name)); expr += id_len; return module->wires_.at(id); @@ -174,7 +174,7 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr) #endif if (stack.size() != 1 || stack.back().type != 3) - log_error("Parser error in function expr `%s'.\n", orig_expr); + log_error("Parser error in function expr `%s'in %s.\n", orig_expr, RTLIL::unescape_id(module->name)); return stack.back().sig; } @@ -191,11 +191,23 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func return cell->getPort(ID::Y); } +static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) +{ + module->addWire(RTLIL::escape_id(node->args.at(0))); + module->addWire(RTLIL::escape_id(node->args.at(1))); +} + +static std::pair find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) +{ + auto* iq_wire = module->wire(RTLIL::escape_id(node->args.at(0))); + auto* iqn_wire = module->wire(RTLIL::escape_id(node->args.at(1))); + log_assert(iq_wire && iqn_wire); + return std::make_pair(iq_wire, iqn_wire); +} + static void create_ff(RTLIL::Module *module, const LibertyAst *node) { - RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0)))); - RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1)))); - + auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node); RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig; bool clk_polarity = true, clear_polarity = true, preset_polarity = true; @@ -211,7 +223,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) } if (clk_sig.size() == 0 || data_sig.size() == 0) - log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", log_id(module->name)); + log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::unescape_id(module->name)); for (bool rerun_invert_rollback = true; rerun_invert_rollback;) { @@ -270,9 +282,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool flag_ignore_miss_data_latch) { - RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0)))); - RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1)))); - + auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node); RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig; bool enable_polarity = true, clear_polarity = true, preset_polarity = true; @@ -289,9 +299,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla if (enable_sig.size() == 0 || data_sig.size() == 0) { if (!flag_ignore_miss_data_latch) - log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name)); + log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::unescape_id(module->name)); else - log("Ignored latch cell %s with no data_in and/or enable attribute.\n", log_id(module->name)); + log("Ignored latch cell %s with no data_in and/or enable attribute.\n", RTLIL::unescape_id(module->name)); return false; } @@ -582,9 +592,9 @@ struct LibertyFrontend : public Frontend { { if (!flag_ignore_miss_dir) { - log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name)); + log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), RTLIL::unescape_id(module->name)); } else { - log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0)); + log("Ignoring cell %s with missing or invalid direction for pin %s.\n", RTLIL::unescape_id(module->name), node->args.at(0)); delete module; goto skip_cell; } @@ -596,13 +606,13 @@ struct LibertyFrontend : public Frontend { if (node->id == "bus" && node->args.size() == 1) { if (flag_ignore_buses) { - log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0)); + log("Ignoring cell %s with a bus interface %s.\n", RTLIL::unescape_id(module->name), node->args.at(0)); delete module; goto skip_cell; } if (!flag_lib) - log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", log_id(cell_name)); + log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", RTLIL::unescape_id(cell_name)); const LibertyAst *dir = node->find("direction"); @@ -613,7 +623,7 @@ struct LibertyFrontend : public Frontend { } if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal")) - log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name)); + log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), RTLIL::unescape_id(module->name)); simple_comb_cell = false; @@ -624,7 +634,7 @@ struct LibertyFrontend : public Frontend { if (!bus_type_node || !type_map.count(bus_type_node->value)) log_error("Unknown or unsupported type for bus interface %s on cell %s.\n", - node->args.at(0).c_str(), log_id(cell_name)); + node->args.at(0).c_str(), RTLIL::unescape_id(cell_name)); int bus_type_width = std::get<0>(type_map.at(bus_type_node->value)); int bus_type_offset = std::get<1>(type_map.at(bus_type_node->value)); @@ -646,6 +656,13 @@ struct LibertyFrontend : public Frontend { { // some liberty files do not put ff/latch at the beginning of a cell // try to find "ff" or "latch" and create FF/latch _before_ processing all other nodes + // but first, in case of balloon retention cells, we need all ff/latch output wires + // defined before we add ff/latch cells + for (auto node : cell->children) + { + if ((node->id == "ff" && node->args.size() == 2) || (node->id == "latch" && node->args.size() == 2)) + create_latch_ff_wires(module, node); + } for (auto node : cell->children) { if (node->id == "ff" && node->args.size() == 2) @@ -701,9 +718,9 @@ struct LibertyFrontend : public Frontend { if (dir->value != "inout") { // allow inout with missing function, can be used for power pins if (!flag_ignore_miss_func) { - log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name)); + log_error("Missing function on output %s of cell %s.\n", RTLIL::unescape_id(wire->name), RTLIL::unescape_id(module->name)); } else { - log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name)); + log("Ignoring cell %s with missing function on output %s.\n", RTLIL::unescape_id(module->name), RTLIL::unescape_id(wire->name)); delete module; goto skip_cell; } @@ -757,13 +774,13 @@ struct LibertyFrontend : public Frontend { if (design->has(cell_name)) { Module *existing_mod = design->module(cell_name); if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { - log_error("Re-definition of cell/module %s!\n", log_id(cell_name)); + log_error("Re-definition of cell/module %s!\n", RTLIL::unescape_id(cell_name)); } else if (flag_nooverwrite) { - log("Ignoring re-definition of module %s.\n", log_id(cell_name)); + log("Ignoring re-definition of module %s.\n", RTLIL::unescape_id(cell_name)); delete module; goto skip_cell; } else { - log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name)); + log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", RTLIL::unescape_id(cell_name)); design->remove(existing_mod); } } diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 271962725..a1412d983 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -40,6 +40,7 @@ struct RTLILFrontendWorker { bool flag_nooverwrite = false; bool flag_overwrite = false; bool flag_lib = false; + bool flag_legalize = false; int line_num; std::string line_buf; @@ -322,6 +323,17 @@ struct RTLILFrontendWorker { return val; } + RTLIL::Wire *legalize_wire(RTLIL::IdString id) + { + int wires_size = current_module->wires_size(); + if (wires_size == 0) + error("No wires found for legalization"); + int hash = hash_ops::hash(id).yield(); + RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size)); + log("Legalizing wire `%s' to `%s'.\n", log_id(id), log_id(wire->name)); + return wire; + } + RTLIL::SigSpec parse_sigspec() { RTLIL::SigSpec sig; @@ -339,8 +351,12 @@ struct RTLILFrontendWorker { std::optional id = try_parse_id(); if (id.has_value()) { RTLIL::Wire *wire = current_module->wire(*id); - if (wire == nullptr) - error("Wire `%s' not found.", *id); + if (wire == nullptr) { + if (flag_legalize) + wire = legalize_wire(*id); + else + error("Wire `%s' not found.", *id); + } sig = RTLIL::SigSpec(wire); } else { sig = RTLIL::SigSpec(parse_const()); @@ -349,17 +365,44 @@ struct RTLILFrontendWorker { while (try_parse_char('[')) { int left = parse_integer(); - if (left >= sig.size() || left < 0) - error("bit index %d out of range", left); + if (left >= sig.size() || left < 0) { + if (flag_legalize) { + int legalized; + if (sig.size() == 0) + legalized = 0; + else + legalized = std::max(0, std::min(left, sig.size() - 1)); + log("Legalizing bit index %d to %d.\n", left, legalized); + left = legalized; + } else { + error("bit index %d out of range", left); + } + } if (try_parse_char(':')) { int right = parse_integer(); - if (right < 0) - error("bit index %d out of range", right); - if (left < right) - error("invalid slice [%d:%d]", left, right); - sig = sig.extract(right, left-right+1); + if (right < 0) { + if (flag_legalize) { + log("Legalizing bit index %d to %d.\n", right, 0); + right = 0; + } else + error("bit index %d out of range", right); + } + if (left < right) { + if (flag_legalize) { + log("Legalizing bit index %d to %d.\n", left, right); + left = right; + } else + error("invalid slice [%d:%d]", left, right); + } + if (flag_legalize && left >= sig.size()) + log("Legalizing slice %d:%d by igoring it\n", left, right); + else + sig = sig.extract(right, left - right + 1); } else { - sig = sig.extract(left); + if (flag_legalize && left >= sig.size()) + log("Legalizing slice %d by igoring it\n", left); + else + sig = sig.extract(left); } expect_char(']'); } @@ -476,8 +519,14 @@ struct RTLILFrontendWorker { { std::optional id = try_parse_id(); if (id.has_value()) { - if (current_module->wire(*id) != nullptr) - error("RTLIL error: redefinition of wire %s.", *id); + if (current_module->wire(*id) != nullptr) { + if (flag_legalize) { + log("Legalizing redefinition of wire %s.\n", *id); + pool wires = {current_module->wire(*id)}; + current_module->remove(wires); + } else + error("RTLIL error: redefinition of wire %s.", *id); + } wire = current_module->addWire(std::move(*id)); break; } @@ -528,8 +577,13 @@ struct RTLILFrontendWorker { { std::optional id = try_parse_id(); if (id.has_value()) { - if (current_module->memories.count(*id) != 0) - error("RTLIL error: redefinition of memory %s.", *id); + if (current_module->memories.count(*id) != 0) { + if (flag_legalize) { + log("Legalizing redefinition of memory %s.\n", *id); + current_module->remove(current_module->memories.at(*id)); + } else + error("RTLIL error: redefinition of memory %s.", *id); + } memory->name = std::move(*id); break; } @@ -551,14 +605,36 @@ struct RTLILFrontendWorker { expect_eol(); } + void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name) + { + std::string width_param_name = port_name.str() + "_WIDTH"; + if (cell->parameters.count(width_param_name) == 0) + return; + RTLIL::Const ¶m = cell->parameters.at(width_param_name); + if (param.as_int() != 0) + return; + cell->parameters[width_param_name] = RTLIL::Const(cell->getPort(port_name).size()); + } + void parse_cell() { RTLIL::IdString cell_type = parse_id(); RTLIL::IdString cell_name = parse_id(); expect_eol(); - if (current_module->cell(cell_name) != nullptr) - error("RTLIL error: redefinition of cell %s.", cell_name); + if (current_module->cell(cell_name) != nullptr) { + if (flag_legalize) { + RTLIL::IdString new_name; + int suffix = 1; + do { + new_name = RTLIL::IdString(cell_name.str() + "_" + std::to_string(suffix)); + ++suffix; + } while (current_module->cell(new_name) != nullptr); + log("Legalizing redefinition of cell %s by renaming to %s.\n", cell_name, new_name); + cell_name = new_name; + } else + error("RTLIL error: redefinition of cell %s.", cell_name); + } RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type); cell->attributes = std::move(attrbuf); @@ -587,9 +663,15 @@ struct RTLILFrontendWorker { expect_eol(); } else if (try_parse_keyword("connect")) { RTLIL::IdString port_name = parse_id(); - if (cell->hasPort(port_name)) - error("RTLIL error: redefinition of cell port %s.", port_name); + if (cell->hasPort(port_name)) { + if (flag_legalize) + log("Legalizing redefinition of cell port %s.", port_name); + else + error("RTLIL error: redefinition of cell port %s.", port_name); + } cell->setPort(std::move(port_name), parse_sigspec()); + if (flag_legalize) + legalize_width_parameter(cell, port_name); expect_eol(); } else if (try_parse_keyword("end")) { expect_eol(); @@ -606,6 +688,11 @@ struct RTLILFrontendWorker { error("dangling attribute"); RTLIL::SigSpec s1 = parse_sigspec(); RTLIL::SigSpec s2 = parse_sigspec(); + if (flag_legalize) { + int min_size = std::min(s1.size(), s2.size()); + s1 = s1.extract(0, min_size); + s2 = s2.extract(0, min_size); + } current_module->connect(std::move(s1), std::move(s2)); expect_eol(); } @@ -682,8 +769,13 @@ struct RTLILFrontendWorker { RTLIL::IdString proc_name = parse_id(); expect_eol(); - if (current_module->processes.count(proc_name) != 0) - error("RTLIL error: redefinition of process %s.", proc_name); + if (current_module->processes.count(proc_name) != 0) { + if (flag_legalize) { + log("Legalizing redefinition of process %s.\n", proc_name); + current_module->remove(current_module->processes.at(proc_name)); + } else + error("RTLIL error: redefinition of process %s.", proc_name); + } RTLIL::Process *proc = current_module->addProcess(std::move(proc_name)); proc->attributes = std::move(attrbuf); @@ -804,6 +896,11 @@ struct RTLILFrontend : public Frontend { log(" -lib\n"); log(" only create empty blackbox modules\n"); log("\n"); + log(" -legalize\n"); + log(" prevent semantic errors (e.g. reference to unknown wire, redefinition of wire/cell)\n"); + log(" by deterministically rewriting the input into something valid. Useful when using\n"); + log(" fuzzing to generate random but valid RTLIL.\n"); + log("\n"); } void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -828,6 +925,10 @@ struct RTLILFrontend : public Frontend { worker.flag_lib = true; continue; } + if (arg == "-legalize") { + worker.flag_legalize = true; + continue; + } break; } extra_args(f, filename, args, argidx); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5790e92f0..6a1c81aa4 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3114,9 +3114,11 @@ struct VerificPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} ..\n"); + log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|\n"); + log(" -sv2017|-sv} ..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n"); + log("Note that -sv option will use latest supported SystemVerilog standard.\n"); log("\n"); log("All files specified in one call to this command are one compilation unit.\n"); log("Files passed to different calls to this command are treated as belonging to\n"); @@ -3161,7 +3163,10 @@ struct VerificPass : public Pass { #endif #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n"); - log(" -sv2012|-sv|-formal] \n"); +#ifdef VERIFIC_VHDL_SUPPORT + log(" -vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl|\n"); +#endif + log(" -sv2012|-sv2017|-sv|-formal] \n"); log("\n"); log("Load and execute the specified command file.\n"); log("Override verilog parsing mode can be set.\n"); @@ -3696,6 +3701,9 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; +#ifdef VERIFIC_VHDL_SUPPORT + unsigned vhdl_mode = vhdl_file::UNDEFINED; +#endif bool is_formal = false; const char* filename = nullptr; @@ -3714,10 +3722,38 @@ struct VerificPass : public Pass { } else if (args[argidx] == "-sv2009") { verilog_mode = veri_file::SYSTEM_VERILOG_2009; continue; - } else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") { + } else if (args[argidx] == "-sv2012") { + verilog_mode = veri_file::SYSTEM_VERILOG_2012; + continue; + } else if (args[argidx] == "-sv2017") { + verilog_mode = veri_file::SYSTEM_VERILOG_2017; + continue; + } else if (args[argidx] == "-sv" || args[argidx] == "-formal") { verilog_mode = veri_file::SYSTEM_VERILOG; if (args[argidx] == "-formal") is_formal = true; continue; +#ifdef VERIFIC_VHDL_SUPPORT + } else if (args[argidx] == "-vhdl87") { + vhdl_mode = vhdl_file::VHDL_87; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); + continue; + } else if (args[argidx] == "-vhdl93") { + vhdl_mode = vhdl_file::VHDL_93; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); + continue; + } else if (args[argidx] == "-vhdl2k") { + vhdl_mode = vhdl_file::VHDL_2K; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); + continue; + } else if (args[argidx] == "-vhdl2019") { + vhdl_mode = vhdl_file::VHDL_2019; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); + continue; + } else if (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl") { + vhdl_mode = vhdl_file::VHDL_2008; + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); + continue; +#endif } else if (args[argidx].compare(0, 1, "-") == 0) { cmd_error(args, argidx, "unknown option"); goto check_error; @@ -3742,10 +3778,36 @@ struct VerificPass : public Pass { veri_file::DefineMacro("VERIFIC"); veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS"); +#ifdef VERIFIC_VHDL_SUPPORT + if (vhdl_mode == vhdl_file::UNDEFINED) { + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); + vhdl_mode = vhdl_file::VHDL_2008; + } + int i; + Array *file_names_sv = new Array(POINTER_HASH); + FOREACH_ARRAY_ITEM(file_names, i, filename) { + std::string filename_str = filename; + if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || + (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { + if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_mode)) { + verific_error_msg.clear(); + log_cmd_error("Reading VHDL sources failed.\n"); + } + } else { + file_names_sv->Insert(strdup(filename)); + } + } + if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + delete file_names_sv; +#else if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } +#endif delete file_names; verific_import_pending = true; @@ -3753,7 +3815,8 @@ struct VerificPass : public Pass { } if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || - args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")) + args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv2017" || args[argidx] == "-sv" || + args[argidx] == "-formal")) { Array file_names; unsigned verilog_mode; @@ -3766,7 +3829,11 @@ struct VerificPass : public Pass { verilog_mode = veri_file::SYSTEM_VERILOG_2005; else if (args[argidx] == "-sv2009") verilog_mode = veri_file::SYSTEM_VERILOG_2009; - else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") + else if (args[argidx] == "-sv2012") + verilog_mode = veri_file::SYSTEM_VERILOG_2012; + else if (args[argidx] == "-sv2017") + verilog_mode = veri_file::SYSTEM_VERILOG_2017; + else if (args[argidx] == "-sv" || args[argidx] == "-formal") verilog_mode = veri_file::SYSTEM_VERILOG; else log_abort(); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index dffe6e8e0..c2cfe7e75 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1846,7 +1846,10 @@ struct VerificSvaImporter if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q); if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q); - if (c) importer->import_attributes(c->attributes, root); + if (c) { + c->set_bool_attribute(ID(keep)); + importer->import_attributes(c->attributes, root); + } } } catch (ParserErrorException) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 6c9e67dc5..29a739f81 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -500,7 +500,6 @@ struct VerilogFrontend : public Frontend { log("Parsing %s%s input from `%s' to AST representation.\n", parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); - log("verilog frontend filename %s\n", filename.c_str()); if (flag_relative_share) { auto share_path = proc_share_dirname(); if (filename.substr(0, share_path.length()) == share_path) diff --git a/kernel/calc.cc b/kernel/calc.cc index 9b0885db9..84ac100ab 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -291,7 +291,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co if (pos < 0) result.set(i, vacant_bits); else if (pos >= BigInteger(GetSize(arg1))) - result.set(i, sign_ext ? arg1.back() : vacant_bits); + result.set(i, sign_ext && !arg1.empty() ? arg1.back() : vacant_bits); else result.set(i, arg1[pos.toInt()]); } diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index fd3c7bb67..0f897cd58 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -185,50 +185,68 @@ struct AigMaker int or_gate(int A, int B) { - return nand_gate(not_gate(A), not_gate(B)); + int not_a = not_gate(A); + int not_b = not_gate(B); + return nand_gate(not_a, not_b); } int nor_gate(int A, int B) { - return and_gate(not_gate(A), not_gate(B)); + int not_a = not_gate(A); + int not_b = not_gate(B); + return and_gate(not_a, not_b); } int xor_gate(int A, int B) { - return nor_gate(and_gate(A, B), nor_gate(A, B)); + int a_and_b = and_gate(A, B); + int a_nor_b = nor_gate(A, B); + return nor_gate(a_and_b, a_nor_b); } int xnor_gate(int A, int B) { - return or_gate(and_gate(A, B), nor_gate(A, B)); + int a_and_b = and_gate(A, B); + int a_nor_b = nor_gate(A, B); + return or_gate(a_and_b, a_nor_b); } int andnot_gate(int A, int B) { - return and_gate(A, not_gate(B)); + int not_b = not_gate(B); + return and_gate(A, not_b); } int ornot_gate(int A, int B) { - return or_gate(A, not_gate(B)); + int not_b = not_gate(B); + return or_gate(A, not_b); } int mux_gate(int A, int B, int S) { - return or_gate(and_gate(A, not_gate(S)), and_gate(B, S)); + int not_s = not_gate(S); + int a_active = and_gate(A, not_s); + int b_active = and_gate(B, S); + return or_gate(a_active, b_active); } - vector adder(const vector &A, const vector &B, int carry, vector *X = nullptr, vector *CO = nullptr) + vector adder(const vector &A, const vector &B, int carry_in, vector *X = nullptr, vector *CO = nullptr) { vector Y(GetSize(A)); log_assert(GetSize(A) == GetSize(B)); for (int i = 0; i < GetSize(A); i++) { - Y[i] = xor_gate(xor_gate(A[i], B[i]), carry); - carry = or_gate(and_gate(A[i], B[i]), and_gate(or_gate(A[i], B[i]), carry)); + int a_xor_b = xor_gate(A[i], B[i]); + int a_or_b = or_gate(A[i], B[i]); + int a_and_b = and_gate(A[i], B[i]); + Y[i] = xor_gate(a_xor_b, carry_in); + int tmp = and_gate(a_or_b, carry_in); + int carry_out = or_gate(a_and_b, tmp); if (X != nullptr) - X->at(i) = xor_gate(A[i], B[i]); + X->at(i) = a_xor_b; if (CO != nullptr) - CO->at(i) = carry; + CO->at(i) = carry_out; + carry_in = carry_out; } return Y; } @@ -307,13 +325,13 @@ Aig::Aig(Cell *cell) int A = mk.inport(ID::A, i); int B = mk.inport(ID::B, i); int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) : - cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) : + cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) : cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) : - cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) : + cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) : cell->type.in(ID($xor), ID($_XOR_)) ? mk.xor_gate(A, B) : cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) : - cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) : - cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1; + cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) : + cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1; mk.outport(Y, ID::Y, i); } goto optimize; @@ -465,7 +483,8 @@ Aig::Aig(Cell *cell) int B = mk.inport(ID::B); int C = mk.inport(ID::C); int D = mk.inport(ID::D); - int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D)); + int a_and_b = mk.and_gate(A, B); + int Y = mk.nor_gate(a_and_b, mk.and_gate(C, D)); mk.outport(Y, ID::Y); goto optimize; } @@ -476,7 +495,8 @@ Aig::Aig(Cell *cell) int B = mk.inport(ID::B); int C = mk.inport(ID::C); int D = mk.inport(ID::D); - int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); + int a_or_b = mk.or_gate(A, B); + int Y = mk.nand_gate(a_or_b, mk.or_gate(C, D)); mk.outport(Y, ID::Y); goto optimize; } diff --git a/kernel/celledges.cc b/kernel/celledges.cc index c39ced95a..195d4b15b 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -112,6 +112,41 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) db->add_edge(cell, ID::A, i, ID::Y, 0, -1); } +void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + + for (int i = 0; i < a_width; i++) + db->add_edge(cell, ID::A, i, ID::Y, 0, -1); + for (int i = 0; i < b_width; i++) + db->add_edge(cell, ID::B, i, ID::Y, 0, -1); +} + +void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + + for (int i = 0; i < a_width; i++) + db->add_edge(cell, ID::A, i, ID::Y, i, -1); + for (int i = 0; i < b_width; i++) + db->add_edge(cell, ID::B, i, ID::Y, a_width + i, -1); +} + +void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int offset = cell->getParam(ID::OFFSET).as_int(); + int a_width = GetSize(cell->getPort(ID::A)); + int y_width = GetSize(cell->getPort(ID::Y)); + + for (int i = 0; i < y_width; i++) { + int a_bit = offset + i; + if (a_bit >= 0 && a_bit < a_width) + db->add_edge(cell, ID::A, a_bit, ID::Y, i, -1); + } +} + void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { int a_width = GetSize(cell->getPort(ID::A)); @@ -254,7 +289,7 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int skip = 1 << (k + 1); int base = skip -1; if (i % skip != base && i - a_width + 2 < 1 << b_width_capped) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, ID::B, k, ID::Y, i, -1); } else if (is_signed) { if (i - a_width + 2 < 1 << b_width_capped) db->add_edge(cell, ID::B, k, ID::Y, i, -1); @@ -388,6 +423,64 @@ void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1); } +void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + std::vector input_ports; + std::vector output_ports; + + for (auto &conn : cell->connections()) + { + RTLIL::IdString port = conn.first; + RTLIL::PortDir dir = cell->port_dir(port); + if (cell->input(port) || dir == RTLIL::PortDir::PD_INOUT) + input_ports.push_back(port); + if (cell->output(port) || dir == RTLIL::PortDir::PD_INOUT) + output_ports.push_back(port); + } + + for (auto out_port : output_ports) + { + int out_width = GetSize(cell->getPort(out_port)); + for (int out_bit = 0; out_bit < out_width; out_bit++) + { + for (auto in_port : input_ports) + { + int in_width = GetSize(cell->getPort(in_port)); + for (int in_bit = 0; in_bit < in_width; in_bit++) + db->add_edge(cell, in_port, in_bit, out_port, out_bit, -1); + } + } + } +} + +void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int max_width = std::min(width, std::min(a_width, b_width)); + + for (int i = 0; i < max_width; i++) { + db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, ID::B, i, ID::Y, i, -1); + } +} + +void bwmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + int width = GetSize(cell->getPort(ID::Y)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int s_width = GetSize(cell->getPort(ID::S)); + int max_width = std::min(width, std::min(a_width, std::min(b_width, s_width))); + + for (int i = 0; i < max_width; i++) { + db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, ID::B, i, ID::Y, i, -1); + db->add_edge(cell, ID::S, i, ID::Y, i, -1); + } +} + PRIVATE_NAMESPACE_END bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) @@ -417,6 +510,21 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } + if (cell->type.in(ID($logic_and), ID($logic_or))) { + logic_op(this, cell); + return true; + } + + if (cell->type == ID($slice)) { + slice_op(this, cell); + return true; + } + + if (cell->type == ID($concat)) { + concat_op(this, cell); + return true; + } + if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { shift_op(this, cell); return true; @@ -442,6 +550,16 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } + if (cell->type == ID($bweqx)) { + bweqx_op(this, cell); + return true; + } + + if (cell->type == ID($bwmux)) { + bwmux_op(this, cell); + return true; + } + if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) { mem_op(this, cell); return true; @@ -452,13 +570,24 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } - // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat - // FIXME: $lut $sop $alu $lcu $macc $macc_v2 $fa - // FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx - // FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux + if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) { + full_op(this, cell); + return true; + } - // FIXME: $_BUF_ $_NOT_ $_AND_ $_NAND_ $_OR_ $_NOR_ $_XOR_ $_XNOR_ $_ANDNOT_ $_ORNOT_ - // FIXME: $_MUX_ $_NMUX_ $_MUX4_ $_MUX8_ $_MUX16_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ + if (cell->type.in(ID($lut), ID($sop), ID($alu), ID($lcu), ID($macc), ID($macc_v2))) { + full_op(this, cell); + return true; + } + + if (cell->type.in( + ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), + ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), + ID($_MUX4_), ID($_MUX8_), ID($_MUX16_), ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), + ID($_OAI4_), ID($_TBUF_))) { + full_op(this, cell); + return true; + } // FIXME: $specify2 $specify3 $specrule ??? // FIXME: $equiv $set_tag $get_tag $overwrite_tag $original_tag @@ -468,4 +597,3 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return false; } - diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 2d53f5a87..c03cbdcc3 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -305,18 +305,18 @@ struct CellTypes cell_types.clear(); } - bool cell_known(const RTLIL::IdString &type) const + bool cell_known(RTLIL::IdString type) const { return cell_types.count(type) != 0; } - bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const + bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const + bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; @@ -332,7 +332,7 @@ struct CellTypes return RTLIL::PortDir(is_input + is_output * 2); } - bool cell_evaluable(const RTLIL::IdString &type) const + bool cell_evaluable(RTLIL::IdString type) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.is_evaluable; diff --git a/kernel/consteval.h b/kernel/consteval.h index 82169f31e..d00ae8f33 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -28,6 +28,10 @@ YOSYS_NAMESPACE_BEGIN +/** + * ConstEval provides on-demand constant propagation by traversing input cones + * with caching + */ struct ConstEval { RTLIL::Module *module; diff --git a/kernel/driver.cc b/kernel/driver.cc index 4097411b4..fa78bad59 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -255,6 +255,7 @@ int main(int argc, char **argv) ("h,help", "print this help message. If given, print help for .", cxxopts::value(), "[]") ("V,version", "print version information and exit") + ("git-hash", "print git commit hash and exit") ("infile", "input files", cxxopts::value>()) ; options.add_options("logging") @@ -332,6 +333,10 @@ int main(int argc, char **argv) std::cout << yosys_version_str << std::endl; exit(0); } + if (result.count("git-hash")) { + std::cout << yosys_git_hash_str << std::endl; + exit(0); + } if (result.count("S")) { passes_commands.push_back("synth"); run_shell = false; @@ -764,33 +769,6 @@ int main(int argc, char **argv) } } -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) - if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) - { - string filename; - FILE *f; - - if (getenv("YOSYS_COVER_DIR")) { - filename = stringf("%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid()); - filename = make_temp_file(filename); - } else { - filename = getenv("YOSYS_COVER_FILE"); - } - - f = fopen(filename.c_str(), "a+"); - - if (f == NULL) - log_error("Can't create coverage file `%s'.\n", filename); - - log("\n", filename); - - for (auto &it : get_coverage_data()) - fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); - - fclose(f); - } -#endif - log_check_expected(); yosys_atexit(); diff --git a/kernel/hashlib.h b/kernel/hashlib.h index ca600231a..b43a68abf 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -1321,6 +1321,12 @@ public: return i < 0 ? 0 : 1; } + int lookup(const K &key) const + { + Hasher::hash_t hash = database.do_hash(key); + return database.do_lookup_no_rehash(key, hash); + } + void expect(const K &key, int i) { int j = (*this)(key); diff --git a/kernel/io.cc b/kernel/io.cc index 4f805e43b..078fa139c 100644 --- a/kernel/io.cc +++ b/kernel/io.cc @@ -602,7 +602,7 @@ void format_emit_string_view(std::string &result, std::string_view spec, int *dy } void format_emit_idstring(std::string &result, std::string_view spec, int *dynamic_ints, - DynamicIntCount num_dynamic_ints, const IdString &arg) + DynamicIntCount num_dynamic_ints, const RTLIL::IdString &arg) { if (spec == "%s") { // Format checking will have guaranteed num_dynamic_ints == 0. diff --git a/kernel/log.cc b/kernel/log.cc index 34e56f8ac..018a19081 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -90,11 +90,11 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) QueryPerformanceFrequency(&freq); QueryPerformanceCounter(&counter); - counter.QuadPart *= 1000000; + counter.QuadPart *= 1'000'000; counter.QuadPart /= freq.QuadPart; tv->tv_sec = long(counter.QuadPart / 1000000); - tv->tv_usec = counter.QuadPart % 1000000; + tv->tv_usec = counter.QuadPart % 1'000'000; return 0; } @@ -135,7 +135,7 @@ static void logv_string(std::string_view format, std::string str) { initial_tv = tv; if (tv.tv_usec < initial_tv.tv_usec) { tv.tv_sec--; - tv.tv_usec += 1000000; + tv.tv_usec += 1'000'000; } tv.tv_sec -= initial_tv.tv_sec; tv.tv_usec -= initial_tv.tv_usec; @@ -203,6 +203,8 @@ static void logv_string(std::string_view format, std::string str) { void log_formatted_string(std::string_view format, std::string str) { + log_assert(!Multithreading::active()); + if (log_make_debug && !ys_debug(1)) return; logv_string(format, std::move(str)); @@ -210,6 +212,8 @@ void log_formatted_string(std::string_view format, std::string str) void log_formatted_header(RTLIL::Design *design, std::string_view format, std::string str) { + log_assert(!Multithreading::active()); + bool pop_errfile = false; log_spacer(); @@ -249,6 +253,8 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s void log_formatted_warning(std::string_view prefix, std::string message) { + log_assert(!Multithreading::active()); + bool suppressed = false; for (auto &re : log_nowarn_regexes) @@ -681,55 +687,4 @@ void log_check_expected() check_err("prefixed error", pattern, item); } -// --------------------------------------------------- -// This is the magic behind the code coverage counters -// --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) - -dict> extra_coverage_data; - -void cover_extra(std::string parent, std::string id, bool increment) { - if (extra_coverage_data.count(id) == 0) { - for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) - if (p->id == parent) - extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func); - log_assert(extra_coverage_data.count(id)); - } - if (increment) - extra_coverage_data[id].second++; -} - -dict> get_coverage_data() -{ - dict> coverage_data; - - for (auto &it : pass_register) { - std::string key = stringf("passes.%s", it.first); - coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__); - coverage_data[key].second += it.second->call_counter; - } - - for (auto &it : extra_coverage_data) { - if (coverage_data.count(it.first)) - log_warning("found duplicate coverage id \"%s\".\n", it.first); - coverage_data[it.first].first = it.second.first; - coverage_data[it.first].second += it.second.second; - } - - for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { - if (coverage_data.count(p->id)) - log_warning("found duplicate coverage id \"%s\".\n", p->id); - coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); - coverage_data[p->id].second += p->counter; - } - - for (auto &it : coverage_data) - if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/")) - it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/")); - - return coverage_data; -} - -#endif - YOSYS_NAMESPACE_END diff --git a/kernel/log.h b/kernel/log.h index 144570026..63faf7091 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -24,6 +24,7 @@ #include +#include #include #define YS_REGEX_COMPILE(param) std::regex(param, \ std::regex_constants::nosubs | \ @@ -290,53 +291,6 @@ void log_abort_internal(const char *file, int line); #define log_ping() YOSYS_NAMESPACE_PREFIX log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__) -// --------------------------------------------------- -// This is the magic behind the code coverage counters -// --------------------------------------------------- - -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) - -#define cover(_id) do { \ - static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ - __d.counter++; \ -} while (0) - -struct CoverData { - const char *file, *func, *id; - int line, counter; -} YS_ATTRIBUTE(packed); - -// this two symbols are created by the linker for the "yosys_cover_list" ELF section -extern "C" struct CoverData __start_yosys_cover_list[]; -extern "C" struct CoverData __stop_yosys_cover_list[]; - -extern dict> extra_coverage_data; - -void cover_extra(std::string parent, std::string id, bool increment = true); -dict> get_coverage_data(); - -#define cover_list(_id, ...) do { cover(_id); \ - std::string r = cover_list_worker(_id, __VA_ARGS__); \ - log_assert(r.empty()); \ -} while (0) - -static inline std::string cover_list_worker(std::string, std::string last) { - return last; -} - -template -std::string cover_list_worker(std::string prefix, std::string first, T... rest) { - std::string selected = cover_list_worker(prefix, rest...); - cover_extra(prefix, prefix + "." + first, first == selected); - return first == selected ? "" : selected; -} - -#else -# define cover(...) do { } while (0) -# define cover_list(...) do { } while (0) -#endif - - // ------------------------------------------------------------ // everything below this line are utilities for troubleshooting // ------------------------------------------------------------ diff --git a/kernel/log_help.cc b/kernel/log_help.cc index 93b91b08b..01c9a93f6 100644 --- a/kernel/log_help.cc +++ b/kernel/log_help.cc @@ -78,7 +78,7 @@ ContentListing* ContentListing::open_option(const string &text, } #define MAX_LINE_LEN 80 -void log_pass_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false) { +void log_body_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false, bool is_formatted=false) { if (pass_str.empty()) return; std::istringstream iss(pass_str); @@ -86,26 +86,30 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead log("\n"); for (std::string line; std::getline(iss, line);) { log("%s", indent_str); - auto curr_len = indent_str.length(); - std::istringstream lss(line); - for (std::string word; std::getline(lss, word, ' ');) { - while (word[0] == '`' && word.back() == '`') - word = word.substr(1, word.length()-2); - if (curr_len + word.length() >= MAX_LINE_LEN-1) { - curr_len = 0; - log("\n%s", indent_str); - } - if (word.length()) { - log("%s ", word); - curr_len += word.length() + 1; + if (is_formatted) { + log("%s", line); + } else { + auto curr_len = indent_str.length(); + std::istringstream lss(line); + for (std::string word; std::getline(lss, word, ' ');) { + while (word[0] == '`' && word.back() == '`') + word = word.substr(1, word.length()-2); + if (curr_len + word.length() >= MAX_LINE_LEN-1) { + curr_len = 0; + log("\n%s", indent_str); + } + if (word.length()) { + log("%s ", word); + curr_len += word.length() + 1; + } } } log("\n"); } } -void log_pass_str(const std::string &pass_str, int indent=0, bool leading_newline=false) { +void log_body(const ContentListing &content, int indent=0, bool leading_newline=false) { std::string indent_str(indent*4, ' '); - log_pass_str(pass_str, indent_str, leading_newline); + log_body_str(content.body, indent_str, leading_newline, content.type.compare("code") == 0); } PrettyHelp *current_help = nullptr; @@ -134,16 +138,16 @@ void PrettyHelp::log_help() const { for (auto &content : _root_listing) { if (content.type.compare("usage") == 0) { - log_pass_str(content.body, 1, true); + log_body(content, 1, true); log("\n"); } else if (content.type.compare("option") == 0) { - log_pass_str(content.body, 1); + log_body(content, 1); for (auto text : content) { - log_pass_str(text.body, 2); + log_body(text, 2); log("\n"); } } else { - log_pass_str(content.body, 0); + log_body(content, 0); log("\n"); } } diff --git a/kernel/modtools.h b/kernel/modtools.h index 4be32a806..193269687 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -29,6 +29,22 @@ YOSYS_NAMESPACE_BEGIN struct ModIndex : public RTLIL::Monitor { + struct PointerOrderedSigBit : public RTLIL::SigBit { + PointerOrderedSigBit(SigBit s) { + wire = s.wire; + if (wire) + offset = s.offset; + else + data = s.data; + } + inline bool operator<(const RTLIL::SigBit &other) const { + if (wire == other.wire) + return wire ? (offset < other.offset) : (data < other.data); + if (wire != nullptr && other.wire != nullptr) + return wire < other.wire; // look here + return (wire != nullptr) < (other.wire != nullptr); + } + }; struct PortInfo { RTLIL::Cell* cell; RTLIL::IdString port; @@ -78,7 +94,7 @@ struct ModIndex : public RTLIL::Monitor SigMap sigmap; RTLIL::Module *module; - std::map database; + std::map database; int auto_reload_counter; bool auto_reload_module; @@ -95,8 +111,11 @@ struct ModIndex : public RTLIL::Monitor { for (int i = 0; i < GetSize(sig); i++) { RTLIL::SigBit bit = sigmap(sig[i]); - if (bit.wire) + if (bit.wire) { database[bit].ports.erase(PortInfo(cell, port, i)); + if (!database[bit].is_input && !database[bit].is_output && database[bit].ports.empty()) + database.erase(bit); + } } } @@ -133,11 +152,11 @@ struct ModIndex : public RTLIL::Monitor } } - void check() + bool ok() { #ifndef NDEBUG if (auto_reload_module) - return; + return true; for (auto it : database) log_assert(it.first == sigmap(it.first)); @@ -157,12 +176,18 @@ struct ModIndex : public RTLIL::Monitor else if (!(it.second == database_bak.at(it.first))) log("ModuleIndex::check(): Different content for database[%s].\n", log_signal(it.first)); - log_assert(database == database_bak); + return false; } + return true; #endif } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override + void check() + { + log_assert(ok()); + } + + void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log_assert(module == cell->module); diff --git a/kernel/pattern.h b/kernel/pattern.h new file mode 100644 index 000000000..bb794e9fa --- /dev/null +++ b/kernel/pattern.h @@ -0,0 +1,102 @@ +#ifndef OPT_DFF_COMP_H +#define OPT_DFF_COMP_H + +#include "kernel/rtlil.h" +#include +#include + +YOSYS_NAMESPACE_BEGIN + +/** + * Pattern matching utilities for control signal analysis. + * + * A pattern_t maps control signals to required values, representing a + * product term (conjunction): {A=1, B=0} means "A AND !B". + * + * A patterns_t is a set of patterns representing a sum-of-products: + * {{A=1, B=0}, {A=0, C=1}} means "(A AND !B) OR (!A AND C)". + * + * Used for analyzing MUX tree control paths in DFF optimization. + */ + +// Pattern matching for clock enable +// A pattern maps control signals to their required values for a MUX path +typedef std::map pattern_t; // Set of control signals that must ALL match required vals +typedef std::set patterns_t; // Alternative patterns (OR) +typedef std::pair ctrl_t; // Control signal +typedef std::set ctrls_t; // Set of control signals that must ALL be active + +/** + * Find if two patterns differ in exactly one variable. + * Example: {A=1,B=1} vs {A=1,B=0} returns B, allows simplification: (A&B) | (A&!B) => A + */ +inline std::optional find_complementary_pattern_var( + const pattern_t& left, + const pattern_t& right +) { + std::optional ret; + for (const auto &pt : left) { + // Left requires signal that right doesn't constrain - incompatible domains + if (right.count(pt.first) == 0) + return std::nullopt; + // Signal has same required value in both - not the complement variable + if (right.at(pt.first) == pt.second) + continue; + // Already found one differing signal, now found another - not simplifiable + if (ret) + return std::nullopt; + // First differing signal - candidate complement variable + ret = pt.first; + } + return ret; +} + +/** + * Simplify a sum-of-products by merging complementary patterns: (A&B) | (A&!B) => A, + * and removing redundant patterns: A | (A&B) => A + */ +inline void simplify_patterns(patterns_t& patterns) { + auto new_patterns = patterns; + + // Merge complementary patterns + bool optimized; + do { + optimized = false; + for (auto i = patterns.begin(); i != patterns.end(); i++) { + for (auto j = std::next(i, 1); j != patterns.end(); j++) { + const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; + auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; + const auto complementary_var = find_complementary_pattern_var(left, right); + + if (complementary_var && new_patterns.count(right)) { + new_patterns.erase(right); + right.erase(complementary_var.value()); + new_patterns.insert(right); + optimized = true; + } + } + } + patterns = new_patterns; + } while(optimized); + + // Remove redundant patterns + for (auto i = patterns.begin(); i != patterns.end(); ++i) { + for (auto j = std::next(i, 1); j != patterns.end(); ++j) { + const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; + const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i; + bool redundant = true; + + for (const auto& pt : left) + if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second) + redundant = false; + if (redundant) + new_patterns.erase(right); + } + } + + patterns = std::move(new_patterns); +} + +YOSYS_NAMESPACE_END + +#endif diff --git a/kernel/register.cc b/kernel/register.cc index 00cd27383..cba6d5f99 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -1207,7 +1207,7 @@ struct LicensePass : public Pass { log(" | |\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); log(" | |\n"); - log(" | Copyright (C) 2012 - 2025 Claire Xenia Wolf |\n"); + log(" | Copyright (C) 2012 - 2026 Claire Xenia Wolf |\n"); log(" | |\n"); log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); log(" | purpose with or without fee is hereby granted, provided that the above |\n"); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 54fff829c..61dac3313 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -31,6 +31,7 @@ #include #include #include +#include YOSYS_NAMESPACE_BEGIN @@ -38,12 +39,9 @@ bool RTLIL::IdString::destruct_guard_ok = false; RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard; std::vector RTLIL::IdString::global_id_storage_; std::unordered_map RTLIL::IdString::global_id_index_; -std::unordered_map RTLIL::IdString::global_autoidx_id_prefix_storage_; -std::unordered_map RTLIL::IdString::global_autoidx_id_storage_; -#ifndef YOSYS_NO_IDS_REFCNT +std::unordered_map RTLIL::IdString::global_autoidx_id_storage_; std::unordered_map RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_free_idx_list_; -#endif static void populate(std::string_view name) { @@ -95,16 +93,16 @@ int RTLIL::IdString::really_insert(std::string_view p, std::unordered_map p_autoidx = parse_autoidx(p.substr(autoidx_pos)); if (p_autoidx.has_value()) { - auto prefix_it = global_autoidx_id_prefix_storage_.find(-*p_autoidx); - if (prefix_it != global_autoidx_id_prefix_storage_.end() && p.substr(0, autoidx_pos) == *prefix_it->second) + auto autoidx_it = global_autoidx_id_storage_.find(-*p_autoidx); + if (autoidx_it != global_autoidx_id_storage_.end() && + p.substr(0, autoidx_pos) == *autoidx_it->second.prefix) return -*p_autoidx; // Ensure NEW_ID/NEW_ID_SUFFIX will not create collisions with the ID // we're about to create. - autoidx = std::max(autoidx, *p_autoidx + 1); + autoidx.ensure_at_least(*p_autoidx + 1); } } -#ifndef YOSYS_NO_IDS_REFCNT if (global_free_idx_list_.empty()) { log_assert(global_id_storage_.size() < 0x40000000); global_free_idx_list_.push_back(global_id_storage_.size()); @@ -113,10 +111,6 @@ int RTLIL::IdString::really_insert(std::string_view p, std::unordered_map(malloc(p.size() + 1)); memcpy(buf, p.data(), p.size()); buf[p.size()] = 0; @@ -192,7 +186,7 @@ struct IdStringCollector { trace(selection_var.selected_modules); trace(selection_var.selected_members); } - void trace_named(const RTLIL::NamedObject named) { + void trace_named(const RTLIL::NamedObject &named) { trace_keys(named.attributes); trace(named.name); } @@ -249,7 +243,6 @@ int RTLIL::OwningIdString::gc_count; void RTLIL::OwningIdString::collect_garbage() { int64_t start = PerformanceTimer::query(); -#ifndef YOSYS_NO_IDS_REFCNT IdStringCollector collector; for (auto &[idx, design] : *RTLIL::Design::get_all_designs()) { collector.trace(*design); @@ -275,7 +268,7 @@ void RTLIL::OwningIdString::collect_garbage() global_free_idx_list_.push_back(i); } - for (auto it = global_autoidx_id_prefix_storage_.begin(); it != global_autoidx_id_prefix_storage_.end();) { + for (auto it = global_autoidx_id_storage_.begin(); it != global_autoidx_id_storage_.end();) { if (collector.live.find(it->first) != collector.live.end()) { ++it; continue; @@ -284,14 +277,9 @@ void RTLIL::OwningIdString::collect_garbage() ++it; continue; } - auto str_it = global_autoidx_id_storage_.find(it->first); - if (str_it != global_autoidx_id_storage_.end()) { - delete[] str_it->second; - global_autoidx_id_storage_.erase(str_it); - } - it = global_autoidx_id_prefix_storage_.erase(it); + it = global_autoidx_id_storage_.erase(it); } -#endif + int64_t time_ns = PerformanceTimer::query() - start; Pass::subtract_from_current_runtime_ns(time_ns); gc_ns += time_ns; @@ -897,8 +885,6 @@ RTLIL::State RTLIL::Const::const_iterator::operator*() const { bool RTLIL::Const::is_fully_zero() const { - cover("kernel.rtlil.const.is_fully_zero"); - if (auto str = get_if_str()) { for (char ch : *str) if (ch != 0) @@ -917,8 +903,6 @@ bool RTLIL::Const::is_fully_zero() const bool RTLIL::Const::is_fully_ones() const { - cover("kernel.rtlil.const.is_fully_ones"); - if (auto str = get_if_str()) { for (char ch : *str) if (ch != (char)0xff) @@ -936,8 +920,6 @@ bool RTLIL::Const::is_fully_ones() const bool RTLIL::Const::is_fully_def() const { - cover("kernel.rtlil.const.is_fully_def"); - if (is_str()) return true; @@ -951,8 +933,6 @@ bool RTLIL::Const::is_fully_def() const bool RTLIL::Const::is_fully_undef() const { - cover("kernel.rtlil.const.is_fully_undef"); - if (auto str = get_if_str()) return str->empty(); @@ -966,8 +946,6 @@ bool RTLIL::Const::is_fully_undef() const bool RTLIL::Const::is_fully_undef_x_only() const { - cover("kernel.rtlil.const.is_fully_undef_x_only"); - if (auto str = get_if_str()) return str->empty(); @@ -981,8 +959,6 @@ bool RTLIL::Const::is_fully_undef_x_only() const bool RTLIL::Const::is_onehot(int *pos) const { - cover("kernel.rtlil.const.is_onehot"); - bool found = false; int size = GetSize(*this); for (int i = 0; i < size; i++) { @@ -1043,12 +1019,12 @@ RTLIL::Const RTLIL::Const::extract(int offset, int len, RTLIL::State padding) co } #undef check /* check(condition) for Const */ -bool RTLIL::AttrObject::has_attribute(const RTLIL::IdString &id) const +bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const { return attributes.count(id); } -void RTLIL::AttrObject::set_bool_attribute(const RTLIL::IdString &id, bool value) +void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value) { if (value) attributes[id] = RTLIL::Const(1); @@ -1056,7 +1032,7 @@ void RTLIL::AttrObject::set_bool_attribute(const RTLIL::IdString &id, bool value attributes.erase(id); } -bool RTLIL::AttrObject::get_bool_attribute(const RTLIL::IdString &id) const +bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const { const auto it = attributes.find(id); if (it == attributes.end()) @@ -1064,7 +1040,7 @@ bool RTLIL::AttrObject::get_bool_attribute(const RTLIL::IdString &id) const return it->second.as_bool(); } -void RTLIL::AttrObject::set_string_attribute(const RTLIL::IdString& id, string value) +void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value) { if (value.empty()) attributes.erase(id); @@ -1072,7 +1048,7 @@ void RTLIL::AttrObject::set_string_attribute(const RTLIL::IdString& id, string v attributes[id] = value; } -string RTLIL::AttrObject::get_string_attribute(const RTLIL::IdString &id) const +string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const { std::string value; const auto it = attributes.find(id); @@ -1081,7 +1057,7 @@ string RTLIL::AttrObject::get_string_attribute(const RTLIL::IdString &id) const return value; } -void RTLIL::AttrObject::set_strpool_attribute(const RTLIL::IdString& id, const pool &data) +void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool &data) { string attrval; for (const auto &s : data) { @@ -1092,7 +1068,7 @@ void RTLIL::AttrObject::set_strpool_attribute(const RTLIL::IdString& id, const p set_string_attribute(id, attrval); } -void RTLIL::AttrObject::add_strpool_attribute(const RTLIL::IdString& id, const pool &data) +void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool &data) { pool union_data = get_strpool_attribute(id); union_data.insert(data.begin(), data.end()); @@ -1100,7 +1076,7 @@ void RTLIL::AttrObject::add_strpool_attribute(const RTLIL::IdString& id, const p set_strpool_attribute(id, union_data); } -pool RTLIL::AttrObject::get_strpool_attribute(const RTLIL::IdString &id) const +pool RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const { pool data; if (attributes.count(id) != 0) @@ -1125,7 +1101,7 @@ vector RTLIL::AttrObject::get_hdlname_attribute() const return split_tokens(get_string_attribute(ID::hdlname), " "); } -void RTLIL::AttrObject::set_intvec_attribute(const RTLIL::IdString& id, const vector &data) +void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector &data) { std::stringstream attrval; for (auto &i : data) { @@ -1136,7 +1112,7 @@ void RTLIL::AttrObject::set_intvec_attribute(const RTLIL::IdString& id, const ve attributes[id] = RTLIL::Const(attrval.str()); } -vector RTLIL::AttrObject::get_intvec_attribute(const RTLIL::IdString &id) const +vector RTLIL::AttrObject::get_intvec_attribute(RTLIL::IdString id) const { vector data; auto it = attributes.find(id); @@ -1154,7 +1130,7 @@ vector RTLIL::AttrObject::get_intvec_attribute(const RTLIL::IdString &id) c return data; } -bool RTLIL::Selection::boxed_module(const RTLIL::IdString &mod_name) const +bool RTLIL::Selection::boxed_module(RTLIL::IdString mod_name) const { if (current_design != nullptr) { auto module = current_design->module(mod_name); @@ -1165,7 +1141,7 @@ bool RTLIL::Selection::boxed_module(const RTLIL::IdString &mod_name) const } } -bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const +bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const { if (complete_selection) return true; @@ -1180,7 +1156,7 @@ bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const return false; } -bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) const +bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const { if (complete_selection) return true; @@ -1193,7 +1169,7 @@ bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) co return false; } -bool RTLIL::Selection::selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const +bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const { if (complete_selection) return true; @@ -1320,12 +1296,12 @@ RTLIL::ObjRange RTLIL::Design::modules() return RTLIL::ObjRange(&modules_, &refcount_modules_); } -RTLIL::Module *RTLIL::Design::module(const RTLIL::IdString& name) +RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) { return modules_.count(name) ? modules_.at(name) : NULL; } -const RTLIL::Module *RTLIL::Design::module(const RTLIL::IdString& name) const +const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const { return modules_.count(name) ? modules_.at(name) : NULL; } @@ -1514,21 +1490,21 @@ void RTLIL::Design::optimize() it.second.optimize(this); } -bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const +bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const { if (!selected_active_module.empty() && mod_name != selected_active_module) return false; return selection().selected_module(mod_name); } -bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const +bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const { if (!selected_active_module.empty() && mod_name != selected_active_module) return false; return selection().selected_whole_module(mod_name); } -bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL::IdString& memb_name) const +bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const { if (!selected_active_module.empty() && mod_name != selected_active_module) return false; @@ -1574,6 +1550,13 @@ void RTLIL::Design::pop_selection() push_full_selection(); } +std::string RTLIL::Design::to_rtlil_str(bool only_selected) const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_design(f, const_cast(this), only_selected); + return f.str(); +} + std::vector RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const { bool include_partials = partials == RTLIL::SELECT_ALL; @@ -1719,7 +1702,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dictname.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); } - int param(const RTLIL::IdString& name) + int param(RTLIL::IdString name) { auto it = cell->parameters.find(name); if (it == cell->parameters.end()) @@ -1753,7 +1736,7 @@ namespace { return it->second.as_int(); } - int param_bool(const RTLIL::IdString& name) + int param_bool(RTLIL::IdString name) { int v = param(name); if (GetSize(cell->parameters.at(name)) > 32) @@ -1763,7 +1746,7 @@ namespace { return v; } - int param_bool(const RTLIL::IdString& name, bool expected) + int param_bool(RTLIL::IdString name, bool expected) { int v = param_bool(name); if (v != expected) @@ -1771,20 +1754,20 @@ namespace { return v; } - void param_bits(const RTLIL::IdString& name, int width) + void param_bits(RTLIL::IdString name, int width) { param(name); if (GetSize(cell->parameters.at(name)) != width) error(__LINE__); } - std::string param_string(const RTLIL::IdString &name) + std::string param_string(RTLIL::IdString name) { param(name); return cell->parameters.at(name).decode_string(); } - void port(const RTLIL::IdString& name, int width) + void port(RTLIL::IdString name, int width) { auto it = cell->connections_.find(name); if (it == cell->connections_.end()) @@ -3008,6 +2991,8 @@ void RTLIL::Module::add(RTLIL::Binding *binding) void RTLIL::Module::remove(const pool &wires) { log_assert(refcount_wires_ == 0); + if (wires.empty()) + return; struct DeleteWireWorker { @@ -3065,6 +3050,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) } } +void RTLIL::Module::remove(RTLIL::Memory *memory) +{ + log_assert(memories.count(memory->name) != 0); + memories.erase(memory->name); + delete memory; +} + void RTLIL::Module::remove(RTLIL::Process *process) { log_assert(processes.count(process->name) != 0); @@ -4307,6 +4299,13 @@ RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpe return sig; } +std::string RTLIL::Module::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_module(f, "", const_cast(this), design, false); + return f.str(); +} + RTLIL::Wire::Wire() { static unsigned int hashidx_count = 123456789; @@ -4334,6 +4333,13 @@ RTLIL::Wire::~Wire() #endif } +std::string RTLIL::Wire::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_wire(f, "", this); + return f.str(); +} + #ifdef YOSYS_ENABLE_PYTHON static std::map all_wires; std::map *RTLIL::Wire::get_all_wires(void) @@ -4356,6 +4362,13 @@ RTLIL::Memory::Memory() #endif } +std::string RTLIL::Memory::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_memory(f, "", this); + return f.str(); +} + RTLIL::Process::Process() : module(nullptr) { static unsigned int hashidx_count = 123456789; @@ -4363,6 +4376,13 @@ RTLIL::Process::Process() : module(nullptr) hashidx_ = hashidx_count; } +std::string RTLIL::Process::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_proc(f, "", this); + return f.str(); +} + RTLIL::Cell::Cell() : module(nullptr) { static unsigned int hashidx_count = 123456789; @@ -4384,6 +4404,13 @@ RTLIL::Cell::~Cell() #endif } +std::string RTLIL::Cell::to_rtlil_str() const +{ + std::ostringstream f; + RTLIL_BACKEND::dump_cell(f, "", this); + return f.str(); +} + #ifdef YOSYS_ENABLE_PYTHON static std::map all_cells; std::map *RTLIL::Cell::get_all_cells(void) @@ -4392,14 +4419,14 @@ std::map *RTLIL::Cell::get_all_cells(void) } #endif -bool RTLIL::Cell::hasPort(const RTLIL::IdString& portname) const +bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const { return connections_.count(portname) != 0; } // bufnorm -const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString& portname) const +const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const { return connections_.at(portname); } @@ -4418,7 +4445,7 @@ bool RTLIL::Cell::known() const return false; } -bool RTLIL::Cell::input(const RTLIL::IdString& portname) const +bool RTLIL::Cell::input(RTLIL::IdString portname) const { if (yosys_celltypes.cell_known(type)) return yosys_celltypes.cell_input(type, portname); @@ -4430,7 +4457,7 @@ bool RTLIL::Cell::input(const RTLIL::IdString& portname) const return false; } -bool RTLIL::Cell::output(const RTLIL::IdString& portname) const +bool RTLIL::Cell::output(RTLIL::IdString portname) const { if (yosys_celltypes.cell_known(type)) return yosys_celltypes.cell_output(type, portname); @@ -4442,7 +4469,7 @@ bool RTLIL::Cell::output(const RTLIL::IdString& portname) const return false; } -RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const +RTLIL::PortDir RTLIL::Cell::port_dir(RTLIL::IdString portname) const { if (yosys_celltypes.cell_known(type)) return yosys_celltypes.cell_port_dir(type, portname); @@ -4458,22 +4485,22 @@ RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const return PortDir::PD_UNKNOWN; } -bool RTLIL::Cell::hasParam(const RTLIL::IdString& paramname) const +bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const { return parameters.count(paramname) != 0; } -void RTLIL::Cell::unsetParam(const RTLIL::IdString& paramname) +void RTLIL::Cell::unsetParam(RTLIL::IdString paramname) { parameters.erase(paramname); } -void RTLIL::Cell::setParam(const RTLIL::IdString& paramname, RTLIL::Const value) +void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value) { parameters[paramname] = std::move(value); } -const RTLIL::Const &RTLIL::Cell::getParam(const RTLIL::IdString& paramname) const +const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const { const auto &it = parameters.find(paramname); if (it != parameters.end()) @@ -4662,8 +4689,6 @@ bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const RTLIL::SigSpec::SigSpec(std::initializer_list parts) { - cover("kernel.rtlil.sigspec.init.list"); - init_empty_bits(); log_assert(parts.size() > 0); auto ie = parts.begin(); @@ -4674,8 +4699,6 @@ RTLIL::SigSpec::SigSpec(std::initializer_list parts) RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) { - cover("kernel.rtlil.sigspec.init.const"); - if (GetSize(value) != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(value); @@ -4687,8 +4710,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) RTLIL::SigSpec::SigSpec(RTLIL::Const &&value) { - cover("kernel.rtlil.sigspec.init.const.move"); - if (GetSize(value) != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(value); @@ -4700,8 +4721,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Const &&value) RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) { - cover("kernel.rtlil.sigspec.init.chunk"); - if (chunk.width != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(chunk); @@ -4713,8 +4732,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk) { - cover("kernel.rtlil.sigspec.init.chunk.move"); - if (chunk.width != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(chunk); @@ -4726,8 +4743,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk) RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) { - cover("kernel.rtlil.sigspec.init.wire"); - if (wire->width != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(wire); @@ -4739,8 +4754,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) { - cover("kernel.rtlil.sigspec.init.wire_part"); - if (width != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(wire, offset, width); @@ -4752,8 +4765,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) RTLIL::SigSpec::SigSpec(const std::string &str) { - cover("kernel.rtlil.sigspec.init.str"); - if (str.size() != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(str); @@ -4765,8 +4776,6 @@ RTLIL::SigSpec::SigSpec(const std::string &str) RTLIL::SigSpec::SigSpec(int val, int width) { - cover("kernel.rtlil.sigspec.init.int"); - if (width != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(val, width); @@ -4777,8 +4786,6 @@ RTLIL::SigSpec::SigSpec(int val, int width) RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) { - cover("kernel.rtlil.sigspec.init.state"); - if (width != 0) { rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(bit, width); @@ -4789,8 +4796,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width) { - cover("kernel.rtlil.sigspec.init.bit"); - if (width != 0) { if (bit.wire == NULL) { rep_ = CHUNK; @@ -4811,8 +4816,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width) RTLIL::SigSpec::SigSpec(const std::vector &chunks) { - cover("kernel.rtlil.sigspec.init.stdvec_chunks"); - init_empty_bits(); for (const auto &c : chunks) append(c); @@ -4821,8 +4824,6 @@ RTLIL::SigSpec::SigSpec(const std::vector &chunks) RTLIL::SigSpec::SigSpec(const std::vector &bits) { - cover("kernel.rtlil.sigspec.init.stdvec_bits"); - init_empty_bits(); for (const auto &bit : bits) append(bit); @@ -4831,8 +4832,6 @@ RTLIL::SigSpec::SigSpec(const std::vector &bits) RTLIL::SigSpec::SigSpec(const pool &bits) { - cover("kernel.rtlil.sigspec.init.pool_bits"); - init_empty_bits(); for (const auto &bit : bits) append(bit); @@ -4841,8 +4840,6 @@ RTLIL::SigSpec::SigSpec(const pool &bits) RTLIL::SigSpec::SigSpec(const std::set &bits) { - cover("kernel.rtlil.sigspec.init.stdset_bits"); - init_empty_bits(); for (const auto &bit : bits) append(bit); @@ -4851,8 +4848,6 @@ RTLIL::SigSpec::SigSpec(const std::set &bits) RTLIL::SigSpec::SigSpec(bool bit) { - cover("kernel.rtlil.sigspec.init.bool"); - rep_ = CHUNK; new (&chunk_) RTLIL::SigChunk(bit ? RTLIL::S1 : RTLIL::S0); check(); @@ -4888,8 +4883,6 @@ void RTLIL::SigSpec::unpack() if (rep_ == BITS) return; - cover("kernel.rtlil.sigspec.convert.unpack"); - std::vector bits; bits.reserve(chunk_.width); for (int i = 0; i < chunk_.width; i++) @@ -4905,8 +4898,6 @@ void RTLIL::SigSpec::try_repack() if (rep_ != BITS) return; - cover("kernel.rtlil.sigspec.convert.try_repack"); - int bits_size = GetSize(bits_); if (bits_size == 0) return; @@ -4935,8 +4926,6 @@ void RTLIL::SigSpec::try_repack() Hasher::hash_t RTLIL::SigSpec::updhash() const { - cover("kernel.rtlil.sigspec.hash"); - Hasher h; for (auto &c : chunks()) if (c.wire == NULL) { @@ -4957,7 +4946,6 @@ Hasher::hash_t RTLIL::SigSpec::updhash() const void RTLIL::SigSpec::sort() { unpack(); - cover("kernel.rtlil.sigspec.sort"); std::sort(bits_.begin(), bits_.end()); hash_.clear(); try_repack(); @@ -4966,8 +4954,6 @@ void RTLIL::SigSpec::sort() void RTLIL::SigSpec::sort_and_unify() { unpack(); - cover("kernel.rtlil.sigspec.sort_and_unify"); - // A copy of the bits vector is used to prevent duplicating the logic from // SigSpec::SigSpec(std::vector). This incurrs an extra copy but // that isn't showing up as significant in profiles. @@ -5023,8 +5009,6 @@ void RTLIL::SigSpec::replace(const dict &rules) void RTLIL::SigSpec::replace(const dict &rules, RTLIL::SigSpec *other) const { - cover("kernel.rtlil.sigspec.replace_dict"); - log_assert(other != NULL); log_assert(size() == other->size()); @@ -5052,8 +5036,6 @@ void RTLIL::SigSpec::replace(const std::map &rules void RTLIL::SigSpec::replace(const std::map &rules, RTLIL::SigSpec *other) const { - cover("kernel.rtlil.sigspec.replace_map"); - log_assert(other != NULL); log_assert(size() == other->size()); @@ -5087,11 +5069,6 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) { - if (other) - cover("kernel.rtlil.sigspec.remove_other"); - else - cover("kernel.rtlil.sigspec.remove"); - unpack(); if (other != NULL) { log_assert(size() == other->size()); @@ -5142,11 +5119,6 @@ void RTLIL::SigSpec::remove(const pool &pattern, RTLIL::SigSpec * void RTLIL::SigSpec::remove2(const pool &pattern, RTLIL::SigSpec *other) { - if (other) - cover("kernel.rtlil.sigspec.remove_other"); - else - cover("kernel.rtlil.sigspec.remove"); - unpack(); if (other != NULL) { @@ -5180,11 +5152,6 @@ void RTLIL::SigSpec::remove2(const pool &pattern, RTLIL::SigSpec void RTLIL::SigSpec::remove2(const std::set &pattern, RTLIL::SigSpec *other) { - if (other) - cover("kernel.rtlil.sigspec.remove_other"); - else - cover("kernel.rtlil.sigspec.remove"); - unpack(); if (other != NULL) { @@ -5218,11 +5185,6 @@ void RTLIL::SigSpec::remove2(const std::set &pattern, RTLIL::SigS void RTLIL::SigSpec::remove2(const pool &pattern, RTLIL::SigSpec *other) { - if (other) - cover("kernel.rtlil.sigspec.remove_other"); - else - cover("kernel.rtlil.sigspec.remove"); - unpack(); if (other != NULL) { @@ -5256,11 +5218,6 @@ void RTLIL::SigSpec::remove2(const pool &pattern, RTLIL::SigSpec * RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const { - if (other) - cover("kernel.rtlil.sigspec.extract_other"); - else - cover("kernel.rtlil.sigspec.extract"); - log_assert(other == NULL || size() == other->size()); RTLIL::SigSpec ret; @@ -5294,11 +5251,6 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLI RTLIL::SigSpec RTLIL::SigSpec::extract(const pool &pattern, const RTLIL::SigSpec *other) const { - if (other) - cover("kernel.rtlil.sigspec.extract_other"); - else - cover("kernel.rtlil.sigspec.extract"); - log_assert(other == NULL || size() == other->size()); std::vector bits_match = to_sigbit_vector(); @@ -5324,8 +5276,6 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const pool &pattern, const void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { - cover("kernel.rtlil.sigspec.replace_pos"); - if (with.size() == 0) return; @@ -5350,8 +5300,6 @@ void RTLIL::SigSpec::remove_const() { if (rep_ == CHUNK) { - cover("kernel.rtlil.sigspec.remove_const.packed"); - if (chunk_.wire == NULL) { chunk_.~SigChunk(); init_empty_bits(); @@ -5360,8 +5308,6 @@ void RTLIL::SigSpec::remove_const() } else { - cover("kernel.rtlil.sigspec.remove_const.unpacked"); - std::vector new_bits; new_bits.reserve(bits_.size()); for (auto &bit : bits_) @@ -5379,8 +5325,6 @@ void RTLIL::SigSpec::remove_const() void RTLIL::SigSpec::remove(int offset, int length) { - cover("kernel.rtlil.sigspec.remove_pos"); - if (length == 0) return; @@ -5403,8 +5347,6 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const log_assert(length >= 0); log_assert(offset + length <= size()); - cover("kernel.rtlil.sigspec.extract_pos"); - SigSpec extracted; Chunks cs = chunks(); auto it = cs.begin(); @@ -5458,8 +5400,6 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) return; } - cover("kernel.rtlil.sigspec.append"); - hash_.clear(); if (rep_ == CHUNK && signal.rep_ == CHUNK && chunk_.wire == signal.chunk_.wire) { if (chunk_.wire == NULL) { @@ -5491,8 +5431,6 @@ void RTLIL::SigSpec::append(const RTLIL::SigBit &bit) } if (rep_ == CHUNK && chunk_.wire == bit.wire) { - cover("kernel.rtlil.sigspec.append_bit.packed"); - if (chunk_.wire == NULL) { chunk_.data.push_back(bit.data); chunk_.width++; @@ -5506,15 +5444,12 @@ void RTLIL::SigSpec::append(const RTLIL::SigBit &bit) unpack(); - cover("kernel.rtlil.sigspec.append_bit.unpacked"); bits_.push_back(bit); check(); } void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { - cover("kernel.rtlil.sigspec.extend_u0"); - if (size() > width) remove(width, size() - width); @@ -5529,8 +5464,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const { - cover("kernel.rtlil.sigspec.repeat"); - RTLIL::SigSpec sig; for (int i = 0; i < num; i++) sig.append(*this); @@ -5542,8 +5475,6 @@ void RTLIL::SigSpec::check(Module *mod) const { if (rep_ == CHUNK) { - cover("kernel.rtlil.sigspec.check.packed"); - log_assert(chunk_.width != 0); if (chunk_.wire == NULL) { log_assert(chunk_.offset == 0); @@ -5557,14 +5488,8 @@ void RTLIL::SigSpec::check(Module *mod) const log_assert(chunk_.wire->module == mod); } } - else if (size() > 64) + else if (size() <= 64) { - cover("kernel.rtlil.sigspec.check.skip"); - } - else - { - cover("kernel.rtlil.sigspec.check.unpacked"); - if (mod != nullptr) { for (const RTLIL::SigBit &bit : bits_) if (bit.wire != nullptr) @@ -5576,8 +5501,6 @@ void RTLIL::SigSpec::check(Module *mod) const bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { - cover("kernel.rtlil.sigspec.comp_lt"); - if (this == &other) return false; @@ -5591,14 +5514,11 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const ++other_it; } - cover("kernel.rtlil.sigspec.comp_lt.equal"); return false; } bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const { - cover("kernel.rtlil.sigspec.comp_eq"); - if (this == &other) return true; @@ -5612,14 +5532,11 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const ++other_it; } - cover("kernel.rtlil.sigspec.comp_eq.equal"); return true; } bool RTLIL::SigSpec::is_wire() const { - cover("kernel.rtlil.sigspec.is_wire"); - Chunks cs = chunks(); auto it = cs.begin(); if (it == cs.end()) @@ -5630,8 +5547,6 @@ bool RTLIL::SigSpec::is_wire() const bool RTLIL::SigSpec::is_chunk() const { - cover("kernel.rtlil.sigspec.is_chunk"); - Chunks cs = chunks(); auto it = cs.begin(); if (it == cs.end()) @@ -5649,8 +5564,6 @@ bool RTLIL::SigSpec::known_driver() const bool RTLIL::SigSpec::is_fully_const() const { - cover("kernel.rtlil.sigspec.is_fully_const"); - for (auto &chunk : chunks()) if (chunk.width > 0 && chunk.wire != NULL) return false; @@ -5659,8 +5572,6 @@ bool RTLIL::SigSpec::is_fully_const() const bool RTLIL::SigSpec::is_fully_zero() const { - cover("kernel.rtlil.sigspec.is_fully_zero"); - for (auto &chunk : chunks()) { if (chunk.width > 0 && chunk.wire != NULL) return false; @@ -5673,8 +5584,6 @@ bool RTLIL::SigSpec::is_fully_zero() const bool RTLIL::SigSpec::is_fully_ones() const { - cover("kernel.rtlil.sigspec.is_fully_ones"); - for (auto &chunk : chunks()) { if (chunk.width > 0 && chunk.wire != NULL) return false; @@ -5687,8 +5596,6 @@ bool RTLIL::SigSpec::is_fully_ones() const bool RTLIL::SigSpec::is_fully_def() const { - cover("kernel.rtlil.sigspec.is_fully_def"); - for (auto &chunk : chunks()) { if (chunk.width > 0 && chunk.wire != NULL) return false; @@ -5701,8 +5608,6 @@ bool RTLIL::SigSpec::is_fully_def() const bool RTLIL::SigSpec::is_fully_undef() const { - cover("kernel.rtlil.sigspec.is_fully_undef"); - for (auto &chunk : chunks()) { if (chunk.width > 0 && chunk.wire != NULL) return false; @@ -5715,8 +5620,6 @@ bool RTLIL::SigSpec::is_fully_undef() const bool RTLIL::SigSpec::has_const() const { - cover("kernel.rtlil.sigspec.has_const"); - for (auto &chunk : chunks()) if (chunk.width > 0 && chunk.wire == NULL) return true; @@ -5725,8 +5628,6 @@ bool RTLIL::SigSpec::has_const() const bool RTLIL::SigSpec::has_const(State state) const { - cover("kernel.rtlil.sigspec.has_const"); - for (auto &chunk : chunks()) if (chunk.width > 0 && chunk.wire == NULL && std::find(chunk.data.begin(), chunk.data.end(), state) != chunk.data.end()) return true; @@ -5736,8 +5637,6 @@ bool RTLIL::SigSpec::has_const(State state) const bool RTLIL::SigSpec::has_marked_bits() const { - cover("kernel.rtlil.sigspec.has_marked_bits"); - for (auto &chunk : chunks()) if (chunk.width > 0 && chunk.wire == NULL) { for (RTLIL::State d : chunk.data) @@ -5749,8 +5648,6 @@ bool RTLIL::SigSpec::has_marked_bits() const bool RTLIL::SigSpec::is_onehot(int *pos) const { - cover("kernel.rtlil.sigspec.is_onehot"); - if (std::optional c = try_as_const()) return c->is_onehot(pos); return false; @@ -5758,8 +5655,6 @@ bool RTLIL::SigSpec::is_onehot(int *pos) const bool RTLIL::SigSpec::as_bool() const { - cover("kernel.rtlil.sigspec.as_bool"); - std::optional c = try_as_const(); log_assert(c.has_value()); return c->as_bool(); @@ -5767,8 +5662,6 @@ bool RTLIL::SigSpec::as_bool() const int RTLIL::SigSpec::as_int(bool is_signed) const { - cover("kernel.rtlil.sigspec.as_int"); - std::optional c = try_as_const(); log_assert(c.has_value()); return c->as_int(is_signed); @@ -5776,8 +5669,6 @@ int RTLIL::SigSpec::as_int(bool is_signed) const bool RTLIL::SigSpec::convertible_to_int(bool is_signed) const { - cover("kernel.rtlil.sigspec.convertible_to_int"); - std::optional c = try_as_const(); if (!c.has_value()) return false; @@ -5786,8 +5677,6 @@ bool RTLIL::SigSpec::convertible_to_int(bool is_signed) const std::optional RTLIL::SigSpec::try_as_int(bool is_signed) const { - cover("kernel.rtlil.sigspec.try_as_int"); - std::optional c = try_as_const(); if (!c.has_value()) return std::nullopt; @@ -5796,8 +5685,6 @@ std::optional RTLIL::SigSpec::try_as_int(bool is_signed) const int RTLIL::SigSpec::as_int_saturating(bool is_signed) const { - cover("kernel.rtlil.sigspec.try_as_int"); - std::optional c = try_as_const(); log_assert(c.has_value()); return c->as_int_saturating(is_signed); @@ -5805,8 +5692,6 @@ int RTLIL::SigSpec::as_int_saturating(bool is_signed) const std::string RTLIL::SigSpec::as_string() const { - cover("kernel.rtlil.sigspec.as_string"); - std::string str; str.reserve(size()); std::vector chunks = *this; @@ -5822,8 +5707,6 @@ std::string RTLIL::SigSpec::as_string() const std::optional RTLIL::SigSpec::try_as_const() const { - cover("kernel.rtlil.sigspec.as_const"); - Chunks cs = chunks(); auto it = cs.begin(); if (it == cs.end()) @@ -5836,8 +5719,6 @@ std::optional RTLIL::SigSpec::try_as_const() const RTLIL::Const RTLIL::SigSpec::as_const() const { - cover("kernel.rtlil.sigspec.as_const"); - std::optional c = try_as_const(); log_assert(c.has_value()); return *c; @@ -5845,8 +5726,6 @@ RTLIL::Const RTLIL::SigSpec::as_const() const RTLIL::Wire *RTLIL::SigSpec::as_wire() const { - cover("kernel.rtlil.sigspec.as_wire"); - Chunks cs = chunks(); auto it = cs.begin(); log_assert(it != cs.end()); @@ -5857,8 +5736,6 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const { - cover("kernel.rtlil.sigspec.as_chunk"); - Chunks cs = chunks(); auto it = cs.begin(); log_assert(it != cs.end()); @@ -5869,14 +5746,11 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const RTLIL::SigBit RTLIL::SigSpec::as_bit() const { - cover("kernel.rtlil.sigspec.as_bit"); return RTLIL::SigBit(*this); } bool RTLIL::SigSpec::match(const char* pattern) const { - cover("kernel.rtlil.sigspec.match"); - int pattern_len = strlen(pattern); log_assert(pattern_len == size()); @@ -5906,8 +5780,6 @@ bool RTLIL::SigSpec::match(const char* pattern) const std::set RTLIL::SigSpec::to_sigbit_set() const { - cover("kernel.rtlil.sigspec.to_sigbit_set"); - std::set sigbits; for (auto &c : chunks()) for (int i = 0; i < c.width; i++) @@ -5917,8 +5789,6 @@ std::set RTLIL::SigSpec::to_sigbit_set() const pool RTLIL::SigSpec::to_sigbit_pool() const { - cover("kernel.rtlil.sigspec.to_sigbit_pool"); - pool sigbits; sigbits.reserve(size()); for (auto &c : chunks()) @@ -5929,8 +5799,6 @@ pool RTLIL::SigSpec::to_sigbit_pool() const std::vector RTLIL::SigSpec::to_sigbit_vector() const { - cover("kernel.rtlil.sigspec.to_sigbit_vector"); - std::vector result; result.reserve(size()); for (SigBit bit : *this) @@ -5940,8 +5808,6 @@ std::vector RTLIL::SigSpec::to_sigbit_vector() const std::map RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const { - cover("kernel.rtlil.sigspec.to_sigbit_map"); - int this_size = size(); log_assert(this_size == other.size()); @@ -5954,8 +5820,6 @@ std::map RTLIL::SigSpec::to_sigbit_map(const RTLIL dict RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const { - cover("kernel.rtlil.sigspec.to_sigbit_dict"); - int this_size = size(); log_assert(this_size == other.size()); @@ -5979,9 +5843,6 @@ static void sigspec_parse_split(std::vector &tokens, const std::str bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) { - cover("kernel.rtlil.sigspec.parse"); - - std::vector tokens; sigspec_parse_split(tokens, str, ','); @@ -5995,7 +5856,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri continue; if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') { - cover("kernel.rtlil.sigspec.parse.const"); VERILOG_FRONTEND::ConstParser p{Location()}; auto ast = p.const2ast(netname); if (ast == nullptr) @@ -6007,8 +5867,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri if (module == NULL) return false; - cover("kernel.rtlil.sigspec.parse.net"); - if (netname[0] != '$' && netname[0] != '\\') netname = "\\" + netname; @@ -6037,13 +5895,11 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); if (index_tokens.size() == 1) { - cover("kernel.rtlil.sigspec.parse.bit_sel"); int a = atoi(index_tokens.at(0).c_str()); if (a < 0 || a >= wire->width) return false; sig.append(RTLIL::SigSpec(wire, a)); } else { - cover("kernel.rtlil.sigspec.parse.part_sel"); int a = atoi(index_tokens.at(0).c_str()); int b = atoi(index_tokens.at(1).c_str()); if (a > b) { @@ -6068,8 +5924,6 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL if (str.empty() || str[0] != '@') return parse(sig, module, str); - cover("kernel.rtlil.sigspec.parse.sel"); - str = RTLIL::escape_id(str.substr(1)); if (design->selection_vars.count(str) == 0) return false; @@ -6086,13 +5940,11 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) { if (str == "0") { - cover("kernel.rtlil.sigspec.parse.rhs_zeros"); sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.size()); return true; } if (str == "~0") { - cover("kernel.rtlil.sigspec.parse.rhs_ones"); sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.size()); return true; } @@ -6102,7 +5954,6 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R long int val = strtol(p, &endptr, 10); if (endptr && endptr != p && *endptr == 0) { sig = RTLIL::SigSpec(val, lhs.size()); - cover("kernel.rtlil.sigspec.parse.rhs_dec"); return true; } } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4da030e8d..fea53081e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -134,6 +134,17 @@ struct RTLIL::IdString std::string_view str_view() const { return {buf, static_cast(size)}; } }; + struct AutoidxStorage { + // Append the negated (i.e. positive) ID to this string to get + // the real string. The prefix strings must live forever. + const std::string *prefix; + // Cache of the full string, or nullptr if not cached yet. + std::atomic full_str; + + AutoidxStorage(const std::string *prefix) : prefix(prefix), full_str(nullptr) {} + AutoidxStorage(AutoidxStorage&& other) : prefix(other.prefix), full_str(other.full_str.exchange(nullptr, std::memory_order_relaxed)) {} + ~AutoidxStorage() { delete[] full_str.load(std::memory_order_acquire); } + }; // the global id string cache @@ -147,17 +158,12 @@ struct RTLIL::IdString static std::vector global_id_storage_; // Lookup table for non-autoidx IDs static std::unordered_map global_id_index_; - // Shared prefix string storage for autoidx IDs, which have negative - // indices. Append the negated (i.e. positive) ID to this string to get - // the real string. The prefix strings must live forever. - static std::unordered_map global_autoidx_id_prefix_storage_; - // Explicit string storage for autoidx IDs - static std::unordered_map global_autoidx_id_storage_; -#ifndef YOSYS_NO_IDS_REFCNT + // Storage for autoidx IDs, which have negative indices, i.e. all entries in this + // map have negative keys. + static std::unordered_map global_autoidx_id_storage_; // All (index, refcount) pairs in this map have refcount > 0. static std::unordered_map global_refcount_storage_; static std::vector global_free_idx_list_; -#endif static int refcount(int idx) { auto it = global_refcount_storage_.find(idx); @@ -189,6 +195,7 @@ struct RTLIL::IdString static int insert(std::string_view p) { log_assert(destruct_guard_ok); + log_assert(!Multithreading::active()); auto it = global_id_index_.find(p); if (it != global_id_index_.end()) { @@ -204,8 +211,9 @@ struct RTLIL::IdString // Inserts an ID with string `prefix + autoidx', incrementing autoidx. // `prefix` must start with '$auto$', end with '$', and live forever. static IdString new_autoidx_with_prefix(const std::string *prefix) { + log_assert(!Multithreading::active()); int index = -(autoidx++); - global_autoidx_id_prefix_storage_.insert({index, prefix}); + global_autoidx_id_storage_.insert({index, prefix}); return from_index(index); } @@ -215,8 +223,8 @@ struct RTLIL::IdString constexpr inline IdString() : index_(0) { } inline IdString(const char *str) : index_(insert(std::string_view(str))) { } - constexpr inline IdString(const IdString &str) : index_(str.index_) { } - inline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; } + constexpr IdString(const IdString &str) = default; + IdString(IdString &&str) = default; inline IdString(const std::string &str) : index_(insert(std::string_view(str))) { } inline IdString(std::string_view str) : index_(insert(str)) { } constexpr inline IdString(StaticId id) : index_(static_cast(id)) {} @@ -233,22 +241,23 @@ struct RTLIL::IdString *this = id; } - constexpr inline const IdString &id_string() const { return *this; } - inline const char *c_str() const { if (index_ >= 0) return global_id_storage_.at(index_).buf; - auto it = global_autoidx_id_storage_.find(index_); - if (it != global_autoidx_id_storage_.end()) - return it->second; - const std::string &prefix = *global_autoidx_id_prefix_storage_.at(index_); + AutoidxStorage &s = global_autoidx_id_storage_.at(index_); + char *full_str = s.full_str.load(std::memory_order_acquire); + if (full_str != nullptr) + return full_str; + const std::string &prefix = *s.prefix; std::string suffix = std::to_string(-index_); char *c = new char[prefix.size() + suffix.size() + 1]; memcpy(c, prefix.data(), prefix.size()); memcpy(c + prefix.size(), suffix.c_str(), suffix.size() + 1); - global_autoidx_id_storage_.insert(it, {index_, c}); - return c; + if (s.full_str.compare_exchange_strong(full_str, c, std::memory_order_acq_rel)) + return c; + delete[] c; + return full_str; } inline std::string str() const { @@ -262,7 +271,7 @@ struct RTLIL::IdString *out += global_id_storage_.at(index_).str_view(); return; } - *out += *global_autoidx_id_prefix_storage_.at(index_); + *out += *global_autoidx_id_storage_.at(index_).prefix; *out += std::to_string(-index_); } @@ -348,7 +357,7 @@ struct RTLIL::IdString if (index_ >= 0) { return const_iterator(global_id_storage_.at(index_)); } - return const_iterator(global_autoidx_id_prefix_storage_.at(index_), -index_); + return const_iterator(global_autoidx_id_storage_.at(index_).prefix, -index_); } const_iterator end() const { return const_iterator(); @@ -358,10 +367,10 @@ struct RTLIL::IdString if (index_ >= 0) { return Substrings(global_id_storage_.at(index_)); } - return Substrings(global_autoidx_id_prefix_storage_.at(index_), -index_); + return Substrings(global_autoidx_id_storage_.at(index_).prefix, -index_); } - inline bool lt_by_name(const IdString &rhs) const { + inline bool lt_by_name(IdString rhs) const { Substrings lhs_it = substrings(); Substrings rhs_it = rhs.substrings(); std::string_view lhs_substr = lhs_it.first(); @@ -388,12 +397,12 @@ struct RTLIL::IdString } } - inline bool operator<(const IdString &rhs) const { + inline bool operator<(IdString rhs) const { return index_ < rhs.index_; } - inline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; } - inline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; } + inline bool operator==(IdString rhs) const { return index_ == rhs.index_; } + inline bool operator!=(IdString rhs) const { return index_ != rhs.index_; } // The methods below are just convenience functions for better compatibility with std::string. @@ -411,7 +420,7 @@ struct RTLIL::IdString #endif return *(storage.buf + i); } - const std::string &id_start = *global_autoidx_id_prefix_storage_.at(index_); + const std::string &id_start = *global_autoidx_id_storage_.at(index_).prefix; if (i < id_start.size()) return id_start[i]; i -= id_start.size(); @@ -517,7 +526,7 @@ struct RTLIL::IdString return (... || in(args)); } - bool in(const IdString &rhs) const { return *this == rhs; } + bool in(IdString rhs) const { return *this == rhs; } bool in(const char *rhs) const { return *this == rhs; } bool in(const std::string &rhs) const { return *this == rhs; } inline bool in(const pool &rhs) const; @@ -597,7 +606,8 @@ private: } static void get_reference(int idx) { - #ifndef YOSYS_NO_IDS_REFCNT + log_assert(!Multithreading::active()); + if (idx < static_cast(StaticId::STATIC_ID_END)) return; auto it = global_refcount_storage_.find(idx); @@ -605,7 +615,6 @@ private: global_refcount_storage_.insert(it, {idx, 1}); else ++it->second; - #endif #ifdef YOSYS_XTRACE_GET_PUT if (yosys_xtrace && idx >= static_cast(StaticId::STATIC_ID_END)) log("#X# GET-BY-INDEX '%s' (index %d, refcount %u)\n", from_index(idx), idx, refcount(idx)); @@ -614,7 +623,8 @@ private: void put_reference() { - #ifndef YOSYS_NO_IDS_REFCNT + log_assert(!Multithreading::active()); + // put_reference() may be called from destructors after the destructor of // global_refcount_storage_ has been run. in this case we simply do nothing. if (index_ < static_cast(StaticId::STATIC_ID_END) || !destruct_guard_ok) @@ -628,20 +638,19 @@ private: if (--it->second == 0) { global_refcount_storage_.erase(it); } - #endif } }; namespace hashlib { template <> struct hash_ops { - static inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) { + static inline bool cmp(RTLIL::IdString a, RTLIL::IdString b) { return a == b; } - [[nodiscard]] static inline Hasher hash(const RTLIL::IdString &id) { + [[nodiscard]] static inline Hasher hash(RTLIL::IdString id) { return id.hash_top(); } - [[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString &id, Hasher h) { + [[nodiscard]] static inline Hasher hash_into(RTLIL::IdString id, Hasher h) { return id.hash_into(h); } }; @@ -748,11 +757,11 @@ namespace RTLIL { return str.substr(1); } - static inline std::string unescape_id(const RTLIL::IdString &str) { + static inline std::string unescape_id(RTLIL::IdString str) { return unescape_id(str.str()); } - static inline const char *id2cstr(const RTLIL::IdString &str) { + static inline const char *id2cstr(RTLIL::IdString str) { return log_id(str); } @@ -769,7 +778,7 @@ namespace RTLIL { }; struct sort_by_id_str { - bool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const { + bool operator()(RTLIL::IdString a, RTLIL::IdString b) const { return a.lt_by_name(b); } }; @@ -1235,22 +1244,22 @@ struct RTLIL::AttrObject { dict attributes; - bool has_attribute(const RTLIL::IdString &id) const; + bool has_attribute(RTLIL::IdString id) const; - void set_bool_attribute(const RTLIL::IdString &id, bool value=true); - bool get_bool_attribute(const RTLIL::IdString &id) const; + void set_bool_attribute(RTLIL::IdString id, bool value=true); + bool get_bool_attribute(RTLIL::IdString id) const; [[deprecated("Use Module::get_blackbox_attribute() instead.")]] bool get_blackbox_attribute(bool ignore_wb=false) const { return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox)); } - void set_string_attribute(const RTLIL::IdString& id, string value); - string get_string_attribute(const RTLIL::IdString &id) const; + void set_string_attribute(RTLIL::IdString id, string value); + string get_string_attribute(RTLIL::IdString id) const; - void set_strpool_attribute(const RTLIL::IdString& id, const pool &data); - void add_strpool_attribute(const RTLIL::IdString& id, const pool &data); - pool get_strpool_attribute(const RTLIL::IdString &id) const; + void set_strpool_attribute(RTLIL::IdString id, const pool &data); + void add_strpool_attribute(RTLIL::IdString id, const pool &data); + pool get_strpool_attribute(RTLIL::IdString id) const; void set_src_attribute(const std::string &src) { set_string_attribute(ID::src, src); @@ -1262,8 +1271,8 @@ struct RTLIL::AttrObject void set_hdlname_attribute(const vector &hierarchy); vector get_hdlname_attribute() const; - void set_intvec_attribute(const RTLIL::IdString& id, const vector &data); - vector get_intvec_attribute(const RTLIL::IdString &id) const; + void set_intvec_attribute(RTLIL::IdString id, const vector &data); + vector get_intvec_attribute(RTLIL::IdString id) const; }; struct RTLIL::NamedObject : public RTLIL::AttrObject @@ -1770,18 +1779,18 @@ struct RTLIL::Selection // checks if the given module exists in the current design and is a // boxed module, warning the user if the current design is not set - bool boxed_module(const RTLIL::IdString &mod_name) const; + bool boxed_module(RTLIL::IdString mod_name) const; // checks if the given module is included in this selection - bool selected_module(const RTLIL::IdString &mod_name) const; + bool selected_module(RTLIL::IdString mod_name) const; // checks if the given module is wholly included in this selection, // i.e. not partially selected - bool selected_whole_module(const RTLIL::IdString &mod_name) const; + bool selected_whole_module(RTLIL::IdString mod_name) const; // checks if the given member from the given module is included in this // selection - bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const; + bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; // optimizes this selection for the given design by: // - removing non-existent modules and members, any boxed modules and @@ -1851,7 +1860,7 @@ struct RTLIL::Monitor virtual ~Monitor() { } virtual void notify_module_add(RTLIL::Module*) { } virtual void notify_module_del(RTLIL::Module*) { } - virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { } + virtual void notify_connect(RTLIL::Cell*, RTLIL::IdString, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { } virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } virtual void notify_connect(RTLIL::Module*, const std::vector&) { } virtual void notify_blackout(RTLIL::Module*) { } @@ -1886,11 +1895,11 @@ struct RTLIL::Design ~Design(); RTLIL::ObjRange modules(); - RTLIL::Module *module(const RTLIL::IdString &name); - const RTLIL::Module *module(const RTLIL::IdString &name) const; + RTLIL::Module *module(RTLIL::IdString name); + const RTLIL::Module *module(RTLIL::IdString name) const; RTLIL::Module *top_module() const; - bool has(const RTLIL::IdString &id) const { + bool has(RTLIL::IdString id) const { return modules_.count(id) != 0; } @@ -1917,15 +1926,15 @@ struct RTLIL::Design void optimize(); // checks if the given module is included in the current selection - bool selected_module(const RTLIL::IdString &mod_name) const; + bool selected_module(RTLIL::IdString mod_name) const; // checks if the given module is wholly included in the current // selection, i.e. not partially selected - bool selected_whole_module(const RTLIL::IdString &mod_name) const; + bool selected_whole_module(RTLIL::IdString mod_name) const; // checks if the given member from the given module is included in the // current selection - bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const; + bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; // checks if the given module is included in the current selection bool selected_module(RTLIL::Module *mod) const; @@ -2022,7 +2031,10 @@ struct RTLIL::Design // returns all selected unboxed whole modules, warning the user if any // partially selected or boxed modules have been ignored std::vector selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } + static std::map *get_all_designs(void); + + std::string to_rtlil_str(bool only_selected = true) const; }; struct RTLIL::Module : public RTLIL::NamedObject @@ -2057,7 +2069,7 @@ public: virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool mayfail = false); virtual RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, const dict &interfaces, const dict &modports, bool mayfail = false); - virtual size_t count_id(const RTLIL::IdString& id); + virtual size_t count_id(RTLIL::IdString id); virtual void expand_interfaces(RTLIL::Design *design, const dict &local_interfaces); virtual bool reprocess_if_necessary(RTLIL::Design *design); @@ -2109,32 +2121,37 @@ public: return design->selected_member(name, member->name); } - RTLIL::Wire* wire(const RTLIL::IdString &id) { + RTLIL::Wire* wire(RTLIL::IdString id) { auto it = wires_.find(id); return it == wires_.end() ? nullptr : it->second; } - RTLIL::Cell* cell(const RTLIL::IdString &id) { + RTLIL::Cell* cell(RTLIL::IdString id) { auto it = cells_.find(id); return it == cells_.end() ? nullptr : it->second; } - const RTLIL::Wire* wire(const RTLIL::IdString &id) const{ + const RTLIL::Wire* wire(RTLIL::IdString id) const{ auto it = wires_.find(id); return it == wires_.end() ? nullptr : it->second; } - const RTLIL::Cell* cell(const RTLIL::IdString &id) const { + const RTLIL::Cell* cell(RTLIL::IdString id) const { auto it = cells_.find(id); return it == cells_.end() ? nullptr : it->second; } RTLIL::ObjRange wires() { return RTLIL::ObjRange(&wires_, &refcount_wires_); } + int wires_size() const { return wires_.size(); } + RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; } RTLIL::ObjRange cells() { return RTLIL::ObjRange(&cells_, &refcount_cells_); } + int cells_size() const { return cells_.size(); } + RTLIL::Cell* cell_at(int index) const { return cells_.element(index)->second; } void add(RTLIL::Binding *binding); // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const pool &wires); void remove(RTLIL::Cell *cell); + void remove(RTLIL::Memory *memory); void remove(RTLIL::Process *process); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); @@ -2381,6 +2398,7 @@ public: RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = ""); RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = ""); + std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON static std::map *get_all_modules(void); #endif @@ -2434,6 +2452,7 @@ public: return zero_index + start_offset; } + std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON static std::map *get_all_wires(void); #endif @@ -2451,6 +2470,8 @@ struct RTLIL::Memory : public RTLIL::NamedObject Memory(); int width, start_offset, size; + + std::string to_rtlil_str() const; #ifdef YOSYS_ENABLE_PYTHON ~Memory(); static std::map *get_all_memorys(void); @@ -2479,23 +2500,23 @@ public: dict parameters; // access cell ports - bool hasPort(const RTLIL::IdString &portname) const; - void unsetPort(const RTLIL::IdString &portname); - void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal); - const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const; + bool hasPort(RTLIL::IdString portname) const; + void unsetPort(RTLIL::IdString portname); + void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const; const dict &connections() const; // information about cell ports bool known() const; - bool input(const RTLIL::IdString &portname) const; - bool output(const RTLIL::IdString &portname) const; - PortDir port_dir(const RTLIL::IdString &portname) const; + bool input(RTLIL::IdString portname) const; + bool output(RTLIL::IdString portname) const; + PortDir port_dir(RTLIL::IdString portname) const; // access cell parameters - bool hasParam(const RTLIL::IdString ¶mname) const; - void unsetParam(const RTLIL::IdString ¶mname); - void setParam(const RTLIL::IdString ¶mname, RTLIL::Const value); - const RTLIL::Const &getParam(const RTLIL::IdString ¶mname) const; + bool hasParam(RTLIL::IdString paramname) const; + void unsetParam(RTLIL::IdString paramname); + void setParam(RTLIL::IdString paramname, RTLIL::Const value); + const RTLIL::Const &getParam(RTLIL::IdString paramname) const; void sort(); void check(); @@ -2509,6 +2530,8 @@ public: template void rewrite_sigspecs(T &functor); template void rewrite_sigspecs2(T &functor); + std::string to_rtlil_str() const; + #ifdef YOSYS_ENABLE_PYTHON static std::map *get_all_cells(void); #endif @@ -2587,6 +2610,7 @@ public: template void rewrite_sigspecs(T &functor); template void rewrite_sigspecs2(T &functor); RTLIL::Process *clone() const; + std::string to_rtlil_str() const; }; diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index d0561f880..5f74b3380 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -526,7 +526,7 @@ void RTLIL::Module::bufNormalize() pending_deleted_cells.clear(); } -void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) +void RTLIL::Cell::unsetPort(RTLIL::IdString portname) { RTLIL::SigSpec signal; auto conn_it = connections_.find(portname); @@ -586,7 +586,7 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) } } -void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal) +void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) { auto r = connections_.insert(portname); auto conn_it = r.first; diff --git a/kernel/satgen.h b/kernel/satgen.h index 7815847b3..c53d20fe0 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -59,6 +59,7 @@ struct SatSolver struct ezSatPtr : public std::unique_ptr { ezSatPtr() : unique_ptr(yosys_satsolver->create()) { } + explicit ezSatPtr(SatSolver *solver) : unique_ptr((solver ? solver : yosys_satsolver)->create()) { } }; struct SatGen diff --git a/kernel/scopeinfo.cc b/kernel/scopeinfo.cc index 7ed9ebf33..59dd746b5 100644 --- a/kernel/scopeinfo.cc +++ b/kernel/scopeinfo.cc @@ -97,13 +97,13 @@ static const char *attr_prefix(ScopeinfoAttrs attrs) } } -bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id) +bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id) { log_assert(scopeinfo->type == ID($scopeinfo)); return scopeinfo->has_attribute(attr_prefix(attrs) + RTLIL::unescape_id(id)); } -RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id) +RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id) { log_assert(scopeinfo->type == ID($scopeinfo)); auto found = scopeinfo->attributes.find(attr_prefix(attrs) + RTLIL::unescape_id(id)); diff --git a/kernel/scopeinfo.h b/kernel/scopeinfo.h index 3bc1a8162..a3939b903 100644 --- a/kernel/scopeinfo.h +++ b/kernel/scopeinfo.h @@ -433,10 +433,10 @@ enum class ScopeinfoAttrs { }; // Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute. -bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id); +bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id); // Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell. -RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id); +RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id); // Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell. dict scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs); diff --git a/kernel/threading.cc b/kernel/threading.cc index 49fddaa7c..dcc044c89 100644 --- a/kernel/threading.cc +++ b/kernel/threading.cc @@ -3,6 +3,20 @@ YOSYS_NAMESPACE_BEGIN +static int init_max_threads() +{ + const char *v = getenv("YOSYS_MAX_THREADS"); + if (v == nullptr) + return INT32_MAX; + return atoi(v); +} + +static int get_max_threads() +{ + static int max_threads = init_max_threads(); + return max_threads; +} + void DeferredLogs::flush() { for (auto &m : logs) @@ -12,10 +26,11 @@ void DeferredLogs::flush() YOSYS_NAMESPACE_PREFIX log("%s", m.text.c_str()); } -int ThreadPool::pool_size(int reserved_cores, int max_threads) +int ThreadPool::pool_size(int reserved_cores, int max_worker_threads) { #ifdef YOSYS_ENABLE_THREADS - int num_threads = std::min(std::thread::hardware_concurrency() - reserved_cores, max_threads); + int available_threads = std::min(std::thread::hardware_concurrency(), get_max_threads()); + int num_threads = std::min(available_threads - reserved_cores, max_worker_threads); return std::max(0, num_threads); #else return 0; diff --git a/kernel/threading.h b/kernel/threading.h index c34abf850..b8cd62f87 100644 --- a/kernel/threading.h +++ b/kernel/threading.h @@ -127,9 +127,9 @@ class ThreadPool public: // Computes the number of worker threads to use. // `reserved_cores` cores are set aside for other threads (e.g. work on the main thread). - // `max_threads` --- don't return more workers than this. + // `max_worker_threads` --- don't return more workers than this. // The result may be 0. - static int pool_size(int reserved_cores, int max_threads); + static int pool_size(int reserved_cores, int max_worker_threads); // Create a pool of threads running the given closure (parameterized by thread number). // `pool_size` must be the result of a `pool_size()` call. diff --git a/kernel/yosys.cc b/kernel/yosys.cc index adfd8d808..0ccff7c5d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -19,6 +19,7 @@ #include "kernel/yosys.h" #include "kernel/newcelltypes.h" +#include "kernel/log.h" #ifdef YOSYS_ENABLE_READLINE # include @@ -80,7 +81,7 @@ extern "C" PyObject* PyInit_pyosys(); YOSYS_NAMESPACE_BEGIN -int autoidx = 1; +Autoidx autoidx(1); int yosys_xtrace = 0; bool yosys_write_versions = true; const char* yosys_maybe_version() { @@ -108,9 +109,30 @@ uint32_t Hasher::fudge = 0; std::string yosys_share_dirname; std::string yosys_abc_executable; +bool Multithreading::active_ = false; + void init_share_dirname(); void init_abc_executable_name(); +Multithreading::Multithreading() { + log_assert(!active_); + active_ = true; +} + +Multithreading::~Multithreading() { + log_assert(active_); + active_ = false; +} + +void Autoidx::ensure_at_least(int v) { + value = std::max(value, v); +} + +int Autoidx::operator++(int) { + log_assert(!Multithreading::active()); + return value++; +} + void memhasher_on() { #if defined(__linux__) || defined(__FreeBSD__) @@ -151,7 +173,7 @@ void yosys_banner() log("\n"); log(" /----------------------------------------------------------------------------\\\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); - log(" | Copyright (C) 2012 - 2025 Claire Xenia Wolf |\n"); + log(" | Copyright (C) 2012 - 2026 Claire Xenia Wolf |\n"); log(" | Distributed under an ISC-like license, type \"license\" to see terms |\n"); log(" \\----------------------------------------------------------------------------/\n"); log(" %s\n", yosys_maybe_version()); diff --git a/kernel/yosys.h b/kernel/yosys.h index b455ad496..9f5a16a9c 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -81,6 +81,7 @@ extern std::set yosys_input_files, yosys_output_files; // from kernel/version_*.o (cc source generated from Makefile) extern const char *yosys_version_str; +extern const char *yosys_git_hash_str; const char* yosys_maybe_version(); // from passes/cmds/design.cc diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index 2374182ee..47dae5473 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -267,7 +267,30 @@ int ceil_log2(int x) YS_ATTRIBUTE(const); template int GetSize(const T &obj) { return obj.size(); } inline int GetSize(RTLIL::Wire *wire); -extern int autoidx; +// When multiple threads are accessing RTLIL, one of these guard objects +// must exist. +struct Multithreading +{ + Multithreading(); + ~Multithreading(); + // Returns true when multiple threads are accessing RTLIL. + // autoidx cannot be used during such times. + // IdStrings cannot be created during such times. + static bool active() { return active_; } +private: + static bool active_; +}; + +struct Autoidx { + Autoidx(int value) : value(value) {} + operator int() const { return value; } + void ensure_at_least(int v); + int operator++(int); +private: + int value; +}; + +extern Autoidx autoidx; extern int yosys_xtrace; extern bool yosys_write_versions; @@ -276,8 +299,8 @@ RTLIL::IdString new_id_suffix(std::string_view file, int line, std::string_view #define NEW_ID \ YOSYS_NAMESPACE_PREFIX RTLIL::IdString::new_autoidx_with_prefix([](std::string_view func) -> const std::string * { \ - static const std::string *prefix = YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func); \ - return prefix; \ + static std::unique_ptr prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \ + return prefix.get(); \ }(__FUNCTION__)) #define NEW_ID_SUFFIX(suffix) \ YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix) diff --git a/libs/ezsat/ezcmdline.cc b/libs/ezsat/ezcmdline.cc new file mode 100644 index 000000000..57800591c --- /dev/null +++ b/libs/ezsat/ezcmdline.cc @@ -0,0 +1,92 @@ + +#include "ezcmdline.h" + +#include "../../kernel/yosys.h" + +ezCmdlineSAT::ezCmdlineSAT(const std::string &cmd) : command(cmd) {} + +ezCmdlineSAT::~ezCmdlineSAT() {} + +bool ezCmdlineSAT::solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) +{ +#if !defined(YOSYS_DISABLE_SPAWN) + const std::string tempdir_name = Yosys::make_temp_dir(Yosys::get_base_tmpdir() + "/yosys-sat-XXXXXX"); + const std::string cnf_filename = Yosys::stringf("%s/problem.cnf", tempdir_name.c_str()); + const std::string sat_command = Yosys::stringf("%s %s", command.c_str(), cnf_filename.c_str()); + FILE *dimacs = fopen(cnf_filename.c_str(), "w"); + if (dimacs == nullptr) { + Yosys::log_cmd_error("Failed to create CNF file `%s`.\n", cnf_filename.c_str()); + } + + std::vector modelIdx; + for (auto id : modelExpressions) + modelIdx.push_back(bind(id)); + std::vector> extraClauses; + for (auto id : assumptions) + extraClauses.push_back({bind(id)}); + + printDIMACS(dimacs, false, extraClauses); + fclose(dimacs); + + bool status_sat = false; + bool status_unsat = false; + std::vector values; + + auto line_callback = [&](const std::string &line) { + if (line.empty()) { + return; + } + if (line[0] == 's') { + if (line.substr(0, 5) == "s SAT") { + status_sat = true; + } + if (line.substr(0, 7) == "s UNSAT") { + status_unsat = true; + } + return; + } + if (line[0] == 'v') { + std::stringstream ss(line.substr(1)); + int lit; + while (ss >> lit) { + if (lit == 0) { + return; + } + bool val = lit >= 0; + int ind = lit >= 0 ? lit - 1 : -lit - 1; + if (Yosys::GetSize(values) <= ind) { + values.resize(ind + 1); + } + values[ind] = val; + } + } + }; + int return_code = Yosys::run_command(sat_command, line_callback); + if (return_code != 0 && return_code != 10 && return_code != 20) { + Yosys::log_cmd_error("Shell command failed!\n"); + } + + modelValues.clear(); + modelValues.resize(modelIdx.size()); + + if (!status_sat && !status_unsat) { + solverTimeoutStatus = true; + } + if (!status_sat) { + return false; + } + + for (size_t i = 0; i < modelIdx.size(); i++) { + int idx = modelIdx[i]; + bool refvalue = true; + + if (idx < 0) + idx = -idx, refvalue = false; + + modelValues[i] = (values.at(idx - 1) == refvalue); + } + return true; +#else + Yosys::log_error("SAT solver command not available in this build!\n"); +#endif +} diff --git a/libs/ezsat/ezcmdline.h b/libs/ezsat/ezcmdline.h new file mode 100644 index 000000000..8ec8c7043 --- /dev/null +++ b/libs/ezsat/ezcmdline.h @@ -0,0 +1,36 @@ +/* + * ezSAT -- A simple and easy to use CNF generator for SAT solvers + * + * Copyright (C) 2013 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef EZSATCOMMAND_H +#define EZSATCOMMAND_H + +#include "ezsat.h" + +class ezCmdlineSAT : public ezSAT +{ +private: + std::string command; + +public: + ezCmdlineSAT(const std::string &cmd); + virtual ~ezCmdlineSAT(); + bool solver(const std::vector &modelExpressions, std::vector &modelValues, const std::vector &assumptions) override; +}; + +#endif diff --git a/libs/ezsat/ezminisat.cc b/libs/ezsat/ezminisat.cc index 30df625cb..1f4b8855f 100644 --- a/libs/ezsat/ezminisat.cc +++ b/libs/ezsat/ezminisat.cc @@ -103,7 +103,7 @@ bool ezMiniSAT::solver(const std::vector &modelExpressions, std::vector 0) { if (alarmHandlerTimeout == 0) - solverTimoutStatus = true; + solverTimeoutStatus = true; alarm(0); sigaction(SIGALRM, &old_sig_action, NULL); alarm(old_alarm_timeout); diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 20a210abe..8e3114705 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -54,7 +54,7 @@ ezSAT::ezSAT() cnfClausesCount = 0; solverTimeout = 0; - solverTimoutStatus = false; + solverTimeoutStatus = false; literal("CONST_TRUE"); literal("CONST_FALSE"); @@ -1222,10 +1222,15 @@ ezSATvec ezSAT::vec(const std::vector &vec) return ezSATvec(*this, vec); } -void ezSAT::printDIMACS(FILE *f, bool verbose) const +void ezSAT::printDIMACS(FILE *f, bool verbose, const std::vector> &extraClauses) const { + if (f == nullptr) { + fprintf(stderr, "Usage error: printDIMACS() must not be called with a null FILE pointer\n"); + abort(); + } + if (cnfConsumed) { - fprintf(stderr, "Usage error: printDIMACS() must not be called after cnfConsumed()!"); + fprintf(stderr, "Usage error: printDIMACS() must not be called after cnfConsumed()!\n"); abort(); } @@ -1259,8 +1264,10 @@ void ezSAT::printDIMACS(FILE *f, bool verbose) const std::vector> all_clauses; getFullCnf(all_clauses); assert(cnfClausesCount == int(all_clauses.size())); + for (auto c : extraClauses) + all_clauses.push_back(c); - fprintf(f, "p cnf %d %d\n", cnfVariableCount, cnfClausesCount); + fprintf(f, "p cnf %d %d\n", cnfVariableCount, (int) all_clauses.size()); int maxClauseLen = 0; for (auto &clause : all_clauses) maxClauseLen = std::max(int(clause.size()), maxClauseLen); diff --git a/libs/ezsat/ezsat.h b/libs/ezsat/ezsat.h index 7f3bdf68d..445c8edba 100644 --- a/libs/ezsat/ezsat.h +++ b/libs/ezsat/ezsat.h @@ -78,7 +78,7 @@ protected: public: int solverTimeout; - bool solverTimoutStatus; + bool solverTimeoutStatus; ezSAT(); virtual ~ezSAT(); @@ -153,8 +153,8 @@ public: solverTimeout = newTimeoutSeconds; } - bool getSolverTimoutStatus() { - return solverTimoutStatus; + bool getSolverTimeoutStatus() { + return solverTimeoutStatus; } // manage CNF (usually only accessed by SAT solvers) @@ -295,7 +295,7 @@ public: // printing CNF and internal state - void printDIMACS(FILE *f, bool verbose = false) const; + void printDIMACS(FILE *f, bool verbose = false, const std::vector> &extraClauses = std::vector>()) const; void printInternalState(FILE *f) const; // more sophisticated constraints (designed to be used directly with assume(..)) diff --git a/libs/subcircuit/subcircuit.cc b/libs/subcircuit/subcircuit.cc index 60f27fd55..dfec80254 100644 --- a/libs/subcircuit/subcircuit.cc +++ b/libs/subcircuit/subcircuit.cc @@ -912,6 +912,10 @@ class SubCircuit::SolverWorker bool pruneEnumerationMatrix(std::vector> &enumerationMatrix, const GraphData &needle, const GraphData &haystack, int &nextRow, bool allowOverlap) { bool didSomething = true; + + // Map of j:[i where j is used] + std::map> usedNodes; + while (didSomething) { nextRow = -1; @@ -923,13 +927,23 @@ class SubCircuit::SolverWorker didSomething = true; else if (!allowOverlap && haystack.usedNodes[j]) didSomething = true; - else + else { newRow.insert(j); + usedNodes[j].insert(i); // Store the needle index by haystack node index + } } + + // This indicates there are no available haystack nodes to assign to the needle if (newRow.size() == 0) return false; + + // If there are multiple needles assigned to the haystack node, the solution is invalid + if (newRow.size() == 1 && usedNodes[*newRow.begin()].size() > 1) + return false; + if (newRow.size() >= 2 && (nextRow < 0 || needle.adjMatrix.at(nextRow).size() < needle.adjMatrix.at(i).size())) nextRow = i; + enumerationMatrix[i].swap(newRow); } } diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh index 228003bad..42a690ce6 100644 --- a/misc/create_vcxsrc.sh +++ b/misc/create_vcxsrc.sh @@ -1,9 +1,8 @@ #!/bin/bash set -ex -vcxsrc="$1-$2" +vcxsrc="$1" yosysver="$2" -gitsha="$3" rm -rf YosysVS-Tpl-v2.zip YosysVS wget https://github.com/YosysHQ/yosys/releases/download/resources/YosysVS-Tpl-v2.zip @@ -33,7 +32,6 @@ popd head -n$n "$vcxsrc"/YosysVS/YosysVS.vcxproj egrep '\.(h|hh|hpp|inc)$' srcfiles.txt | sed 's,.*,,' egrep -v '\.(h|hh|hpp|inc)$' srcfiles.txt | sed 's,.*,,' - echo '' tail -n +$((n+1)) "$vcxsrc"/YosysVS/YosysVS.vcxproj } > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new @@ -48,9 +46,6 @@ mkdir -p "$vcxsrc"/yosys tar -cf - -T srcfiles.txt | tar -xf - -C "$vcxsrc"/yosys cp -r share "$vcxsrc"/ -echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys" \ - "$yosysver (git sha1 $gitsha, Visual Studio)\"; }" > "$vcxsrc"/yosys/kernel/version.cc - cat > "$vcxsrc"/readme-git.txt << EOT Want to use a git working copy for the yosys source code? Open "Git Bash" in this directory and run: diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 14ea9c52a..5e2994a53 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -5,6 +5,7 @@ endif OBJS += passes/cmds/add.o OBJS += passes/cmds/delete.o OBJS += passes/cmds/design.o +OBJS += passes/cmds/design_equal.o OBJS += passes/cmds/select.o OBJS += passes/cmds/show.o OBJS += passes/cmds/viz.o @@ -27,7 +28,6 @@ OBJS += passes/cmds/logcmd.o OBJS += passes/cmds/tee.o OBJS += passes/cmds/write_file.o OBJS += passes/cmds/connwrappers.o -OBJS += passes/cmds/cover.o OBJS += passes/cmds/trace.o OBJS += passes/cmds/plugin.o OBJS += passes/cmds/check.o @@ -37,6 +37,7 @@ OBJS += passes/cmds/chformal.o OBJS += passes/cmds/chtype.o OBJS += passes/cmds/blackbox.o OBJS += passes/cmds/ltp.o +OBJS += passes/cmds/linux_perf.o ifeq ($(DISABLE_SPAWN),0) OBJS += passes/cmds/bugpoint.o endif diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc deleted file mode 100644 index 7f217329c..000000000 --- a/passes/cmds/cover.cc +++ /dev/null @@ -1,163 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2014 Claire Xenia Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/log_help.h" -#include - -#ifndef _WIN32 -# include -#else -# include -#endif - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct CoverPass : public Pass { - CoverPass() : Pass("cover", "print code coverage counters") { - internal(); - } - bool formatted_help() override { - auto *help = PrettyHelp::get_current(); - help->set_group("passes/status"); - return false; - } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" cover [options] [pattern]\n"); - log("\n"); - log("Print the code coverage counters collected using the cover() macro in the Yosys\n"); - log("C++ code. This is useful to figure out what parts of Yosys are utilized by a\n"); - log("test bench.\n"); - log("\n"); - log(" -q\n"); - log(" Do not print output to the normal destination (console and/or log file)\n"); - log("\n"); - log(" -o file\n"); - log(" Write output to this file, truncate if exists.\n"); - log("\n"); - log(" -a file\n"); - log(" Write output to this file, append if exists.\n"); - log("\n"); - log(" -d dir\n"); - log(" Write output to a newly created file in the specified directory.\n"); - log("\n"); - log("When one or more pattern (shell wildcards) are specified, then only counters\n"); - log("matching at least one pattern are printed.\n"); - log("\n"); - log("\n"); - log("It is also possible to instruct Yosys to print the coverage counters on program\n"); - log("exit to a file using environment variables:\n"); - log("\n"); - log(" YOSYS_COVER_DIR=\"{dir-name}\" yosys {args}\n"); - log("\n"); - log(" This will create a file (with an auto-generated name) in this\n"); - log(" directory and write the coverage counters to it.\n"); - log("\n"); - log(" YOSYS_COVER_FILE=\"{file-name}\" yosys {args}\n"); - log("\n"); - log(" This will append the coverage counters to the specified file.\n"); - log("\n"); - log("\n"); - log("Hint: Use the following AWK command to consolidate Yosys coverage files:\n"); - log("\n"); - log(" gawk '{ p[$3] = $1; c[$3] += $2; } END { for (i in p)\n"); - log(" printf \"%%-60s %%10d %%s\\n\", p[i], c[i], i; }' {files} | sort -k3\n"); - log("\n"); - log("\n"); - log("Coverage counters are only available in Yosys for Linux.\n"); - log("\n"); - } - void execute(std::vector args, RTLIL::Design *design) override - { - std::vector out_files; - std::vector patterns; - bool do_log = true; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-q") { - do_log = false; - continue; - } - if ((args[argidx] == "-o" || args[argidx] == "-a" || args[argidx] == "-d") && argidx+1 < args.size()) { - const char *open_mode = args[argidx] == "-a" ? "a+" : "w"; - const std::string &filename = args[++argidx]; - FILE *f = nullptr; - if (args[argidx-1] == "-d") { - #if defined(_WIN32) || defined(__wasm) - log_cmd_error("The 'cover -d' option is not supported on this platform.\n"); - #else - char filename_buffer[4096]; - snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", filename.c_str(), getpid()); - f = fdopen(mkstemps(filename_buffer, 4), "w"); - #endif - } else { - f = fopen(filename.c_str(), open_mode); - } - if (f == NULL) { - for (auto f : out_files) - fclose(f); - log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx]); - } - out_files.push_back(f); - continue; - } - break; - } - while (argidx < args.size() && args[argidx].compare(0, 1, "-") != 0) - patterns.push_back(args[argidx++]); - extra_args(args, argidx, design); - - if (do_log) { - log_header(design, "Printing code coverage counters.\n"); - log("\n"); - } - -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) - for (auto &it : get_coverage_data()) { - if (!patterns.empty()) { - for (auto &p : patterns) - if (patmatch(p.c_str(), it.first.c_str())) - goto pattern_match; - continue; - } - pattern_match: - for (auto f : out_files) - fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); - if (do_log) - log("%-60s %10d %s\n", it.second.first, it.second.second, it.first); - } -#else - for (auto f : out_files) - fclose(f); - - log_cmd_error("This version of Yosys was not built with support for code coverage counters.\n"); -#endif - - for (auto f : out_files) - fclose(f); - } -} CoverPass; - -PRIVATE_NAMESPACE_END diff --git a/passes/cmds/design_equal.cc b/passes/cmds/design_equal.cc new file mode 100644 index 000000000..d5f0d617a --- /dev/null +++ b/passes/cmds/design_equal.cc @@ -0,0 +1,367 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/rtlil.h" + +YOSYS_NAMESPACE_BEGIN + +class ModuleComparator +{ + RTLIL::Module *mod_a; + RTLIL::Module *mod_b; + +public: + ModuleComparator(RTLIL::Module *mod_a, RTLIL::Module *mod_b) : mod_a(mod_a), mod_b(mod_b) {} + + template + [[noreturn]] void error(FmtString...> fmt, const Args &... args) + { + formatted_error(fmt.format(args...)); + } + [[noreturn]] + void formatted_error(std::string err) + { + log("Module A: %s\n", log_id(mod_a->name)); + log_module(mod_a, " "); + log("Module B: %s\n", log_id(mod_b->name)); + log_module(mod_b, " "); + log_cmd_error("Designs are different: %s\n", err); + } + + bool compare_sigbit(const RTLIL::SigBit &a, const RTLIL::SigBit &b) + { + if (a.wire == nullptr && b.wire == nullptr) + return a.data == b.data; + if (a.wire != nullptr && b.wire != nullptr) + return a.wire->name == b.wire->name && a.offset == b.offset; + return false; + } + + bool compare_sigspec(const RTLIL::SigSpec &a, const RTLIL::SigSpec &b) + { + if (a.size() != b.size()) return false; + auto it_a = a.begin(), it_b = b.begin(); + for (; it_a != a.end(); ++it_a, ++it_b) { + if (!compare_sigbit(*it_a, *it_b)) return false; + } + return true; + } + + std::string compare_attributes(const RTLIL::AttrObject *a, const RTLIL::AttrObject *b) + { + for (const auto &it : a->attributes) { + if (b->attributes.count(it.first) == 0) + return "missing attribute " + std::string(log_id(it.first)) + " in second design"; + if (it.second != b->attributes.at(it.first)) + return "attribute " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first)); + } + for (const auto &it : b->attributes) + if (a->attributes.count(it.first) == 0) + return "missing attribute " + std::string(log_id(it.first)) + " in first design"; + return ""; + } + + std::string compare_wires(const RTLIL::Wire *a, const RTLIL::Wire *b) + { + if (a->name != b->name) + return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (a->width != b->width) + return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width); + if (a->start_offset != b->start_offset) + return "start_offset mismatch: " + std::to_string(a->start_offset) + " != " + std::to_string(b->start_offset); + if (a->port_id != b->port_id) + return "port_id mismatch: " + std::to_string(a->port_id) + " != " + std::to_string(b->port_id); + if (a->port_input != b->port_input) + return "port_input mismatch: " + std::to_string(a->port_input) + " != " + std::to_string(b->port_input); + if (a->port_output != b->port_output) + return "port_output mismatch: " + std::to_string(a->port_output) + " != " + std::to_string(b->port_output); + if (a->upto != b->upto) + return "upto mismatch: " + std::to_string(a->upto) + " != " + std::to_string(b->upto); + if (a->is_signed != b->is_signed) + return "is_signed mismatch: " + std::to_string(a->is_signed) + " != " + std::to_string(b->is_signed); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + return ""; + } + + void check_wires() + { + for (const auto &it : mod_a->wires_) { + if (mod_b->wires_.count(it.first) == 0) + error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty()) + error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + } + for (const auto &it : mod_b->wires_) + if (mod_a->wires_.count(it.first) == 0) + error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b) + { + if (a->name != b->name) + return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (a->width != b->width) + return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width); + if (a->start_offset != b->start_offset) + return "start_offset mismatch: " + std::to_string(a->start_offset) + " != " + std::to_string(b->start_offset); + if (a->size != b->size) + return "size mismatch: " + std::to_string(a->size) + " != " + std::to_string(b->size); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + return ""; + } + + std::string compare_cells(const RTLIL::Cell *a, const RTLIL::Cell *b) + { + if (a->name != b->name) + return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (a->type != b->type) + return "type mismatch: " + std::string(log_id(a->type)) + " != " + log_id(b->type); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + + for (const auto &it : a->parameters) { + if (b->parameters.count(it.first) == 0) + return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in second design"; + if (it.second != b->parameters.at(it.first)) + return "parameter mismatch: " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first)); + } + for (const auto &it : b->parameters) + if (a->parameters.count(it.first) == 0) + return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in first design"; + + for (const auto &it : a->connections()) { + if (b->connections().count(it.first) == 0) + return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in second design"; + if (!compare_sigspec(it.second, b->connections().at(it.first))) + return "connection " + std::string(log_id(it.first)) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first)); + } + for (const auto &it : b->connections()) + if (a->connections().count(it.first) == 0) + return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in first design"; + + return ""; + } + + void check_cells() + { + for (const auto &it : mod_a->cells_) { + if (mod_b->cells_.count(it.first) == 0) + error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty()) + error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + } + for (const auto &it : mod_b->cells_) + if (mod_a->cells_.count(it.first) == 0) + error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + void check_memories() + { + for (const auto &it : mod_a->memories) { + if (mod_b->memories.count(it.first) == 0) + error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty()) + error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch); + } + for (const auto &it : mod_b->memories) + if (mod_a->memories.count(it.first) == 0) + error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b) + { + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) return mismatch; + + if (a->compare.size() != b->compare.size()) + return "compare size mismatch: " + std::to_string(a->compare.size()) + " != " + std::to_string(b->compare.size()); + for (size_t i = 0; i < a->compare.size(); i++) + if (!compare_sigspec(a->compare[i], b->compare[i])) + return "compare " + std::to_string(i) + " mismatch: " + log_signal(a->compare[i]) + " != " + log_signal(b->compare[i]); + + if (a->actions.size() != b->actions.size()) + return "actions size mismatch: " + std::to_string(a->actions.size()) + " != " + std::to_string(b->actions.size()); + for (size_t i = 0; i < a->actions.size(); i++) { + if (!compare_sigspec(a->actions[i].first, b->actions[i].first)) + return "action " + std::to_string(i) + " first mismatch: " + log_signal(a->actions[i].first) + " != " + log_signal(b->actions[i].first); + if (!compare_sigspec(a->actions[i].second, b->actions[i].second)) + return "action " + std::to_string(i) + " second mismatch: " + log_signal(a->actions[i].second) + " != " + log_signal(b->actions[i].second); + } + + if (a->switches.size() != b->switches.size()) + return "switches size mismatch: " + std::to_string(a->switches.size()) + " != " + std::to_string(b->switches.size()); + for (size_t i = 0; i < a->switches.size(); i++) + if (std::string mismatch = compare_switch_rules(a->switches[i], b->switches[i]); !mismatch.empty()) + return "switch " + std::to_string(i) + " " + mismatch; + + return ""; + } + + std::string compare_switch_rules(const RTLIL::SwitchRule *a, const RTLIL::SwitchRule *b) + { + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + if (!compare_sigspec(a->signal, b->signal)) + return "signal mismatch: " + log_signal(a->signal) + " != " + log_signal(b->signal); + + if (a->cases.size() != b->cases.size()) + return "cases size mismatch: " + std::to_string(a->cases.size()) + " != " + std::to_string(b->cases.size()); + for (size_t i = 0; i < a->cases.size(); i++) + if (std::string mismatch = compare_case_rules(a->cases[i], b->cases[i]); !mismatch.empty()) + return "case " + std::to_string(i) + " " + mismatch; + + return ""; + } + + std::string compare_sync_rules(const RTLIL::SyncRule *a, const RTLIL::SyncRule *b) + { + if (a->type != b->type) + return "type mismatch: " + std::to_string(a->type) + " != " + std::to_string(b->type); + if (!compare_sigspec(a->signal, b->signal)) + return "signal mismatch: " + log_signal(a->signal) + " != " + log_signal(b->signal); + if (a->actions.size() != b->actions.size()) + return "actions size mismatch: " + std::to_string(a->actions.size()) + " != " + std::to_string(b->actions.size()); + for (size_t i = 0; i < a->actions.size(); i++) { + if (!compare_sigspec(a->actions[i].first, b->actions[i].first)) + return "action " + std::to_string(i) + " first mismatch: " + log_signal(a->actions[i].first) + " != " + log_signal(b->actions[i].first); + if (!compare_sigspec(a->actions[i].second, b->actions[i].second)) + return "action " + std::to_string(i) + " second mismatch: " + log_signal(a->actions[i].second) + " != " + log_signal(b->actions[i].second); + } + if (a->mem_write_actions.size() != b->mem_write_actions.size()) + return "mem_write_actions size mismatch: " + std::to_string(a->mem_write_actions.size()) + " != " + std::to_string(b->mem_write_actions.size()); + for (size_t i = 0; i < a->mem_write_actions.size(); i++) { + const auto &ma = a->mem_write_actions[i]; + const auto &mb = b->mem_write_actions[i]; + if (ma.memid != mb.memid) + return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + log_id(ma.memid) + " != " + log_id(mb.memid); + if (!compare_sigspec(ma.address, mb.address)) + return "mem_write_actions " + std::to_string(i) + " address mismatch: " + log_signal(ma.address) + " != " + log_signal(mb.address); + if (!compare_sigspec(ma.data, mb.data)) + return "mem_write_actions " + std::to_string(i) + " data mismatch: " + log_signal(ma.data) + " != " + log_signal(mb.data); + if (!compare_sigspec(ma.enable, mb.enable)) + return "mem_write_actions " + std::to_string(i) + " enable mismatch: " + log_signal(ma.enable) + " != " + log_signal(mb.enable); + if (ma.priority_mask != mb.priority_mask) + return "mem_write_actions " + std::to_string(i) + " priority_mask mismatch: " + log_const(ma.priority_mask) + " != " + log_const(mb.priority_mask); + if (std::string mismatch = compare_attributes(&ma, &mb); !mismatch.empty()) + return "mem_write_actions " + std::to_string(i) + " " + mismatch; + } + return ""; + } + + std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b) + { + if (a->name != b->name) return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name); + if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) + return mismatch; + if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty()) + return "case rule " + mismatch; + if (a->syncs.size() != b->syncs.size()) + return "sync count mismatch: " + std::to_string(a->syncs.size()) + " != " + std::to_string(b->syncs.size()); + for (size_t i = 0; i < a->syncs.size(); i++) + if (std::string mismatch = compare_sync_rules(a->syncs[i], b->syncs[i]); !mismatch.empty()) + return "sync " + std::to_string(i) + " " + mismatch; + return ""; + } + + void check_processes() + { + for (auto &it : mod_a->processes) { + if (mod_b->processes.count(it.first) == 0) + error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first)); + if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty()) + error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str()); + } + for (auto &it : mod_b->processes) + if (mod_a->processes.count(it.first) == 0) + error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first)); + } + + void check_connections() + { + const auto &conns_a = mod_a->connections(); + const auto &conns_b = mod_b->connections(); + if (conns_a.size() != conns_b.size()) { + error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size()); + } else { + for (size_t i = 0; i < conns_a.size(); i++) { + if (!compare_sigspec(conns_a[i].first, conns_b[i].first)) + error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first)); + if (!compare_sigspec(conns_a[i].second, conns_b[i].second)) + error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second)); + } + } + } + + void check() + { + if (mod_a->name != mod_b->name) + error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name)); + if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty()) + error("Module %s %s.\n", log_id(mod_a->name), mismatch); + check_wires(); + check_cells(); + check_memories(); + check_connections(); + check_processes(); + } +}; + +struct DesignEqualPass : public Pass { + DesignEqualPass() : Pass("design_equal", "check if two designs are the same") { } + void help() override + { + log("\n"); + log(" design_equal \n"); + log("\n"); + log("Compare the current design with the design previously saved under the given\n"); + log("name. Abort with an error if the designs are different.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + if (args.size() != 2) + log_cmd_error("Missing argument.\n"); + + std::string check_name = args[1]; + if (saved_designs.count(check_name) == 0) + log_cmd_error("No saved design '%s' found!\n", check_name.c_str()); + + RTLIL::Design *other = saved_designs.at(check_name); + + for (auto &it : design->modules_) { + RTLIL::Module *mod = it.second; + if (!other->has(mod->name)) + log_error("Second design missing module %s.\n", log_id(mod->name)); + + ModuleComparator cmp(mod, other->module(mod->name)); + cmp.check(); + } + for (auto &it : other->modules_) { + RTLIL::Module *mod = it.second; + if (!design->has(mod->name)) + log_error("First design missing module %s.\n", log_id(mod->name)); + } + + log("Designs are identical.\n"); + } +} DesignEqualPass; + +YOSYS_NAMESPACE_END diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index 7d1c42a79..b10f50502 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -77,7 +77,7 @@ struct ExampleDtPass : public Pass auto enqueue = [&](DriveSpec const &spec) { int index = queue(spec); if (index == GetSize(graph_nodes)) - graph_nodes.emplace_back(compute_graph.add(ID($pending).id_string(), index).index()); + graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index()); //if (index >= GetSize(graph_nodes)) return compute_graph[graph_nodes[index]]; }; diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc index d49cd360a..a928e5d58 100644 --- a/passes/cmds/icell_liberty.cc +++ b/passes/cmds/icell_liberty.cc @@ -163,7 +163,6 @@ struct IcellLiberty : Pass { log_header(d, "Executing ICELL_LIBERTY pass.\n"); size_t argidx; - IdString naming_attr; std::string liberty_filename; auto liberty_file = std::make_unique(); diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc new file mode 100644 index 000000000..2b75a3a79 --- /dev/null +++ b/passes/cmds/linux_perf.cc @@ -0,0 +1,102 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Claire Xenia Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/log_help.h" + +#include +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#ifdef __linux__ +#include +struct LinuxPerf : public Pass { + LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") { + internal(); + } + bool formatted_help() override + { + auto *help = PrettyHelp::get_current(); + + auto content_root = help->get_root(); + + content_root->usage("linux_perf [on|off]"); + + content_root->paragraph( + "This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs." + "YOSYS_PERF_CTL and YOSYS_PERF_ACK must point to Linux perf control FIFOs." + ); + content_root->paragraph("Example shell command line:"); + content_root->codeblock( + "mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n" + "YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n" + " perf record --latency --delay=-1 \\\n" + " --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys \\\n" + " -dt -p \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n" + ); + + return true; + } + void execute(std::vector args, RTLIL::Design *) override + { + if (args.size() > 2) + cmd_error(args, 2, "Unexpected argument."); + + std::string_view ctl_msg; + if (args.size() == 2) { + if (args[1] == "on") + ctl_msg = "enable\n"; + else if (args[1] == "off") + ctl_msg = "disable\n"; + else + cmd_error(args, 1, "Unexpected argument."); + } + + const char *ctl_fifo = std::getenv("YOSYS_PERF_CTL"); + if (!ctl_fifo) + log_error("YOSYS_PERF_CTL environment variable not set."); + const char *ack_fifo = std::getenv("YOSYS_PERF_ACK"); + if (!ack_fifo) + log_error("YOSYS_PERF_ACK environment variable not set."); + + int ctl_fd = open(ctl_fifo, O_WRONLY); + if (ctl_fd < 0) + log_error("Failed to open YOSYS_PERF_CTL."); + int ack_fd = open(ack_fifo, O_RDONLY); + if (ack_fd < 0) + log_error("Failed to open YOSYS_PERF_ACK."); + int result = write(ctl_fd, ctl_msg.data(), ctl_msg.size()); + if (result != static_cast(ctl_msg.size())) + log_error("Failed to write to YOSYS_PERF_CTL."); + char buffer[64]; + result = read(ack_fd, buffer, sizeof(buffer)); + close(ctl_fd); + close(ack_fd); + if (result <= 0) + log_error("Failed to read from YOSYS_PERF_ACK."); + if (strcmp(buffer, "ack\n") != 0) + log_error("YOSYS_PERF_ACK did not return 'ack'."); + } +} LinuxPerf; +#endif + +PRIVATE_NAMESPACE_END diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index e4e78b0ea..6a1fab072 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -45,7 +45,7 @@ struct PrintAttrsPass : public Pass { return stringf("%*s", indent, ""); } - static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) { + static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) { if (x.flags & RTLIL::CONST_FLAG_STRING) log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string()); else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED) diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index f64ce943c..24ab5cfd8 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -37,7 +37,7 @@ struct ScratchpadPass : public Pass { log("\n"); log(" scratchpad [options]\n"); log("\n"); - log("This pass allows to read and modify values from the scratchpad of the current\n"); + log("This pass allows reading and modifying values from the scratchpad of the current\n"); log("design. Options:\n"); log("\n"); log(" -get \n"); diff --git a/passes/cmds/sdc/sdc.cc b/passes/cmds/sdc/sdc.cc index eb1951665..635aad016 100644 --- a/passes/cmds/sdc/sdc.cc +++ b/passes/cmds/sdc/sdc.cc @@ -8,6 +8,11 @@ #include #include +#if TCL_MAJOR_VERSION < 9 +typedef int YS_Tcl_Size; +#else +typedef Tcl_Size YS_Tcl_Size; +#endif USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -160,7 +165,12 @@ struct SdcObjects { if (!top) log_error("Top module couldn't be determined. Check 'top' attribute usage"); for (auto port : top->ports) { - design_ports.push_back(std::make_pair(port.str().substr(1), top->wire(port))); + RTLIL::Wire *wire = top->wire(port); + if (!wire) { + // This should not be possible. See https://github.com/YosysHQ/yosys/pull/5594#issue-3791198573 + log_error("Port %s doesn't exist", log_id(port)); + } + design_ports.push_back(std::make_pair(port.str().substr(1), wire)); } std::list hierarchy{}; sniff_module(hierarchy, top); @@ -432,7 +442,7 @@ static size_t get_node_count(Tcl_Interp* interp) { std::vector> gather_nested_calls(Tcl_Interp* interp) { Tcl_Obj* listObj = Tcl_GetVar2Ex(interp, "sdc_calls", nullptr, TCL_GLOBAL_ONLY); - int listLength; + YS_Tcl_Size listLength; std::vector> sdc_calls; if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) { @@ -442,7 +452,7 @@ std::vector> gather_nested_calls(Tcl_Interp* interp) { if (Tcl_ListObjIndex(interp, listObj, i, &subListObj) != TCL_OK) { log_error("broken list of lists\n"); } - int subListLength; + YS_Tcl_Size subListLength; if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) { // Valid list - extract elements for (int j = 0; j < subListLength; j++) { diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 539a2f651..2359efe03 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -570,7 +570,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char ct.setup(design); if (pos < int(arg.size()) && arg[pos] == '*') { - levels = 1000000; + levels = 1'000'000; pos++; } else if (pos < int(arg.size()) && '0' <= arg[pos] && arg[pos] <= '9') { diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 39ed8e60e..222fecaca 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override + void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } @@ -115,16 +115,45 @@ struct DebugPass : public Pass { log("\n"); log("Execute the specified command with debug log messages enabled\n"); log("\n"); + log(" debug -on\n"); + log(" debug -off\n"); + log("\n"); + log("Enable or disable debug log messages globally\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; + bool mode_on = false; + bool mode_off = false; + for (argidx = 1; argidx < args.size(); argidx++) { - // .. parse options .. + if (args[argidx] == "-on") { + mode_on = true; + continue; + } + if (args[argidx] == "-off") { + mode_off = true; + continue; + } break; } + if (mode_on && mode_off) + log_cmd_error("Cannot specify both -on and -off\n"); + + if (mode_on) { + log_force_debug++; + return; + } + + if (mode_off) { + if (log_force_debug > 0) + log_force_debug--; + return; + } + log_force_debug++; try { diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index c3c10363b..87adaa26d 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -39,6 +39,7 @@ struct PassOptions { bool no_auto_distributed; bool no_auto_block; bool no_auto_huge; + bool force_params; double logic_cost_rom; double logic_cost_ram; }; @@ -1859,7 +1860,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); } else { cell->setPort(stringf("\\PORT_%s_WR_EN", name), hw_wren); - if (cfg.def->byte != 0 && cfg.def->width_mode != WidthMode::Single) + if (cfg.def->byte != 0 && (cfg.def->width_mode != WidthMode::Single || opts.force_params)) cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren)); } } @@ -2068,8 +2069,10 @@ void MemMapping::emit(const MemConfig &cfg) { std::vector cells; for (int rd = 0; rd < cfg.repl_d; rd++) { Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid, rp, rd), cfg.def->id); - if (cfg.def->width_mode == WidthMode::Global) + if (cfg.def->width_mode == WidthMode::Global || opts.force_params) cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]); + if (opts.force_params) + cell->setParam(ID::ABITS, cfg.def->abits); if (cfg.def->widthscale) { std::vector val; for (auto &bit: init_swz.bits[rd]) @@ -2179,6 +2182,9 @@ struct MemoryLibMapPass : public Pass { log(" Disables automatic mapping of given kind of RAMs. Manual mapping\n"); log(" (using ram_style or other attributes) is still supported.\n"); log("\n"); + log(" -force-params\n"); + log(" Always generate memories with WIDTH and ABITS parameters.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { @@ -2188,6 +2194,7 @@ struct MemoryLibMapPass : public Pass { opts.no_auto_distributed = false; opts.no_auto_block = false; opts.no_auto_huge = false; + opts.force_params = false; opts.logic_cost_ram = 1.0; opts.logic_cost_rom = 1.0/16.0; log_header(design, "Executing MEMORY_LIBMAP pass (mapping memories to cells).\n"); @@ -2214,6 +2221,10 @@ struct MemoryLibMapPass : public Pass { opts.no_auto_huge = true; continue; } + if (args[argidx] == "-force-params") { + opts.force_params = true; + continue; + } if (args[argidx] == "-logic-cost-rom" && argidx+1 < args.size()) { opts.logic_cost_rom = strtod(args[++argidx].c_str(), nullptr); continue; diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 426d9a79a..5dee824ff 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -23,6 +23,7 @@ OBJS += passes/opt/opt_lut_ins.o OBJS += passes/opt/opt_ffinv.o OBJS += passes/opt/pmux2shiftx.o OBJS += passes/opt/muxpack.o +OBJS += passes/opt/opt_balance_tree.o OBJS += passes/opt/peepopt.o GENFILES += passes/opt/peepopt_pm.h diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index ec5760cd9..983437e64 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -193,7 +193,6 @@ struct OptPass : public Pass { } design->optimize(); - design->sort(); design->check(); log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)"); diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc new file mode 100644 index 000000000..129a27376 --- /dev/null +++ b/passes/opt/opt_balance_tree.cc @@ -0,0 +1,379 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * 2019 Eddie Hung + * 2024 Akash Levy + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + + +struct OptBalanceTreeWorker { + // Module and signal map + Module *module; + SigMap sigmap; + + // Counts of each cell type that are getting balanced + dict cell_count; + + // Check if cell is of the right type and has matching input/output widths + // Only allow cells with "natural" output widths (no truncation) to prevent + // equivalence issues when rebalancing (see YosysHQ/yosys#5605) + bool is_right_type(Cell* cell, IdString cell_type) { + if (cell->type != cell_type) + return false; + + int y_width = cell->getParam(ID::Y_WIDTH).as_int(); + int a_width = cell->getParam(ID::A_WIDTH).as_int(); + int b_width = cell->getParam(ID::B_WIDTH).as_int(); + + // Calculate the "natural" output width for this operation + int natural_width; + if (cell_type == ID($add)) { + // Addition produces max(A_WIDTH, B_WIDTH) + 1 (for carry bit) + natural_width = std::max(a_width, b_width) + 1; + } else if (cell_type == ID($mul)) { + // Multiplication produces A_WIDTH + B_WIDTH + natural_width = a_width + b_width; + } else { + // Logic operations ($and/$or/$xor) produce max(A_WIDTH, B_WIDTH) + natural_width = std::max(a_width, b_width); + } + + // Only allow cells where Y_WIDTH >= natural width (no truncation) + // This prevents rebalancing chains where truncation semantics matter + return y_width >= natural_width; + } + + // Create a balanced binary tree from a vector of source signals + SigSpec create_balanced_tree(vector &sources, IdString cell_type, Cell* cell) { + // Base case: if we have no sources, return an empty signal + if (sources.size() == 0) + return SigSpec(); + + // Base case: if we have only one source, return it + if (sources.size() == 1) + return sources[0]; + + // Base case: if we have two sources, create a single cell + if (sources.size() == 2) { + // Create a new cell of the same type + Cell* new_cell = module->addCell(NEW_ID, cell_type); + + // Copy attributes from reference cell + new_cell->attributes = cell->attributes; + + // Create output wire + int out_width = cell->getParam(ID::Y_WIDTH).as_int(); + if (cell_type == ID($add)) + out_width = max(sources[0].size(), sources[1].size()) + 1; + else if (cell_type == ID($mul)) + out_width = sources[0].size() + sources[1].size(); + Wire* out_wire = module->addWire(NEW_ID, out_width); + + // Connect ports and fix up parameters + new_cell->setPort(ID::A, sources[0]); + new_cell->setPort(ID::B, sources[1]); + new_cell->setPort(ID::Y, out_wire); + new_cell->fixup_parameters(); + new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); + new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); + + // Update count and return output wire + cell_count[cell_type]++; + return out_wire; + } + + // Recursive case: split sources into two groups and create subtrees + int mid = (sources.size() + 1) / 2; + vector left_sources(sources.begin(), sources.begin() + mid); + vector right_sources(sources.begin() + mid, sources.end()); + + SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell); + SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell); + + // Create a cell to combine the two subtrees + Cell* new_cell = module->addCell(NEW_ID, cell_type); + + // Copy attributes from reference cell + new_cell->attributes = cell->attributes; + + // Create output wire + int out_width = cell->getParam(ID::Y_WIDTH).as_int(); + if (cell_type == ID($add)) + out_width = max(left_tree.size(), right_tree.size()) + 1; + else if (cell_type == ID($mul)) + out_width = left_tree.size() + right_tree.size(); + Wire* out_wire = module->addWire(NEW_ID, out_width); + + // Connect ports and fix up parameters + new_cell->setPort(ID::A, left_tree); + new_cell->setPort(ID::B, right_tree); + new_cell->setPort(ID::Y, out_wire); + new_cell->fixup_parameters(); + new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); + new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); + + // Update count and return output wire + cell_count[cell_type]++; + return out_wire; + } + + OptBalanceTreeWorker(Module *module, const vector cell_types) : module(module), sigmap(module) { + // Do for each cell type + for (auto cell_type : cell_types) { + // Index all of the nets in the module + dict sig_to_driver; + dict> sig_to_sink; + for (auto cell : module->selected_cells()) + { + for (auto &conn : cell->connections()) + { + if (cell->output(conn.first)) + sig_to_driver[sigmap(conn.second)] = cell; + + if (cell->input(conn.first)) + { + SigSpec sig = sigmap(conn.second); + if (sig_to_sink.count(sig) == 0) + sig_to_sink[sig] = pool(); + sig_to_sink[sig].insert(cell); + } + } + } + + // Need to check if any wires connect to module ports + pool input_port_sigs; + pool output_port_sigs; + for (auto wire : module->selected_wires()) + if (wire->port_input || wire->port_output) { + SigSpec sig = sigmap(wire); + for (auto bit : sig) { + if (wire->port_input) + input_port_sigs.insert(bit); + if (wire->port_output) + output_port_sigs.insert(bit); + } + } + + // Actual logic starts here + pool consumed_cells; + for (auto cell : module->selected_cells()) + { + // If consumed or not the correct type, skip + if (consumed_cells.count(cell) || !is_right_type(cell, cell_type)) + continue; + + // BFS, following all chains until they hit a cell of a different type + // Pick the longest one + auto y = sigmap(cell->getPort(ID::Y)); + pool sinks; + pool current_loads = sig_to_sink[y]; + pool next_loads; + while (!current_loads.empty()) + { + // Find each sink and see what they are + for (auto x : current_loads) + { + // If not the correct type, don't follow any further + // (but add the originating cell to the list of sinks) + if (!is_right_type(x, cell_type)) + { + sinks.insert(cell); + continue; + } + + auto xy = sigmap(x->getPort(ID::Y)); + + // If this signal drives a port, add it to the sinks + // (even though it may not be the end of a chain) + for (auto bit : xy) { + if (output_port_sigs.count(bit) && !consumed_cells.count(x)) { + sinks.insert(x); + break; + } + } + + // Search signal's fanout + auto& next = sig_to_sink[xy]; + for (auto z : next) + next_loads.insert(z); + } + + // If we couldn't find any downstream loads, stop. + // Create a reduction for each of the max-length chains we found + if (next_loads.empty()) + { + for (auto s : current_loads) + { + // Not one of our gates? Don't follow any further + if (!is_right_type(s, cell_type)) + continue; + + sinks.insert(s); + } + break; + } + + // Otherwise, continue down the chain + current_loads = next_loads; + next_loads.clear(); + } + + // We have our list of sinks, now go tree balance the chains + for (auto head_cell : sinks) + { + // Avoid duplication if we already were covered + if (consumed_cells.count(head_cell)) + continue; + + // Get sources of the chain + dict sources; + dict signeds; + int inner_cells = 0; + std::deque bfs_queue = {head_cell}; + while (bfs_queue.size()) + { + Cell* x = bfs_queue.front(); + bfs_queue.pop_front(); + + for (IdString port: {ID::A, ID::B}) { + auto sig = sigmap(x->getPort(port)); + Cell* drv = sig_to_driver[sig]; + bool drv_ok = drv && is_right_type(drv, cell_type); + for (auto bit : sig) { + if (input_port_sigs.count(bit) && !consumed_cells.count(drv)) { + drv_ok = false; + break; + } + } + if (drv_ok) { + inner_cells++; + bfs_queue.push_back(drv); + } else { + sources[sig]++; + signeds[sig] = x->getParam(port == ID::A ? ID::A_SIGNED : ID::B_SIGNED).as_bool(); + } + } + } + + if (inner_cells) + { + // Create a tree + log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", log_id(head_cell), GetSize(sources), inner_cells); + + // Build a vector of all source signals + vector source_signals; + vector signed_flags; + for (auto &source : sources) { + for (int i = 0; i < source.second; i++) { + source_signals.push_back(source.first); + signed_flags.push_back(signeds[source.first]); + } + } + + // If not all signed flags are the same, do not balance + if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) { + continue; + } + + // Create the balanced tree + SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell); + + // Connect the tree output to the head cell's output + SigSpec head_output = sigmap(head_cell->getPort(ID::Y)); + int connect_width = std::min(head_output.size(), tree_output.size()); + module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width)); + if (head_output.size() > tree_output.size()) { + SigBit sext_bit = head_cell->getParam(ID::A_SIGNED).as_bool() ? head_output[connect_width - 1] : State::S0; + module->connect(head_output.extract(connect_width, head_output.size() - connect_width), SigSpec(sext_bit, head_output.size() - connect_width)); + } + + // Mark consumed cell for removal + consumed_cells.insert(head_cell); + } + } + } + + // Remove all consumed cells, which now have been replaced by trees + for (auto cell : consumed_cells) + module->remove(cell); + } + } +}; + +struct OptBalanceTreePass : public Pass { + OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$add/$mul cascades to trees") { } + void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" opt_balance_tree [options] [selection]\n"); + log("\n"); + log("This pass converts cascaded chains of $and/$or/$xor/$add/$mul cells into\n"); + log("trees of cells to improve timing.\n"); + log("\n"); + log(" -arith\n"); + log(" only convert arithmetic cells.\n"); + log("\n"); + log(" -logic\n"); + log(" only convert logic cells.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override { + log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n"); + log_experimental("open_balance_tree"); + + // Handle arguments + size_t argidx; + vector cell_types = {ID($and), ID($or), ID($xor), ID($add), ID($mul)}; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-arith") { + cell_types = {ID($add), ID($mul)}; + continue; + } + if (args[argidx] == "-logic") { + cell_types = {ID($and), ID($or), ID($xor)}; + continue; + } + break; + } + extra_args(args, argidx, design); + + // Count of all cells that were packed + dict cell_count; + for (auto module : design->selected_modules()) { + OptBalanceTreeWorker worker(module, cell_types); + for (auto cell : worker.cell_count) { + cell_count[cell.first] += cell.second; + } + } + + // Log stats + for (auto cell_type : cell_types) + log("Converted %d %s cells into trees.\n", cell_count[cell_type], log_id(cell_type)); + + // Clean up + Yosys::run_pass("clean -purge"); + } +} OptBalanceTreePass; + +PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index d824fd2db..72d22ddd3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -275,6 +275,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo return conns.check_any(s2); } + if (w1 == w2) + return s2.offset < s1.offset; + if (w1->port_output != w2->port_output) return w2->port_output; @@ -347,7 +350,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); - if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) + if (compare_signals(s2, s1, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } } @@ -471,8 +474,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase(ID::init); else wire->attributes.at(ID::init) = initval; - used_signals.add(new_conn.first); - used_signals.add(new_conn.second); module->connect(new_conn); } @@ -713,7 +714,6 @@ struct OptCleanPass : public Pass { log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); design->optimize(); - design->sort(); design->check(); keep_cache.reset(); @@ -773,7 +773,6 @@ struct CleanPass : public Pass { log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); design->optimize(); - design->sort(); design->check(); keep_cache.reset(); diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 04bcec835..90ace69e5 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -26,6 +26,7 @@ #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" +#include "kernel/pattern.h" #include "passes/techmap/simplemap.h" #include #include @@ -45,34 +46,80 @@ struct OptDffOptions struct OptDffWorker { const OptDffOptions &opt; - Module *module; + + // Cell to port bit index typedef std::pair cell_int_t; - SigMap sigmap; + + SigMap sigmap; // Signal aliasing FfInitVals initvals; - dict bitusers; - dict bit2mux; + dict bitusers; // Signal sink count + dict bit2mux; // Signal bit to driving MUX - typedef std::map pattern_t; - typedef std::set patterns_t; - typedef std::pair ctrl_t; - typedef std::set ctrls_t; - - // Used as a queue. std::vector dff_cells; - OptDffWorker(const OptDffOptions &opt, Module *mod) : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod) { + bool is_active(SigBit sig, bool pol) const { + return sig == (pol ? State::S1 : State::S0); + } + + bool is_inactive(SigBit sig, bool pol) const { + return sig == (pol ? State::S0 : State::S1); + } + + bool is_always_active(SigBit sig, bool pol) const { + return is_active(sig, pol) || (!opt.keepdc && sig == State::Sx); + } + + bool is_always_inactive(SigBit sig, bool pol) const { + return is_inactive(sig, pol) || (!opt.keepdc && sig == State::Sx); + } + + SigSpec create_not(SigSpec a, bool is_fine) { + if (is_fine) + return module->NotGate(NEW_ID, a); + else + return module->Not(NEW_ID, a); + } + + SigSpec create_and(SigSpec a, SigSpec b, bool is_fine) { + if (is_fine) + return module->AndGate(NEW_ID, a, b); + else + return module->And(NEW_ID, a, b); + } + + void create_mux_to_output(SigSpec a, SigSpec b, SigSpec sel, SigSpec y, bool pol, bool is_fine) { + if (is_fine) { + if (pol) + module->addMuxGate(NEW_ID, a, b, sel, y); + else + module->addMuxGate(NEW_ID, b, a, sel, y); + } else { + if (pol) + module->addMux(NEW_ID, a, b, sel, y); + else + module->addMux(NEW_ID, b, a, sel, y); + } + } + + void maybe_simplemap(Cell *c, bool make_gates) { + if (make_gates) { + simplemap(module, c); + module->remove(c); + } + } + + OptDffWorker(const OptDffOptions &opt, Module *mod) + : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod) + { // Gathering two kinds of information here for every sigmapped SigBit: - // - // - bitusers: how many users it has (muxes will only be merged into FFs if this is 1, making the FF the only user) + // - bitusers: how many users it has (muxes will only be merged into FFs if the FF is the only user) // - bit2mux: the mux cell and bit index that drives it, if any for (auto wire : module->wires()) - { if (wire->port_output) for (auto bit : sigmap(wire)) bitusers[bit]++; - } for (auto cell : module->cells()) { if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { @@ -83,39 +130,36 @@ struct OptDffWorker for (auto conn : cell->connections()) { bool is_output = cell->output(conn.first); - if (!is_output || !cell->known()) { + if (!is_output || !cell->known()) for (auto bit : sigmap(conn.second)) bitusers[bit]++; - } } if (module->design->selected(module, cell) && cell->is_builtin_ff()) dff_cells.push_back(cell); } - } State combine_const(State a, State b) { - if (a == State::Sx && !opt.keepdc) - return b; - if (b == State::Sx && !opt.keepdc) - return a; - if (a == b) - return a; + // Combine constants: returns Sm if values conflict + if (a == State::Sx && !opt.keepdc) return b; + if (b == State::Sx && !opt.keepdc) return a; + if (a == b) return a; return State::Sm; } patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path) { + // Find feedback paths D->Q through mux tree, replacing found paths with Sx patterns_t ret; if (d == q) { ret.insert(path); - return ret; + return ret; // Feedback found } if (bit2mux.count(d) == 0 || bitusers[d] > 1) - return ret; + return ret; // D not driven by MUX / MUX drives multiple loads cell_int_t mbit = bit2mux.at(d); RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A)); @@ -123,11 +167,10 @@ struct OptDffWorker RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S)); int width = GetSize(sig_a), index = mbit.second; - for (int i = 0; i < GetSize(sig_s); i++) - if (path.count(sig_s[i]) && path.at(sig_s[i])) - { + // Traverse MUX tree + for (int i = 0; i < GetSize(sig_s); i++) { + if (path.count(sig_s[i]) && path.at(sig_s[i])) { ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path); - if (sig_b[i*width + index] == q) { RTLIL::SigSpec s = mbit.first->getPort(ID::B); s[i*width + index] = RTLIL::Sx; @@ -136,18 +179,19 @@ struct OptDffWorker return ret; } + } + // Specific path wasn't forced, explore the 0 branch pattern_t path_else = path; - - for (int i = 0; i < GetSize(sig_s); i++) - { + for (int i = 0; i < GetSize(sig_s); i++) { if (path.count(sig_s[i])) continue; pattern_t path_this = path; - path_else[sig_s[i]] = false; - path_this[sig_s[i]] = true; + path_else[sig_s[i]] = false; // Assume S=0 for 'else' path + path_this[sig_s[i]] = true; // Assume S=1 for 'this' path + // Selected when S=1 for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this)) ret.insert(pat); @@ -158,6 +202,7 @@ struct OptDffWorker } } + // Selected when S=0 for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else)) ret.insert(pat); @@ -170,75 +215,17 @@ struct OptDffWorker return ret; } - void simplify_patterns(patterns_t& patterns) - { - auto new_patterns = patterns; - auto find_comp = [](const auto& left, const auto& right) -> std::optional { - std::optional ret; - for (const auto &pt: left) - if (right.count(pt.first) == 0) - return {}; - else if (right.at(pt.first) == pt.second) - continue; - else - if (ret) - return {}; - else - ret = pt.first; - return ret; - }; - - // remove complimentary patterns - bool optimized; - do { - optimized = false; - for (auto i = patterns.begin(); i != patterns.end(); i++) { - for (auto j = std::next(i, 1); j != patterns.end(); j++) { - const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; - auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - - const auto complimentary_var = find_comp(left, right); - - if (complimentary_var && new_patterns.count(right)) { - new_patterns.erase(right); - right.erase(complimentary_var.value()); - new_patterns.insert(right); - optimized = true; - } - } - } - patterns = new_patterns; - } while(optimized); - - // remove redundant patterns - for (auto i = patterns.begin(); i != patterns.end(); ++i) { - for (auto j = std::next(i, 1); j != patterns.end(); ++j) { - const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; - const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i; - - bool redundant = true; - - for (const auto& pt : left) - if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second) - redundant = false; - if (redundant) - new_patterns.erase(right); - } - } - patterns = std::move(new_patterns); - } - ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates) { - if (patterns.empty() && GetSize(ctrls) == 1) { + if (patterns.empty() && GetSize(ctrls) == 1) return *ctrls.begin(); - } RTLIL::SigSpec or_input; - for (auto pat : patterns) - { + // Build logic for each feedback pattern + for (auto pat : patterns) { RTLIL::SigSpec s1, s2; + for (auto it : pat) { s1.append(it.first); s2.append(it.second); @@ -246,81 +233,500 @@ struct OptDffWorker RTLIL::SigSpec y = module->addWire(NEW_ID); RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - + maybe_simplemap(c, make_gates); or_input.append(y); } + + // Add existing control signals for (auto item : ctrls) { if (item.second) or_input.append(item.first); - else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(create_not(item.first, make_gates)); } - if (GetSize(or_input) == 0) - return ctrl_t(State::S1, true); - - if (GetSize(or_input) == 1) - return ctrl_t(or_input, true); + if (GetSize(or_input) == 0) return ctrl_t(State::S1, true); + if (GetSize(or_input) == 1) return ctrl_t(or_input, true); RTLIL::SigSpec y = module->addWire(NEW_ID); RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - + maybe_simplemap(c, make_gates); return ctrl_t(y, true); } ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates) { - if (GetSize(ctrls) == 1) { + if (GetSize(ctrls) == 1) return *ctrls.begin(); - } - - RTLIL::SigSpec or_input; bool final_pol = false; - for (auto item : ctrls) { + for (auto item : ctrls) if (item.second) final_pol = true; - } + RTLIL::SigSpec or_input; for (auto item : ctrls) { if (item.second == final_pol) or_input.append(item.first); - else if (make_gates) - or_input.append(module->NotGate(NEW_ID, item.first)); else - or_input.append(module->Not(NEW_ID, item.first)); + or_input.append(create_not(item.first, make_gates)); } RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - + RTLIL::Cell *c = final_pol + ? module->addReduceOr(NEW_ID, or_input, y) + : module->addReduceAnd(NEW_ID, or_input, y); + maybe_simplemap(c, make_gates); return ctrl_t(y, final_pol); } - bool run() { - // We have all the information we need, and the list of FFs to process as well. Do it. + bool signal_all_same(const SigSpec &sig) { + for (int i = 1; i < GetSize(sig); i++) + if (sig[i] != sig[0]) + return false; + return true; + } + + bool optimize_sr(FfData &ff, Cell *cell, bool &changed) + { + // Removes SR if CLR/SET are always active + // Converts SR to ARST if one pin is never active + // Converts SR to ARST if SET/CLR are inverses of eachother + bool sr_removed = false; + std::vector keep_bits; + + // Check for constant Set/Clear inputs + for (int i = 0; i < ff.width; i++) { + if (is_always_active(ff.sig_clr[i], ff.pol_clr)) { + initvals.remove_init(ff.sig_q[i]); + module->connect(ff.sig_q[i], State::S0); + log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n", + i, log_id(cell), log_id(cell->type), log_id(module)); + sr_removed = true; + } else if (is_always_active(ff.sig_set[i], ff.pol_set)) { + initvals.remove_init(ff.sig_q[i]); + if (!ff.pol_clr) + module->connect(ff.sig_q[i], ff.sig_clr[i]); + else if (ff.is_fine) + module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + else + module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); + log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", + i, log_id(cell), log_id(cell->type), log_id(module)); + sr_removed = true; + } else { + keep_bits.push_back(i); + } + } + + if (sr_removed) { + if (keep_bits.empty()) { + module->remove(cell); + return true; // FF fully removed + } + ff = ff.slice(keep_bits); + ff.cell = cell; + changed = true; + } + + // Try SR -> ARST conversion + bool clr_inactive = ff.pol_clr ? ff.sig_clr.is_fully_zero() : ff.sig_clr.is_fully_ones(); + bool set_inactive = ff.pol_set ? ff.sig_set.is_fully_zero() : ff.sig_set.is_fully_ones(); + + if (clr_inactive && signal_all_same(ff.sig_set)) { + log("Removing never-active CLR on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_sr = false; + ff.has_arst = true; + ff.pol_arst = ff.pol_set; + ff.sig_arst = ff.sig_set[0]; + ff.val_arst = Const(State::S1, ff.width); + changed = true; + } else if (set_inactive && signal_all_same(ff.sig_clr)) { + log("Removing never-active SET on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_sr = false; + ff.has_arst = true; + ff.pol_arst = ff.pol_clr; + ff.sig_arst = ff.sig_clr[0]; + ff.val_arst = Const(State::S0, ff.width); + changed = true; + } else if (ff.pol_clr == ff.pol_set) { + State val_neutral = ff.pol_set ? State::S0 : State::S1; + SigBit sig_arst = (ff.sig_clr[0] == val_neutral) ? ff.sig_set[0] : ff.sig_clr[0]; + + bool failed = false; + Const::Builder val_arst_builder(ff.width); + for (int i = 0; i < ff.width; i++) { + if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral) + val_arst_builder.push_back(State::S0); + else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral) + val_arst_builder.push_back(State::S1); + else { + failed = true; + break; + } + } + + if (!failed) { + log("Converting CLR/SET to ARST on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_sr = false; + ff.has_arst = true; + ff.val_arst = val_arst_builder.build(); + ff.sig_arst = sig_arst; + ff.pol_arst = ff.pol_clr; + changed = true; + } + } + + return false; + } + + bool optimize_aload(FfData &ff, Cell *cell, bool &changed) + { + // Removes unused Async Load + // Converts constant Async Load to ARST + if (is_always_inactive(ff.sig_aload, ff.pol_aload)) { + log("Removing never-active async load on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_aload = false; + changed = true; + return false; + } + + if (is_active(ff.sig_aload, ff.pol_aload)) { + // ALOAD always active + log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.remove(); + + if (ff.has_sr) { + SigSpec tmp; + if (ff.is_fine) { + tmp = ff.pol_set + ? module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set) + : module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); + + if (ff.pol_clr) + module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); + else + module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); + } else { + tmp = ff.pol_set + ? module->Or(NEW_ID, ff.sig_ad, ff.sig_set) + : module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); + + if (ff.pol_clr) + module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); + else + module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); + } + } else if (ff.has_arst) { + create_mux_to_output(ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, ff.pol_arst, ff.is_fine); + } else { + module->connect(ff.sig_q, ff.sig_ad); + } + return true; + } + + // AD is constant -> ARST + if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) { + log("Changing const-value async load to async reset on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_arst = true; + ff.has_aload = false; + ff.sig_arst = ff.sig_aload; + ff.pol_arst = ff.pol_aload; + ff.val_arst = ff.sig_ad.as_const(); + changed = true; + } + + return false; + } + + bool optimize_arst(FfData &ff, Cell *cell, bool &changed) + { + // Removes ARST if never active or replaces FF if always active + if (is_inactive(ff.sig_arst, ff.pol_arst)) { + log("Removing never-active ARST on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_arst = false; + changed = true; + } else if (is_always_active(ff.sig_arst, ff.pol_arst)) { + log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.remove(); + module->connect(ff.sig_q, ff.val_arst); + return true; + } + + return false; + } + + void optimize_srst(FfData &ff, Cell *cell, bool &changed) + { + // Removes SRST if never active or forces D to reset value if always active + if (is_inactive(ff.sig_srst, ff.pol_srst)) { + log("Removing never-active SRST on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_srst = false; + changed = true; + } else if (is_always_active(ff.sig_srst, ff.pol_srst)) { + log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_srst = false; + if (!ff.ce_over_srst) + ff.has_ce = false; + + ff.sig_d = ff.val_srst; + changed = true; + } + } + + void optimize_ce(FfData &ff, Cell *cell, bool &changed) + { + if (is_always_inactive(ff.sig_ce, ff.pol_ce)) { + if (ff.has_srst && !ff.ce_over_srst) { + log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.pol_ce = ff.pol_srst; + ff.sig_ce = ff.sig_srst; + ff.has_srst = false; + ff.sig_d = ff.val_srst; + changed = true; + } else if (!opt.keepdc || ff.val_init.is_fully_def()) { + log("Handling never-active EN on %s (%s) from module %s (removing D path).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_ce = ff.has_clk = ff.has_srst = false; + changed = true; + } else { + ff.sig_d = ff.sig_q; + ff.has_ce = ff.has_srst = false; + changed = true; + } + } else if (is_active(ff.sig_ce, ff.pol_ce)) { + log("Removing always-active EN on %s (%s) from module %s.\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_ce = false; + changed = true; + } + } + + void optimize_const_clk(FfData &ff, Cell *cell, bool &changed) + { + if (!opt.keepdc || ff.val_init.is_fully_def()) { + log("Handling const CLK on %s (%s) from module %s (removing D path).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_ce = ff.has_clk = ff.has_srst = false; + changed = true; + } else if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) { + ff.sig_d = ff.sig_q; + ff.has_ce = ff.has_srst = false; + changed = true; + } + } + + void optimize_d_equals_q(FfData &ff, Cell *cell, bool &changed) + { + // Detect feedback loops where D is hardwired to Q + if (ff.has_clk && ff.has_srst) { + log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n", + log_id(cell), log_id(cell->type), log_id(module)); + if (ff.has_ce && ff.ce_over_srst) { + SigSpec ce = ff.pol_ce ? ff.sig_ce : create_not(ff.sig_ce, ff.is_fine); + SigSpec srst = ff.pol_srst ? ff.sig_srst : create_not(ff.sig_srst, ff.is_fine); + ff.sig_ce = create_and(ce, srst, ff.is_fine); + ff.pol_ce = true; + } else { + ff.pol_ce = ff.pol_srst; + ff.sig_ce = ff.sig_srst; + } + + ff.has_ce = true; + ff.has_srst = false; + ff.sig_d = ff.val_srst; + changed = true; + } else if (!opt.keepdc || ff.val_init.is_fully_def()) { + log("Handling D = Q on %s (%s) from module %s (removing D path).\n", + log_id(cell), log_id(cell->type), log_id(module)); + ff.has_gclk = ff.has_clk = ff.has_ce = false; + changed = true; + } + } + + bool try_merge_srst(FfData &ff, Cell *cell, bool &changed) + { + std::map> groups; + std::vector remaining_indices; + Const::Builder val_srst_builder(ff.width); + + for (int i = 0; i < ff.width; i++) { + ctrls_t resets; + State reset_val = ff.has_srst ? ff.val_srst[i] : State::Sx; + + while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + cell_int_t mbit = bit2mux.at(ff.sig_d[i]); + if (GetSize(mbit.first->getPort(ID::S)) != 1) + break; + + SigBit s = mbit.first->getPort(ID::S); + SigBit a = mbit.first->getPort(ID::A)[mbit.second]; + SigBit b = mbit.first->getPort(ID::B)[mbit.second]; + + if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1)) + break; + + bool b_const = (b == State::S0 || b == State::S1); + bool a_const = (a == State::S0 || a == State::S1); + + if (b_const && (b == reset_val || reset_val == State::Sx) && a != ff.sig_q[i]) { + reset_val = b.data; + resets.insert(ctrl_t(s, true)); + ff.sig_d[i] = a; + } else if (a_const && (a == reset_val || reset_val == State::Sx) && b != ff.sig_q[i]) { + reset_val = a.data; + resets.insert(ctrl_t(s, false)); + ff.sig_d[i] = b; + } else { + break; + } + } + + if (!resets.empty()) { + if (ff.has_srst) + resets.insert(ctrl_t(ff.sig_srst, ff.pol_srst)); + + groups[resets].push_back(i); + } else { + remaining_indices.push_back(i); + } + + val_srst_builder.push_back(reset_val); + } + + Const val_srst = val_srst_builder.build(); + + for (auto &it : groups) { + FfData new_ff = ff.slice(it.second); + Const::Builder new_val_srst_builder(new_ff.width); + for (int i = 0; i < new_ff.width; i++) + new_val_srst_builder.push_back(val_srst[it.second[i]]); + + new_ff.val_srst = new_val_srst_builder.build(); + + ctrl_t srst = combine_resets(it.first, ff.is_fine); + new_ff.has_srst = true; + new_ff.sig_srst = srst.first; + new_ff.pol_srst = srst.second; + if (new_ff.has_ce) + new_ff.ce_over_srst = true; + + Cell *new_cell = new_ff.emit(); + if (new_cell) + dff_cells.push_back(new_cell); + + log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n", + log_id(cell), log_id(cell->type), log_id(module), + log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst)); + } + + if (remaining_indices.empty()) { + module->remove(cell); + return true; + } + + if (GetSize(remaining_indices) != ff.width) { + ff = ff.slice(remaining_indices); + ff.cell = cell; + changed = true; + } + + return false; + } + + bool try_merge_ce(FfData &ff, Cell *cell, bool &changed) + { + std::map, std::vector> groups; + std::vector remaining_indices; + + for (int i = 0; i < ff.width; i++) { + ctrls_t enables; + + while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { + cell_int_t mbit = bit2mux.at(ff.sig_d[i]); + if (GetSize(mbit.first->getPort(ID::S)) != 1) + break; + + SigBit s = mbit.first->getPort(ID::S); + SigBit a = mbit.first->getPort(ID::A)[mbit.second]; + SigBit b = mbit.first->getPort(ID::B)[mbit.second]; + + if (a == ff.sig_q[i]) { + enables.insert(ctrl_t(s, true)); + ff.sig_d[i] = b; + } else if (b == ff.sig_q[i]) { + enables.insert(ctrl_t(s, false)); + ff.sig_d[i] = a; + } else { + break; + } + } + + patterns_t patterns; + if (!opt.simple_dffe) + patterns = find_muxtree_feedback_patterns(ff.sig_d[i], ff.sig_q[i], pattern_t()); + + if (!patterns.empty() || !enables.empty()) { + if (ff.has_ce) + enables.insert(ctrl_t(ff.sig_ce, ff.pol_ce)); + simplify_patterns(patterns); + groups[std::make_pair(patterns, enables)].push_back(i); + } else { + remaining_indices.push_back(i); + } + } + + for (auto &it : groups) { + FfData new_ff = ff.slice(it.second); + ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine); + + new_ff.has_ce = true; + new_ff.sig_ce = en.first; + new_ff.pol_ce = en.second; + new_ff.ce_over_srst = false; + + Cell *new_cell = new_ff.emit(); + if (new_cell) + dff_cells.push_back(new_cell); + + log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n", + log_id(cell), log_id(cell->type), log_id(module), + log_signal(new_ff.sig_d), log_signal(new_ff.sig_q)); + } + + if (remaining_indices.empty()) { + module->remove(cell); + return true; + } + + if (GetSize(remaining_indices) != ff.width) { + ff = ff.slice(remaining_indices); + ff.cell = cell; + changed = true; + } + + return false; + } + + bool run() + { bool did_something = false; + while (!dff_cells.empty()) { Cell *cell = dff_cells.back(); dff_cells.pop_back(); - // Break down the FF into pieces. + FfData ff(&initvals, cell); bool changed = false; @@ -330,301 +736,35 @@ struct OptDffWorker continue; } - if (ff.has_sr) { - bool sr_removed = false; - std::vector keep_bits; - // Check for always-active S/R bits. - for (int i = 0; i < ff.width; i++) { - if (ff.sig_clr[i] == (ff.pol_clr ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_clr[i] == State::Sx)) { - // Always-active clear — connect Q bit to 0. - initvals.remove_init(ff.sig_q[i]); - module->connect(ff.sig_q[i], State::S0); - log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n", - i, log_id(cell), log_id(cell->type), log_id(module)); - sr_removed = true; - } else if (ff.sig_set[i] == (ff.pol_set ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_set[i] == State::Sx)) { - // Always-active set — connect Q bit to 1 if clear inactive, 0 if reset active. - initvals.remove_init(ff.sig_q[i]); - if (!ff.pol_clr) { - module->connect(ff.sig_q[i], ff.sig_clr[i]); - } else if (ff.is_fine) { - module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); - } else { - module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); - } - log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", - i, log_id(cell), log_id(cell->type), log_id(module)); - sr_removed = true; - } else { - keep_bits.push_back(i); - } - } - if (sr_removed) { - if (keep_bits.empty()) { - module->remove(cell); - did_something = true; - continue; - } - ff = ff.slice(keep_bits); - ff.cell = cell; - changed = true; - } - - if (ff.pol_clr ? ff.sig_clr.is_fully_zero() : ff.sig_clr.is_fully_ones()) { - // CLR is useless, try to kill it. - bool failed = false; - for (int i = 0; i < ff.width; i++) - if (ff.sig_set[i] != ff.sig_set[0]) - failed = true; - if (!failed) { - log("Removing never-active CLR on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_sr = false; - ff.has_arst = true; - ff.pol_arst = ff.pol_set; - ff.sig_arst = ff.sig_set[0]; - ff.val_arst = Const(State::S1, ff.width); - changed = true; - } - } else if (ff.pol_set ? ff.sig_set.is_fully_zero() : ff.sig_set.is_fully_ones()) { - // SET is useless, try to kill it. - bool failed = false; - for (int i = 0; i < ff.width; i++) - if (ff.sig_clr[i] != ff.sig_clr[0]) - failed = true; - if (!failed) { - log("Removing never-active SET on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_sr = false; - ff.has_arst = true; - ff.pol_arst = ff.pol_clr; - ff.sig_arst = ff.sig_clr[0]; - ff.val_arst = Const(State::S0, ff.width); - changed = true; - } - } else if (ff.pol_clr == ff.pol_set) { - // Try a more complex conversion to plain async reset. - State val_neutral = ff.pol_set ? State::S0 : State::S1; - SigBit sig_arst; - if (ff.sig_clr[0] == val_neutral) - sig_arst = ff.sig_set[0]; - else - sig_arst = ff.sig_clr[0]; - bool failed = false; - Const::Builder val_arst_builder(ff.width); - for (int i = 0; i < ff.width; i++) { - if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral) - val_arst_builder.push_back(State::S0); - else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral) - val_arst_builder.push_back(State::S1); - else { - failed = true; - break; - } - } - if (!failed) { - log("Converting CLR/SET to ARST on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_sr = false; - ff.has_arst = true; - ff.val_arst = val_arst_builder.build(); - ff.sig_arst = sig_arst; - ff.pol_arst = ff.pol_clr; - changed = true; - } - } + // Async control signal opt + if (ff.has_sr && optimize_sr(ff, cell, changed)) { + did_something = true; + continue; } - if (ff.has_aload) { - if (ff.sig_aload == (ff.pol_aload ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_aload == State::Sx)) { - // Always-inactive enable — remove. - log("Removing never-active async load on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_aload = false; - changed = true; - } else if (ff.sig_aload == (ff.pol_aload ? State::S1 : State::S0)) { - // Always-active enable. Make a comb circuit, nuke the FF/latch. - log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.remove(); - if (ff.has_sr) { - SigSpec tmp; - if (ff.is_fine) { - if (ff.pol_set) - tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set); - else - tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set); - if (ff.pol_clr) - module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q); - else - module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q); - } else { - if (ff.pol_set) - tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set); - else - tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set)); - if (ff.pol_clr) - module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q); - else - module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q); - } - } else if (ff.has_arst) { - if (ff.is_fine) { - if (ff.pol_arst) - module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q); - else - module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q); - } else { - if (ff.pol_arst) - module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q); - else - module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q); - } - } else { - module->connect(ff.sig_q, ff.sig_ad); - } - did_something = true; - continue; - } else if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) { - log("Changing const-value async load to async reset on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_arst = true; - ff.has_aload = false; - ff.sig_arst = ff.sig_aload; - ff.pol_arst = ff.pol_aload; - ff.val_arst = ff.sig_ad.as_const(); - changed = true; - } + if (ff.has_aload && optimize_aload(ff, cell, changed)) { + did_something = true; + continue; } - if (ff.has_arst) { - if (ff.sig_arst == (ff.pol_arst ? State::S0 : State::S1)) { - // Always-inactive reset — remove. - log("Removing never-active ARST on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_arst = false; - changed = true; - } else if (ff.sig_arst == (ff.pol_arst ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_arst == State::Sx)) { - // Always-active async reset — change to const driver. - log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.remove(); - module->connect(ff.sig_q, ff.val_arst); - did_something = true; - continue; - } + if (ff.has_arst && optimize_arst(ff, cell, changed)) { + did_something = true; + continue; } - if (ff.has_srst) { - if (ff.sig_srst == (ff.pol_srst ? State::S0 : State::S1)) { - // Always-inactive reset — remove. - log("Removing never-active SRST on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_srst = false; - changed = true; - } else if (ff.sig_srst == (ff.pol_srst ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_srst == State::Sx)) { - // Always-active sync reset — connect to D instead. - log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_srst = false; - if (!ff.ce_over_srst) - ff.has_ce = false; - ff.sig_d = ff.val_srst; - changed = true; - } - } + // Sync control signal opt + if (ff.has_srst) + optimize_srst(ff, cell, changed); - if (ff.has_ce) { - if (ff.sig_ce == (ff.pol_ce ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_ce == State::Sx)) { - // Always-inactive enable — remove. - if (ff.has_srst && !ff.ce_over_srst) { - log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n", - log_id(cell), log_id(cell->type), log_id(module)); - // FF with sync reset — connect the sync reset to D instead. - ff.pol_ce = ff.pol_srst; - ff.sig_ce = ff.sig_srst; - ff.has_srst = false; - ff.sig_d = ff.val_srst; - changed = true; - } else if (!opt.keepdc || ff.val_init.is_fully_def()) { - log("Handling never-active EN on %s (%s) from module %s (removing D path).\n", - log_id(cell), log_id(cell->type), log_id(module)); - // The D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver). - ff.has_ce = ff.has_clk = ff.has_srst = false; - changed = true; - } else { - // We need to keep the undefined initival around as such - ff.sig_d = ff.sig_q; - ff.has_ce = ff.has_srst = false; - changed = true; - } - } else if (ff.sig_ce == (ff.pol_ce ? State::S1 : State::S0)) { - // Always-active enable. Just remove it. - // For FF, just remove the useless enable. - log("Removing always-active EN on %s (%s) from module %s.\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_ce = false; - changed = true; - } - } + if (ff.has_ce) + optimize_ce(ff, cell, changed); - if (ff.has_clk && ff.sig_clk.is_fully_const()) { - if (!opt.keepdc || ff.val_init.is_fully_def()) { - // Const clock — the D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver). - log("Handling const CLK on %s (%s) from module %s (removing D path).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_ce = ff.has_clk = ff.has_srst = false; - changed = true; - } else { - // Const clock, but we need to keep the undefined initval around as such - if (ff.has_ce || ff.has_srst || ff.sig_d != ff.sig_q) { - ff.sig_d = ff.sig_q; - ff.has_ce = ff.has_srst = false; - changed = true; - } - } - } + if (ff.has_clk && ff.sig_clk.is_fully_const()) + optimize_const_clk(ff, cell, changed); - if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) { - // Q wrapped back to D, can be removed. - if (ff.has_clk && ff.has_srst) { - // FF with sync reset — connect the sync reset to D instead. - log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n", - log_id(cell), log_id(cell->type), log_id(module)); - if (ff.has_ce && ff.ce_over_srst) { - if (!ff.pol_ce) { - if (ff.is_fine) - ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce); - else - ff.sig_ce = module->Not(NEW_ID, ff.sig_ce); - } - if (!ff.pol_srst) { - if (ff.is_fine) - ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst); - else - ff.sig_srst = module->Not(NEW_ID, ff.sig_srst); - } - if (ff.is_fine) - ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst); - else - ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst); - ff.pol_ce = true; - } else { - ff.pol_ce = ff.pol_srst; - ff.sig_ce = ff.sig_srst; - } - ff.has_ce = true; - ff.has_srst = false; - ff.sig_d = ff.val_srst; - changed = true; - } else if (!opt.keepdc || ff.val_init.is_fully_def()) { - // The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver). - log("Handling D = Q on %s (%s) from module %s (removing D path).\n", - log_id(cell), log_id(cell->type), log_id(module)); - ff.has_gclk = ff.has_clk = ff.has_ce = false; - changed = true; - } - } + // Feedback (D=Q) opt + if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) + optimize_d_equals_q(ff, cell, changed); if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) { log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n", @@ -633,284 +773,157 @@ struct OptDffWorker changed = true; } - // The cell has been simplified as much as possible already. Now try to spice it up with enables / sync resets. + // Mux merging if (ff.has_clk && ff.sig_d != ff.sig_q) { - if (!ff.has_arst && !ff.has_sr && (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff) { - // Try to merge sync resets. - std::map> groups; - std::vector remaining_indices; - Const::Builder val_srst_builder(ff.width); + bool can_merge_srst = !ff.has_arst && !ff.has_sr && + (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff; - for (int i = 0 ; i < ff.width; i++) { - ctrls_t resets; - State reset_val = State::Sx; - if (ff.has_srst) - reset_val = ff.val_srst[i]; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { - cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) - break; - SigBit s = mbit.first->getPort(ID::S); - SigBit a = mbit.first->getPort(ID::A)[mbit.second]; - SigBit b = mbit.first->getPort(ID::B)[mbit.second]; - // Workaround for funny memory WE pattern. - if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1)) - break; - if ((b == State::S0 || b == State::S1) && (b == reset_val || reset_val == State::Sx)) { - // This is better handled by CE pattern. - if (a == ff.sig_q[i]) - break; - reset_val = b.data; - resets.insert(ctrl_t(s, true)); - ff.sig_d[i] = a; - } else if ((a == State::S0 || a == State::S1) && (a == reset_val || reset_val == State::Sx)) { - // This is better handled by CE pattern. - if (b == ff.sig_q[i]) - break; - reset_val = a.data; - resets.insert(ctrl_t(s, false)); - ff.sig_d[i] = b; - } else { - break; - } - } - - if (!resets.empty()) { - if (ff.has_srst) - resets.insert(ctrl_t(ff.sig_srst, ff.pol_srst)); - groups[resets].push_back(i); - } else - remaining_indices.push_back(i); - val_srst_builder.push_back(reset_val); - } - Const val_srst = val_srst_builder.build(); - - for (auto &it : groups) { - FfData new_ff = ff.slice(it.second); - Const::Builder new_val_srst_builder(new_ff.width); - for (int i = 0; i < new_ff.width; i++) { - int j = it.second[i]; - new_val_srst_builder.push_back(val_srst[j]); - } - new_ff.val_srst = new_val_srst_builder.build(); - ctrl_t srst = combine_resets(it.first, ff.is_fine); - - new_ff.has_srst = true; - new_ff.sig_srst = srst.first; - new_ff.pol_srst = srst.second; - if (new_ff.has_ce) - new_ff.ce_over_srst = true; - Cell *new_cell = new_ff.emit(); - if (new_cell) - dff_cells.push_back(new_cell); - log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n", - log_id(cell), log_id(cell->type), log_id(module), log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst)); - } - - if (remaining_indices.empty()) { - module->remove(cell); - did_something = true; - continue; - } else if (GetSize(remaining_indices) != ff.width) { - ff = ff.slice(remaining_indices); - ff.cell = cell; - changed = true; - } + if (can_merge_srst && try_merge_srst(ff, cell, changed)) { + did_something = true; + continue; } - if ((!ff.has_srst || !ff.has_ce || !ff.ce_over_srst) && !opt.nodffe) { - // Try to merge enables. - std::map, std::vector> groups; - std::vector remaining_indices; - for (int i = 0 ; i < ff.width; i++) { - // First, eat up as many simple muxes as possible. - ctrls_t enables; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { - cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) - break; - SigBit s = mbit.first->getPort(ID::S); - SigBit a = mbit.first->getPort(ID::A)[mbit.second]; - SigBit b = mbit.first->getPort(ID::B)[mbit.second]; - if (a == ff.sig_q[i]) { - enables.insert(ctrl_t(s, true)); - ff.sig_d[i] = b; - } else if (b == ff.sig_q[i]) { - enables.insert(ctrl_t(s, false)); - ff.sig_d[i] = a; - } else { - break; - } - } + bool can_merge_ce = (!ff.has_srst || !ff.has_ce || !ff.ce_over_srst) && !opt.nodffe; - patterns_t patterns; - if (!opt.simple_dffe) - patterns = find_muxtree_feedback_patterns(ff.sig_d[i], ff.sig_q[i], pattern_t()); - if (!patterns.empty() || !enables.empty()) { - if (ff.has_ce) - enables.insert(ctrl_t(ff.sig_ce, ff.pol_ce)); - simplify_patterns(patterns); - groups[std::make_pair(patterns, enables)].push_back(i); - } else - remaining_indices.push_back(i); - } - - for (auto &it : groups) { - FfData new_ff = ff.slice(it.second); - ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine); - - new_ff.has_ce = true; - new_ff.sig_ce = en.first; - new_ff.pol_ce = en.second; - new_ff.ce_over_srst = false; - Cell *new_cell = new_ff.emit(); - if (new_cell) - dff_cells.push_back(new_cell); - log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n", - log_id(cell), log_id(cell->type), log_id(module), log_signal(new_ff.sig_d), log_signal(new_ff.sig_q)); - } - - if (remaining_indices.empty()) { - module->remove(cell); - did_something = true; - continue; - } else if (GetSize(remaining_indices) != ff.width) { - ff = ff.slice(remaining_indices); - ff.cell = cell; - changed = true; - } + if (can_merge_ce && try_merge_ce(ff, cell, changed)) { + did_something = true; + continue; } } if (changed) { - // Rebuild the FF. ff.emit(); did_something = true; } } + return did_something; } - bool run_constbits() { + bool prove_const_with_sat(QuickConeSat &qcsat, ModWalker &modwalker, SigBit q, SigBit d, State val) + { + // Trivial non-const cases + if (!modwalker.has_drivers(d)) + return false; + if (val != State::S0 && val != State::S1) + return false; + + int init_sat_pi = qcsat.importSigBit(val); + int q_sat_pi = qcsat.importSigBit(q); + int d_sat_pi = qcsat.importSigBit(d); + qcsat.prepare(); + + // If no counterexample exists, FF is constant + return !qcsat.ez->solve( + qcsat.ez->IFF(q_sat_pi, init_sat_pi), + qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); + } + + State check_constbit(FfData &ff, int i) + { + State val = ff.val_init[i]; + if (ff.has_arst) val = combine_const(val, ff.val_arst[i]); + if (ff.has_srst) val = combine_const(val, ff.val_srst[i]); + if (ff.has_sr) { + if (ff.sig_clr[i] != (ff.pol_clr ? State::S0 : State::S1)) + val = combine_const(val, State::S0); + if (ff.sig_set[i] != (ff.pol_set ? State::S0 : State::S1)) + val = combine_const(val, State::S1); + } + + return val; + } + + bool run_constbits() + { + // Find FFs that are provably constant ModWalker modwalker(module->design, module); QuickConeSat qcsat(modwalker); - // Defer mutating cells by removing them/emiting new flip flops so that - // cell references in modwalker are not invalidated std::vector cells_to_remove; std::vector ffs_to_emit; - bool did_something = false; + for (auto cell : module->selected_cells()) { if (!cell->is_builtin_ff()) continue; - FfData ff(&initvals, cell); - // Now check if any bit can be replaced by a constant. + FfData ff(&initvals, cell); pool removed_sigbits; + for (int i = 0; i < ff.width; i++) { - State val = ff.val_init[i]; - if (ff.has_arst) - val = combine_const(val, ff.val_arst[i]); - if (ff.has_srst) - val = combine_const(val, ff.val_srst[i]); - if (ff.has_sr) { - if (ff.sig_clr[i] != (ff.pol_clr ? State::S0 : State::S1)) - val = combine_const(val, State::S0); - if (ff.sig_set[i] != (ff.pol_set ? State::S0 : State::S1)) - val = combine_const(val, State::S1); - } + State val = check_constbit(ff, i); if (val == State::Sm) continue; + + // Check Synchronous input D if (ff.has_clk || ff.has_gclk) { if (!ff.sig_d[i].wire) { + // D is already a constant val = combine_const(val, ff.sig_d[i].data); - if (val == State::Sm) + if (val == State::Sm) continue; + } else if (opt.sat) { + // Try SAT proof for non-constant D wires + if (!prove_const_with_sat(qcsat, modwalker, ff.sig_q[i], ff.sig_d[i], val)) continue; } else { - if (!opt.sat) - continue; - // For each register bit, try to prove that it cannot change from the initial value. If so, remove it - if (!modwalker.has_drivers(ff.sig_d.extract(i))) - continue; - if (val != State::S0 && val != State::S1) - continue; - - int init_sat_pi = qcsat.importSigBit(val); - int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]); - int d_sat_pi = qcsat.importSigBit(ff.sig_d[i]); - - qcsat.prepare(); - - // Try to find out whether the register bit can change under some circumstances - bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); - - // If the register bit cannot change, we can replace it with a constant - if (counter_example_found) - continue; + continue; } } + + // Check Async Load input AD if (ff.has_aload) { if (!ff.sig_ad[i].wire) { val = combine_const(val, ff.sig_ad[i].data); - if (val == State::Sm) + if (val == State::Sm) continue; + } else if (opt.sat) { + if (!prove_const_with_sat(qcsat, modwalker, ff.sig_q[i], ff.sig_ad[i], val)) continue; } else { - if (!opt.sat) - continue; - // For each register bit, try to prove that it cannot change from the initial value. If so, remove it - if (!modwalker.has_drivers(ff.sig_ad.extract(i))) - continue; - if (val != State::S0 && val != State::S1) - continue; - - int init_sat_pi = qcsat.importSigBit(val); - int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]); - int d_sat_pi = qcsat.importSigBit(ff.sig_ad[i]); - - qcsat.prepare(); - - // Try to find out whether the register bit can change under some circumstances - bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi))); - - // If the register bit cannot change, we can replace it with a constant - if (counter_example_found) - continue; + continue; } } - log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", val ? 1 : 0, - i, log_id(cell), log_id(cell->type), log_id(module)); + log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", + val ? 1 : 0, i, log_id(cell), log_id(cell->type), log_id(module)); + + // Replace the Q output with the constant value initvals.remove_init(ff.sig_q[i]); module->connect(ff.sig_q[i], val); removed_sigbits.insert(i); } + + // Reconstruct FF with constant bits removed if (!removed_sigbits.empty()) { std::vector keep_bits; for (int i = 0; i < ff.width; i++) if (!removed_sigbits.count(i)) keep_bits.push_back(i); + if (keep_bits.empty()) { - cells_to_remove.emplace_back(cell); - did_something = true; - continue; + cells_to_remove.push_back(cell); + } else { + ff = ff.slice(keep_bits); + ff.cell = cell; + ffs_to_emit.push_back(ff); } - ff = ff.slice(keep_bits); - ff.cell = cell; - ffs_to_emit.emplace_back(ff); did_something = true; } } + for (auto* cell : cells_to_remove) module->remove(cell); + for (auto& ff : ffs_to_emit) ff.emit(); + return did_something; } }; struct OptDffPass : public Pass { OptDffPass() : Pass("opt_dff", "perform DFF optimizations") { } + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -948,6 +961,7 @@ struct OptDffPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_DFF pass (perform DFF optimizations).\n"); + OptDffOptions opt; opt.nodffe = false; opt.nosdff = false; @@ -957,26 +971,11 @@ struct OptDffPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-nodffe") { - opt.nodffe = true; - continue; - } - if (args[argidx] == "-nosdff") { - opt.nosdff = true; - continue; - } - if (args[argidx] == "-simple-dffe") { - opt.simple_dffe = true; - continue; - } - if (args[argidx] == "-keepdc") { - opt.keepdc = true; - continue; - } - if (args[argidx] == "-sat") { - opt.sat = true; - continue; - } + if (args[argidx] == "-nodffe") { opt.nodffe = true; continue; } + if (args[argidx] == "-nosdff") { opt.nosdff = true; continue; } + if (args[argidx] == "-simple-dffe") { opt.simple_dffe = true; continue; } + if (args[argidx] == "-keepdc") { opt.keepdc = true; continue; } + if (args[argidx] == "-sat") { opt.sat = true; continue; } break; } extra_args(args, argidx, design); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index e8be360a8..2c040b09d 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -298,8 +298,6 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ log_debug("\n"); } - cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str()); - module->remove(cell); did_something = true; return true; @@ -518,7 +516,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (auto cell : cells.sorted) { -#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) +#define ACTION_DO(_p_, _s_) do { replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_)) bool detect_const_and = false; @@ -565,19 +563,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (detect_const_and && (found_zero || found_inv || (found_undef && consume_x))) { - cover("opt.opt_expr.const_and"); replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0); goto next_cell; } if (detect_const_or && (found_one || found_inv || (found_undef && consume_x))) { - cover("opt.opt_expr.const_or"); replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1); goto next_cell; } if (non_const_input != State::Sm && !found_undef) { - cover("opt.opt_expr.and_or_buffer"); replace_cell(assign_map, module, cell, "and_or_buffer", ID::Y, non_const_input); goto next_cell; } @@ -589,12 +584,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons SigBit sig_b = assign_map(cell->getPort(ID::B)); if (!keepdc && (sig_a == sig_b || sig_a == State::Sx || sig_a == State::Sz || sig_b == State::Sx || sig_b == State::Sz)) { if (cell->type.in(ID($xor), ID($_XOR_))) { - cover("opt.opt_expr.const_xor"); replace_cell(assign_map, module, cell, "const_xor", ID::Y, RTLIL::State::S0); goto next_cell; } if (cell->type.in(ID($xnor), ID($_XNOR_))) { - cover("opt.opt_expr.const_xnor"); // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ int width = GetSize(cell->getPort(ID::Y)); replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width)); @@ -607,7 +600,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons std::swap(sig_a, sig_b); if (sig_b == State::S0 || sig_b == State::S1) { if (cell->type.in(ID($xor), ID($_XOR_))) { - cover("opt.opt_expr.xor_buffer"); SigSpec sig_y; if (cell->type == ID($xor)) sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a); @@ -618,7 +610,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons goto next_cell; } if (cell->type.in(ID($xnor), ID($_XNOR_))) { - cover("opt.opt_expr.xnor_buffer"); SigSpec sig_y; if (cell->type == ID($xnor)) { sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit()); @@ -639,13 +630,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) { if (cell->type == ID($reduce_xnor)) { - cover("opt.opt_expr.reduce_xnor_not"); log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n", log_id(cell->type), log_id(cell->name), log_id(module)); cell->type = ID($not); did_something = true; } else { - cover("opt.opt_expr.unary_buffer"); replace_cell(assign_map, module, cell, "unary_buffer", ID::Y, cell->getPort(ID::A)); } goto next_cell; @@ -661,7 +650,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (a_fully_const != b_fully_const) { - cover("opt.opt_expr.bitwise_logic_one_const"); log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n", log_id(cell->type), log_id(cell->name), log_id(module)); RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); @@ -813,7 +801,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons new_sig_a.append(neutral_bit); if (GetSize(new_sig_a) < GetSize(sig_a)) { - cover_list("opt.opt_expr.fine.neutral_A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool", cell->type.str()); log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a)); cell->setPort(ID::A, new_sig_a); @@ -836,7 +823,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons new_sig_b.append(neutral_bit); if (GetSize(new_sig_b) < GetSize(sig_b)) { - cover_list("opt.opt_expr.fine.neutral_B", "$logic_and", "$logic_or", cell->type.str()); log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b)); cell->setPort(ID::B, new_sig_b); @@ -862,7 +848,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { - cover("opt.opt_expr.fine.$reduce_and"); log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(ID::A, sig_a = new_a); @@ -888,7 +873,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { - cover_list("opt.opt_expr.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str()); log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(ID::A, sig_a = new_a); @@ -914,7 +898,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) { - cover_list("opt.opt_expr.fine.B", "$logic_and", "$logic_or", cell->type.str()); log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort(ID::B, sig_b = new_b); @@ -949,7 +932,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module)); SigSpec new_a = sig_a.extract_end(i); SigSpec new_b = sig_b.extract_end(i); @@ -1006,7 +988,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover("opt.opt_expr.fine.$alu"); log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module)); SigSpec new_a = sig_a.extract_end(i); SigSpec new_b = sig_b.extract_end(i); @@ -1045,8 +1026,6 @@ skip_fine_alu: if (0) { found_the_x_bit: - cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", - "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$divfloor", "$modfloor", "$pow", cell->type.str()); if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt))) replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::State::Sx); else @@ -1068,7 +1047,6 @@ skip_fine_alu: } if (width < GetSize(sig_a)) { - cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str()); sig_a.remove(width, GetSize(sig_a)-width); cell->setPort(ID::A, sig_a); cell->setParam(ID::A_WIDTH, width); @@ -1079,13 +1057,11 @@ skip_fine_alu: if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(ID::Y)) == 1 && invert_map.count(assign_map(cell->getPort(ID::A))) != 0) { - cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); replace_cell(assign_map, module, cell, "double_invert", ID::Y, invert_map.at(assign_map(cell->getPort(ID::A)))); goto next_cell; } if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) { - cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module)); RTLIL::SigSpec tmp = cell->getPort(ID::A); cell->setPort(ID::A, cell->getPort(ID::B)); @@ -1168,7 +1144,6 @@ skip_fine_alu: if (input.match(" 1")) ACTION_DO(ID::Y, input.extract(1, 1)); if (input.match("01 ")) ACTION_DO(ID::Y, input.extract(0, 1)); if (input.match("10 ")) { - cover("opt.opt_expr.mux_to_inv"); cell->type = ID($_NOT_); cell->setPort(ID::A, input.extract(0, 1)); cell->unsetPort(ID::B); @@ -1195,7 +1170,6 @@ skip_fine_alu: if (input == State::S1) ACTION_DO(ID::Y, cell->getPort(ID::A)); if (input == State::S0 && !a.is_fully_undef()) { - cover("opt.opt_expr.action_" S__LINE__); log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); cell->setPort(ID::A, SigSpec(State::Sx, GetSize(a))); @@ -1220,7 +1194,6 @@ skip_fine_alu: log_assert(GetSize(a) == GetSize(b)); for (int i = 0; i < GetSize(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { - cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false); replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y); @@ -1233,7 +1206,6 @@ skip_fine_alu: } if (new_a.size() == 0) { - cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false); replace_cell(assign_map, module, cell, "empty", ID::Y, new_y); @@ -1241,7 +1213,6 @@ skip_fine_alu: } if (new_a.size() < a.size() || new_b.size() < b.size()) { - cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cell->setPort(ID::A, new_a); cell->setPort(ID::B, new_b); cell->parameters[ID::A_WIDTH] = new_a.size(); @@ -1256,7 +1227,6 @@ skip_fine_alu: RTLIL::SigSpec b = assign_map(cell->getPort(ID::B)); if (a.is_fully_const() && !b.is_fully_const()) { - cover_list("opt.opt_expr.eqneq.swapconst", "$eq", "$ne", cell->type.str()); cell->setPort(ID::A, b); cell->setPort(ID::B, a); std::swap(a, b); @@ -1271,7 +1241,6 @@ skip_fine_alu: RTLIL::SigSpec input = b; ACTION_DO(ID::Y, cell->getPort(ID::A)); } else { - cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->type = ID($not); cell->parameters.erase(ID::B_WIDTH); @@ -1286,7 +1255,6 @@ skip_fine_alu: if (cell->type.in(ID($eq), ID($ne)) && (assign_map(cell->getPort(ID::A)).is_fully_zero() || assign_map(cell->getPort(ID::B)).is_fully_zero())) { - cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell), log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool"); cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); @@ -1334,8 +1302,6 @@ skip_fine_alu: sig_y[i] = sig_a[GetSize(sig_a)-1]; } - cover_list("opt.opt_expr.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str()); - log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n", log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort(ID::B))), shift_bits, log_id(module), log_signal(sig_y)); @@ -1408,11 +1374,6 @@ skip_fine_alu: if (identity_wrt_a || identity_wrt_b) { - if (identity_wrt_a) - cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); - if (identity_wrt_b) - cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); - log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); @@ -1461,14 +1422,12 @@ skip_identity: if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) { - cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str()); replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID::S)); goto next_cell; } if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) { - cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort(ID::A, cell->getPort(ID::S)); cell->unsetPort(ID::B); @@ -1487,7 +1446,6 @@ skip_identity: } if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) { - cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort(ID::A, cell->getPort(ID::S)); cell->unsetPort(ID::S); @@ -1507,7 +1465,6 @@ skip_identity: } if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) { - cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort(ID::B, cell->getPort(ID::S)); cell->unsetPort(ID::S); @@ -1531,7 +1488,6 @@ skip_identity: int width = GetSize(cell->getPort(ID::A)); if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) || cell->getPort(ID::S).is_fully_undef()) { - cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A)); goto next_cell; } @@ -1550,17 +1506,14 @@ skip_identity: new_s = new_s.extract(0, new_s.size()-1); } if (new_s.size() == 0) { - cover_list("opt.opt_expr.mux_empty", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_empty", ID::Y, new_a); goto next_cell; } if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) { - cover_list("opt.opt_expr.mux_sel01", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s); goto next_cell; } if (cell->getPort(ID::S).size() != new_s.size()) { - cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str()); log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n", GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module)); cell->setPort(ID::A, new_a); @@ -1600,7 +1553,6 @@ skip_identity: RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \ cell->parameters[ID::A_SIGNED].as_bool(), false, \ cell->parameters[ID::Y_WIDTH].as_int())); \ - cover("opt.opt_expr.const.$" #_t); \ replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \ goto next_cell; \ } \ @@ -1615,7 +1567,6 @@ skip_identity: cell->parameters[ID::A_SIGNED].as_bool(), \ cell->parameters[ID::B_SIGNED].as_bool(), \ cell->parameters[ID::Y_WIDTH].as_int())); \ - cover("opt.opt_expr.const.$" #_t); \ replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \ goto next_cell; \ } \ @@ -1627,7 +1578,6 @@ skip_identity: assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const())); \ - cover("opt.opt_expr.const.$" #_t); \ replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \ goto next_cell; \ } \ @@ -1640,7 +1590,6 @@ skip_identity: assign_map.apply(a), assign_map.apply(b), assign_map.apply(s); \ if (a.is_fully_const() && b.is_fully_const() && s.is_fully_const()) { \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), s.as_const())); \ - cover("opt.opt_expr.const.$" #_t); \ replace_cell(assign_map, module, cell, stringf("%s, %s, %s", log_signal(a), log_signal(b), log_signal(s)), ID::Y, y); \ goto next_cell; \ } \ @@ -1716,7 +1665,11 @@ skip_identity: int bit_idx; const auto onehot = sig_a.is_onehot(&bit_idx); - if (onehot) { + // Power of two + // A is unsigned or positive + if (onehot && (!cell->parameters[ID::A_SIGNED].as_bool() || bit_idx < sig_a.size() - 1)) { + cell->parameters[ID::A_SIGNED] = 0; + // 2^B = 1<name.c_str(), module->name.c_str()); @@ -1728,7 +1681,6 @@ skip_identity: log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n", cell->name.c_str(), module->name.c_str()); cell->type = ID($mul); - cell->parameters[ID::A_SIGNED] = 0; cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int())); SigSpec y_wire = module->addWire(NEW_ID, y_size); @@ -1757,8 +1709,6 @@ skip_identity: { if (sig_a.is_fully_zero()) { - cover("opt.opt_expr.mul_shift.zero"); - log_debug("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); @@ -1772,11 +1722,6 @@ skip_identity: int exp; if (sig_a.is_onehot(&exp) && !(a_signed && exp == GetSize(sig_a) - 1)) { - if (swapped_ab) - cover("opt.opt_expr.mul_shift.swapped"); - else - cover("opt.opt_expr.mul_shift.unswapped"); - log_debug("Replacing multiply-by-%s cell `%s' in module `%s' with shift-by-%d.\n", log_signal(sig_a), cell->name.c_str(), module->name.c_str(), exp); @@ -1810,8 +1755,6 @@ skip_identity: break; if (a_zeros || b_zeros) { int y_zeros = a_zeros + b_zeros; - cover("opt.opt_expr.mul_low_zeros"); - log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n", a_zeros, b_zeros, cell->name.c_str(), module->name.c_str()); @@ -1853,8 +1796,6 @@ skip_identity: { if (sig_b.is_fully_zero()) { - cover("opt.opt_expr.divmod_zero"); - log_debug("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n", cell->name.c_str(), module->name.c_str()); @@ -1870,8 +1811,6 @@ skip_identity: { if (cell->type.in(ID($div), ID($divfloor))) { - cover("opt.opt_expr.div_shift"); - bool is_truncating = cell->type == ID($div); log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n", is_truncating ? "truncating" : "flooring", @@ -1900,8 +1839,6 @@ skip_identity: } else if (cell->type.in(ID($mod), ID($modfloor))) { - cover("opt.opt_expr.mod_mask"); - bool is_truncating = cell->type == ID($mod); log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n", is_truncating ? "truncating" : "flooring", @@ -2026,7 +1963,6 @@ skip_identity: sig_ci = p.second; } - cover("opt.opt_expr.alu_split"); module->remove(cell); did_something = true; diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 6cdcbc822..a6121b268 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -22,6 +22,7 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include "kernel/celltypes.h" +#include "kernel/threading.h" #include "libs/sha1/sha1.h" #include #include @@ -37,16 +38,73 @@ PRIVATE_NAMESPACE_BEGIN template inline Hasher hash_pair(const T &t, const U &u) { return hash_ops>::hash(t, u); } -struct OptMergeWorker +// Some cell and its hash value. +struct CellHash { - RTLIL::Design *design; - RTLIL::Module *module; - SigMap assign_map; - FfInitVals initvals; - bool mode_share_all; + // Index of a cell in the module + int cell_index; + Hasher::hash_t hash_value; +}; - CellTypes ct; - int total_count; +// The algorithm: +// 1) Compute and store the hashes of all relevant cells, in parallel. +// 2) Given N = the number of threads, partition the cells into N buckets by hash value: +// bucket k contains the cells whose hash value mod N = k. +// 3) For each bucket in parallel, build a hashtable of that bucket’s cells (using the +// precomputed hashes) and record the duplicates found. +// 4) On the main thread, process the list of duplicates to remove cells. +// For efficiency we fuse the second step into the first step by having the parallel +// threads write the cells into buckets directly. +// To avoid synchronization overhead, we divide each bucket into N shards. Each +// thread j adds a cell to bucket k by writing to shard j of bucket k — +// no synchronization required. In the next phase, thread k builds the hashtable for +// bucket k by iterating over all shards of the bucket. + +// The input to each thread in the "compute cell hashes" phase. +struct CellRange +{ + int begin; + int end; +}; + +// The output from each thread in the "compute cell hashes" phase. +struct CellHashes +{ + // Entry i contains the hashes where hash_value % bucketed_cell_hashes.size() == i + std::vector> bucketed_cell_hashes; +}; + +// A duplicate cell that has been found. +struct DuplicateCell +{ + // Remove this cell from the design + int remove_cell; + // ... and use this cell instead. + int keep_cell; +}; + +// The input to each thread in the "find duplicate cells" phase. +// Shards of buckets of cell hashes +struct Shards +{ + std::vector>> &bucketed_cell_hashes; +}; + +// The output from each thread in the "find duplicate cells" phase. +struct FoundDuplicates +{ + std::vector duplicates; +}; + +struct OptMergeThreadWorker +{ + const RTLIL::Module *module; + const SigMap &assign_map; + const FfInitVals &initvals; + const CellTypes &ct; + int workers; + bool mode_share_all; + bool mode_keepdc; static Hasher hash_pmux_in(const SigSpec& sig_s, const SigSpec& sig_b, Hasher h) { @@ -62,8 +120,8 @@ struct OptMergeWorker static void sort_pmux_conn(dict &conn) { - SigSpec sig_s = conn.at(ID::S); - SigSpec sig_b = conn.at(ID::B); + const SigSpec &sig_s = conn.at(ID::S); + const SigSpec &sig_b = conn.at(ID::B); int s_width = GetSize(sig_s); int width = GetSize(sig_b) / s_width; @@ -144,7 +202,6 @@ struct OptMergeWorker if (cell1->parameters != cell2->parameters) return false; - if (cell1->connections_.size() != cell2->connections_.size()) return false; for (const auto &it : cell1->connections_) @@ -199,7 +256,7 @@ struct OptMergeWorker return conn1 == conn2; } - bool has_dont_care_initval(const RTLIL::Cell *cell) + bool has_dont_care_initval(const RTLIL::Cell *cell) const { if (!cell->is_builtin_ff()) return false; @@ -207,31 +264,134 @@ struct OptMergeWorker return !initvals(cell->getPort(ID::Q)).is_fully_def(); } - OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all, bool mode_keepdc) : - design(design), module(module), mode_share_all(mode_share_all) + OptMergeThreadWorker(const RTLIL::Module *module, const FfInitVals &initvals, + const SigMap &assign_map, const CellTypes &ct, int workers, + bool mode_share_all, bool mode_keepdc) : + module(module), assign_map(assign_map), initvals(initvals), ct(ct), + workers(workers), mode_share_all(mode_share_all), mode_keepdc(mode_keepdc) { - total_count = 0; - ct.setup_internals(); - ct.setup_internals_mem(); - ct.setup_stdcells(); - ct.setup_stdcells_mem(); + } - if (mode_nomux) { - ct.cell_types.erase(ID($mux)); - ct.cell_types.erase(ID($pmux)); + CellHashes compute_cell_hashes(const CellRange &cell_range) const + { + std::vector> bucketed_cell_hashes(workers); + for (int cell_index = cell_range.begin; cell_index < cell_range.end; ++cell_index) { + const RTLIL::Cell *cell = module->cell_at(cell_index); + if (!module->selected(cell)) + continue; + if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) { + // Ignore those for performance: meminit can have an excessively large port, + // mem can have an excessively large parameter holding the init data + continue; + } + if (cell->type == ID($scopeinfo)) + continue; + if (mode_keepdc && has_dont_care_initval(cell)) + continue; + if (!cell->known()) + continue; + if (!mode_share_all && !ct.cell_known(cell->type)) + continue; + + Hasher::hash_t h = hash_cell_function(cell, Hasher()).yield(); + int bucket_index = h % workers; + bucketed_cell_hashes[bucket_index].push_back({cell_index, h}); } + return {std::move(bucketed_cell_hashes)}; + } - ct.cell_types.erase(ID($tribuf)); - ct.cell_types.erase(ID($_TBUF_)); - ct.cell_types.erase(ID($anyseq)); - ct.cell_types.erase(ID($anyconst)); - ct.cell_types.erase(ID($allseq)); - ct.cell_types.erase(ID($allconst)); + FoundDuplicates find_duplicate_cells(int index, const Shards &in) const + { + // We keep a set of known cells. They're hashed with our hash_cell_function + // and compared with our compare_cell_parameters_and_connections. + struct CellHashOp { + std::size_t operator()(const CellHash &c) const { + return (std::size_t)c.hash_value; + } + }; + struct CellEqualOp { + const OptMergeThreadWorker& worker; + CellEqualOp(const OptMergeThreadWorker& w) : worker(w) {} + bool operator()(const CellHash &lhs, const CellHash &rhs) const { + return worker.compare_cell_parameters_and_connections( + worker.module->cell_at(lhs.cell_index), + worker.module->cell_at(rhs.cell_index)); + } + }; + std::unordered_set< + CellHash, + CellHashOp, + CellEqualOp> known_cells(0, CellHashOp(), CellEqualOp(*this)); + + std::vector duplicates; + for (const std::vector> &buckets : in.bucketed_cell_hashes) { + // Clear out our buckets as we go. This keeps the work of deallocation + // off the main thread. + std::vector bucket = std::move(buckets[index]); + for (CellHash c : bucket) { + auto [cell_in_map, inserted] = known_cells.insert(c); + if (inserted) + continue; + CellHash map_c = *cell_in_map; + if (module->cell_at(c.cell_index)->has_keep_attr()) { + if (module->cell_at(map_c.cell_index)->has_keep_attr()) + continue; + known_cells.erase(map_c); + known_cells.insert(c); + std::swap(c, map_c); + } + duplicates.push_back({c.cell_index, map_c.cell_index}); + } + } + return {duplicates}; + } +}; + +template +void initialize_queues(std::vector> &queues, int size) { + queues.reserve(size); + for (int i = 0; i < size; ++i) + queues.emplace_back(1); +} + +struct OptMergeWorker +{ + int total_count; + + OptMergeWorker(RTLIL::Module *module, const CellTypes &ct, bool mode_share_all, bool mode_keepdc) : + total_count(0) + { + SigMap assign_map(module); + FfInitVals initvals; + initvals.set(&assign_map, module); log("Finding identical cells in module `%s'.\n", module->name); - assign_map.set(module); - initvals.set(&assign_map, module); + // Use no more than one worker per thousand cells, rounded down, so + // we only start multithreading with at least 2000 cells. + int num_worker_threads = ThreadPool::pool_size(0, module->cells_size()/1000); + int workers = std::max(1, num_worker_threads); + + // The main thread doesn't do any work, so if there is only one worker thread, + // just run everything on the main thread instead. + // This avoids creating and waiting on a thread, which is pretty high overhead + // for very small modules. + if (num_worker_threads == 1) + num_worker_threads = 0; + OptMergeThreadWorker thread_worker(module, initvals, assign_map, ct, workers, mode_share_all, mode_keepdc); + + std::vector> cell_ranges_queues(num_worker_threads); + std::vector> cell_hashes_queues(num_worker_threads); + std::vector> shards_queues(num_worker_threads); + std::vector> duplicates_queues(num_worker_threads); + + ThreadPool thread_pool(num_worker_threads, [&](int i) { + while (std::optional c = cell_ranges_queues[i].pop_front()) { + cell_hashes_queues[i].push_back(thread_worker.compute_cell_hashes(*c)); + std::optional shards = shards_queues[i].pop_front(); + duplicates_queues[i].push_back(thread_worker.find_duplicate_cells(i, *shards)); + } + }); bool did_something = true; // A cell may have to go through a lot of collisions if the hash @@ -239,87 +399,99 @@ struct OptMergeWorker // beyond the user's control. while (did_something) { - std::vector cells; - cells.reserve(module->cells().size()); - for (auto cell : module->cells()) { - if (!design->selected(module, cell)) - continue; - if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) { - // Ignore those for performance: meminit can have an excessively large port, - // mem can have an excessively large parameter holding the init data - continue; - } - if (cell->type == ID($scopeinfo)) - continue; - if (mode_keepdc && has_dont_care_initval(cell)) - continue; - if (!cell->known()) - continue; - if (!mode_share_all && !ct.cell_known(cell->type)) - continue; - cells.push_back(cell); - } + int cells_size = module->cells_size(); + log("Computing hashes of %d cells of `%s'.\n", cells_size, module->name); + std::vector>> sharded_bucketed_cell_hashes(workers); - did_something = false; - - // We keep a set of known cells. They're hashed with our hash_cell_function - // and compared with our compare_cell_parameters_and_connections. - // Both need to capture OptMergeWorker to access initvals - struct CellPtrHash { - const OptMergeWorker& worker; - CellPtrHash(const OptMergeWorker& w) : worker(w) {} - std::size_t operator()(const Cell* c) const { - return (std::size_t)worker.hash_cell_function(c, Hasher()).yield(); - } - }; - struct CellPtrEqual { - const OptMergeWorker& worker; - CellPtrEqual(const OptMergeWorker& w) : worker(w) {} - bool operator()(const Cell* lhs, const Cell* rhs) const { - return worker.compare_cell_parameters_and_connections(lhs, rhs); - } - }; - std::unordered_set< - RTLIL::Cell*, - CellPtrHash, - CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this)); - - for (auto cell : cells) + int cell_index = 0; + int cells_size_mod_workers = cells_size % workers; { - auto [cell_in_map, inserted] = known_cells.insert(cell); - if (!inserted) { - // We've failed to insert since we already have an equivalent cell - Cell* other_cell = *cell_in_map; - if (cell->has_keep_attr()) { - if (other_cell->has_keep_attr()) - continue; - known_cells.erase(other_cell); - known_cells.insert(cell); - std::swap(other_cell, cell); - } - - did_something = true; - log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name); - for (auto &it : cell->connections()) { - if (cell->output(it.first)) { - RTLIL::SigSpec other_sig = other_cell->getPort(it.first); - log_debug(" Redirecting output %s: %s = %s\n", it.first, - log_signal(it.second), log_signal(other_sig)); - Const init = initvals(other_sig); - initvals.remove_init(it.second); - initvals.remove_init(other_sig); - module->connect(RTLIL::SigSig(it.second, other_sig)); - assign_map.add(it.second, other_sig); - initvals.set_init(other_sig, init); - } - } - log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); - module->remove(cell); - total_count++; + Multithreading multithreading; + for (int i = 0; i < workers; ++i) { + int num_cells = cells_size/workers + ((i < cells_size_mod_workers) ? 1 : 0); + CellRange c = { cell_index, cell_index + num_cells }; + cell_index += num_cells; + if (num_worker_threads > 0) + cell_ranges_queues[i].push_back(c); + else + sharded_bucketed_cell_hashes[i] = std::move(thread_worker.compute_cell_hashes(c).bucketed_cell_hashes); } + log_assert(cell_index == cells_size); + if (num_worker_threads > 0) + for (int i = 0; i < workers; ++i) + sharded_bucketed_cell_hashes[i] = std::move(cell_hashes_queues[i].pop_front()->bucketed_cell_hashes); } + + log("Finding duplicate cells in `%s'.\n", module->name); + std::vector merged_duplicates; + { + Multithreading multithreading; + for (int i = 0; i < workers; ++i) { + Shards thread_shards = { sharded_bucketed_cell_hashes }; + if (num_worker_threads > 0) + shards_queues[i].push_back(thread_shards); + else { + std::vector d = std::move(thread_worker.find_duplicate_cells(i, thread_shards).duplicates); + merged_duplicates.insert(merged_duplicates.end(), d.begin(), d.end()); + } + } + if (num_worker_threads > 0) + for (int i = 0; i < workers; ++i) { + std::vector d = std::move(duplicates_queues[i].pop_front()->duplicates); + merged_duplicates.insert(merged_duplicates.end(), d.begin(), d.end()); + } + } + std::sort(merged_duplicates.begin(), merged_duplicates.end(), [](const DuplicateCell &lhs, const DuplicateCell &rhs) { + // Sort them by the order in which duplicates would have been detected in a single-threaded + // run. The cell at which the duplicate would have been detected is the latter of the two + // cells involved. + return std::max(lhs.remove_cell, lhs.keep_cell) < std::max(rhs.remove_cell, rhs.keep_cell); + }); + + // Convert to cell pointers because removing cells will invalidate the indices. + std::vector> cell_ptrs; + for (DuplicateCell dup : merged_duplicates) + cell_ptrs.push_back({module->cell_at(dup.remove_cell), module->cell_at(dup.keep_cell)}); + + for (auto [remove_cell, keep_cell] : cell_ptrs) + { + log_debug(" Cell `%s' is identical to cell `%s'.\n", remove_cell->name, keep_cell->name); + for (auto &it : remove_cell->connections()) { + if (remove_cell->output(it.first)) { + RTLIL::SigSpec keep_sig = keep_cell->getPort(it.first); + log_debug(" Redirecting output %s: %s = %s\n", it.first, + log_signal(it.second), log_signal(keep_sig)); + Const init = initvals(keep_sig); + initvals.remove_init(it.second); + initvals.remove_init(keep_sig); + module->connect(RTLIL::SigSig(it.second, keep_sig)); + auto keep_sig_it = keep_sig.begin(); + for (SigBit remove_sig_bit : it.second) { + assign_map.add(remove_sig_bit, *keep_sig_it); + ++keep_sig_it; + } + initvals.set_init(keep_sig, init); + } + } + log_debug(" Removing %s cell `%s' from module `%s'.\n", remove_cell->type, remove_cell->name, module->name); + module->remove(remove_cell); + total_count++; + } + did_something = !merged_duplicates.empty(); } + for (ConcurrentQueue &q : cell_ranges_queues) + q.close(); + + for (ConcurrentQueue &q : shards_queues) + q.close(); + + for (ConcurrentQueue &q : cell_ranges_queues) + q.close(); + + for (ConcurrentQueue &q : shards_queues) + q.close(); + log_suppressed(); } }; @@ -372,9 +544,25 @@ struct OptMergePass : public Pass { } extra_args(args, argidx, design); + CellTypes ct; + ct.setup_internals(); + ct.setup_internals_mem(); + ct.setup_stdcells(); + ct.setup_stdcells_mem(); + if (mode_nomux) { + ct.cell_types.erase(ID($mux)); + ct.cell_types.erase(ID($pmux)); + } + ct.cell_types.erase(ID($tribuf)); + ct.cell_types.erase(ID($_TBUF_)); + ct.cell_types.erase(ID($anyseq)); + ct.cell_types.erase(ID($anyconst)); + ct.cell_types.erase(ID($allseq)); + ct.cell_types.erase(ID($allconst)); + int total_count = 0; for (auto module : design->selected_modules()) { - OptMergeWorker worker(design, module, mode_nomux, mode_share_all, mode_keepdc); + OptMergeWorker worker(module, ct, mode_share_all, mode_keepdc); total_count += worker.total_count; } diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 2f7d26dcf..0020af09f 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -64,7 +64,7 @@ struct OptMuxtreeWorker RTLIL::Module *module; SigMap assign_map; int removed_count; - int glob_evals_left = 10000000; + int glob_evals_left = 10'000'000; struct bitinfo_t { // Is bit directly used by non-mux cells or ports? diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 19c2be4ca..8cccb96c4 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -97,6 +97,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did all_empty = false; if (all_empty) { + did_something = true; for (auto cs : sw->cases) delete cs; sw->cases.clear(); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 90b85d709..8a0a45dcf 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -31,6 +31,22 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static SatSolver *find_satsolver(const std::string &name) +{ + for (auto solver = yosys_satsolver_list; solver != nullptr; solver = solver->next) + if (solver->name == name) + return solver; + return nullptr; +} + +static std::string list_satsolvers() +{ + std::string result; + for (auto solver = yosys_satsolver_list; solver != nullptr; solver = solver->next) + result += result.empty() ? solver->name : ", " + solver->name; + return result; +} + struct SatHelper { RTLIL::Design *design; @@ -60,8 +76,8 @@ struct SatHelper int max_timestep, timeout; bool gotTimeout; - SatHelper(RTLIL::Design *design, RTLIL::Module *module, bool enable_undef, bool set_def_formal) : - design(design), module(module), sigmap(module), ct(design), satgen(ez.get(), &sigmap) + SatHelper(RTLIL::Design *design, RTLIL::Module *module, SatSolver *solver, bool enable_undef, bool set_def_formal) : + design(design), module(module), sigmap(module), ct(design), ez(solver), satgen(ez.get(), &sigmap) { this->enable_undef = enable_undef; satgen.model_undef = enable_undef; @@ -441,7 +457,7 @@ struct SatHelper log_assert(gotTimeout == false); ez->setSolverTimeout(timeout); bool success = ez->solve(modelExpressions, modelValues, assumptions); - if (ez->getSolverTimoutStatus()) + if (ez->getSolverTimeoutStatus()) gotTimeout = true; return success; } @@ -451,7 +467,7 @@ struct SatHelper log_assert(gotTimeout == false); ez->setSolverTimeout(timeout); bool success = ez->solve(modelExpressions, modelValues, a, b, c, d, e, f); - if (ez->getSolverTimoutStatus()) + if (ez->getSolverTimeoutStatus()) gotTimeout = true; return success; } @@ -1066,6 +1082,10 @@ struct SatPass : public Pass { log(" -timeout \n"); log(" Maximum number of seconds a single SAT instance may take.\n"); log("\n"); + log(" -select-solver \n"); + log(" Select SAT solver implementation for this invocation.\n"); + log(" If not given, uses scratchpad key 'sat.solver' if set, otherwise default.\n"); + log("\n"); log(" -verify\n"); log(" Return an error and stop the synthesis script if the proof fails.\n"); log("\n"); @@ -1097,8 +1117,14 @@ struct SatPass : public Pass { log_header(design, "Executing SAT pass (solving SAT problems in the circuit).\n"); + std::string solver_name = design->scratchpad_get_string("sat.solver", ""); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-select-solver" && argidx+1 < args.size()) { + solver_name = args[++argidx]; + continue; + } if (args[argidx] == "-all") { loopcount = -1; continue; @@ -1336,6 +1362,14 @@ struct SatPass : public Pass { } extra_args(args, argidx, design); + SatSolver *solver = yosys_satsolver; + if (!solver_name.empty()) { + solver = find_satsolver(solver_name); + if (solver == nullptr) + log_cmd_error("Unknown SAT solver '%s'. Available solvers: %s\n", + solver_name, list_satsolvers()); + } + RTLIL::Module *module = NULL; for (auto mod : design->selected_modules()) { if (module) @@ -1398,13 +1432,15 @@ struct SatPass : public Pass { shows.push_back(wire->name.str()); } + log("Using SAT solver `%s`.\n", solver->name.c_str()); + if (tempinduct) { if (loopcount > 0 || max_undef) log_cmd_error("The options -max, -all, and -max_undef are not supported for temporal induction proofs!\n"); - SatHelper basecase(design, module, enable_undef, set_def_formal); - SatHelper inductstep(design, module, enable_undef, set_def_formal); + SatHelper basecase(design, module, solver, enable_undef, set_def_formal); + SatHelper inductstep(design, module, solver, enable_undef, set_def_formal); basecase.sets = sets; basecase.set_assumes = set_assumes; @@ -1593,7 +1629,7 @@ struct SatPass : public Pass { if (maxsteps > 0) log_cmd_error("The options -maxsteps is only supported for temporal induction proofs!\n"); - SatHelper sathelper(design, module, enable_undef, set_def_formal); + SatHelper sathelper(design, module, solver, enable_undef, set_def_formal); sathelper.sets = sets; sathelper.set_assumes = set_assumes; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 7ea193ac6..d78da892f 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -550,31 +550,27 @@ struct SimInstance if (shared->debug) log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type)); - // Simple (A -> Y) and (A,B -> Y) cells - if (has_a && !has_c && !has_d && !has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b))); - return; - } + bool err = false; + RTLIL::Const eval_state; + if (has_a && !has_c && !has_d && !has_s && has_y) + // Simple (A -> Y) and (A,B -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), &err); + else if (has_a && has_b && has_c && !has_d && !has_s && has_y) + // (A,B,C -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c), &err); + else if (has_a && !has_b && !has_c && !has_d && has_s && has_y) + // (A,S -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_s), &err); + else if (has_a && has_b && !has_c && !has_d && has_s && has_y) + // (A,B,S -> Y) cells + eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s), &err); + else + err = true; - // (A,B,C -> Y) cells - if (has_a && has_b && has_c && !has_d && !has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c))); - return; - } - - // (A,S -> Y) cells - if (has_a && !has_b && !has_c && !has_d && has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_s))); - return; - } - - // (A,B,S -> Y) cells - if (has_a && has_b && !has_c && !has_d && has_s && has_y) { - set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s))); - return; - } - - log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); + if (err) + log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); + else + set_state(sig_y, eval_state); return; } diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 91b3b563a..083778d3c 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -39,6 +39,7 @@ OBJS += passes/techmap/muxcover.o OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o OBJS += passes/techmap/lut2mux.o +OBJS += passes/techmap/lut2bmux.o OBJS += passes/techmap/nlutmap.o OBJS += passes/techmap/shregmap.o OBJS += passes/techmap/deminout.o diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 85e177fd4..a072bf022 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -143,6 +143,14 @@ struct AbcConfig bool markgroups = false; pool enabled_gates; bool cmos_cost = false; + + bool is_yosys_abc() const { +#ifdef ABCEXTERNAL + return false; +#else + return exe_file == yosys_abc_executable; +#endif + } }; struct AbcSigVal { @@ -155,7 +163,12 @@ struct AbcSigVal { } }; -#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) +// REUSE_YOSYS_ABC_PROCESSES only works when ABC is built with ENABLE_READLINE. +#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) && defined(YOSYS_ENABLE_READLINE) +#define REUSE_YOSYS_ABC_PROCESSES +#endif + +#ifdef REUSE_YOSYS_ABC_PROCESSES struct AbcProcess { pid_t pid; @@ -188,10 +201,10 @@ struct AbcProcess int status; int ret = waitpid(pid, &status, 0); if (ret != pid) { - log_error("waitpid(%d) failed", pid); + log_error("waitpid(%d) failed\n", pid); } if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { - log_error("ABC failed with status %X", status); + log_error("ABC failed with status %X\n", status); } if (from_child_pipe >= 0) close(from_child_pipe); @@ -203,12 +216,12 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { // fork()s. int to_child_pipe[2]; if (pipe2(to_child_pipe, O_CLOEXEC) != 0) { - logs.log_error("pipe failed"); + logs.log_error("pipe failed\n"); return std::nullopt; } int from_child_pipe[2]; if (pipe2(from_child_pipe, O_CLOEXEC) != 0) { - logs.log_error("pipe failed"); + logs.log_error("pipe failed\n"); return std::nullopt; } @@ -221,39 +234,39 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { posix_spawn_file_actions_t file_actions; if (posix_spawn_file_actions_init(&file_actions) != 0) { - logs.log_error("posix_spawn_file_actions_init failed"); + logs.log_error("posix_spawn_file_actions_init failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[1]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[0]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_adddup2(&file_actions, to_child_pipe[0], STDIN_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); + logs.log_error("posix_spawn_file_actions_adddup2 failed\n"); return std::nullopt; } if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDOUT_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); + logs.log_error("posix_spawn_file_actions_adddup2 failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[0]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[1]) != 0) { - logs.log_error("posix_spawn_file_actions_addclose failed"); + logs.log_error("posix_spawn_file_actions_addclose failed\n"); return std::nullopt; } char arg1[] = "-s"; char* argv[] = { strdup(abc_exe), arg1, nullptr }; - if (0 != posix_spawn(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { - logs.log_error("posix_spawn %s failed", abc_exe); + if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { + logs.log_error("posix_spawnp %s failed (errno=%s)\n", abc_exe, strerror(errno)); return std::nullopt; } free(argv[0]); @@ -272,7 +285,7 @@ using AbcSigMap = SigValMap; struct RunAbcState { const AbcConfig &config; - std::string tempdir_name; + std::string per_run_tempdir_name; std::vector signal_list; bool did_run = false; bool err = false; @@ -823,16 +836,23 @@ std::string fold_abc_cmd(std::string str) return new_str; } -std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir) +std::string replace_tempdir(std::string text, std::string_view global_tempdir_name, std::string_view per_run_tempdir_name, bool show_tempdir) { if (show_tempdir) return text; while (1) { - size_t pos = text.find(tempdir_name); + size_t pos = text.find(global_tempdir_name); if (pos == std::string::npos) break; - text = text.substr(0, pos) + "" + text.substr(pos + GetSize(tempdir_name)); + text = text.substr(0, pos) + "" + text.substr(pos + GetSize(global_tempdir_name)); + } + + while (1) { + size_t pos = text.find(per_run_tempdir_name); + if (pos == std::string::npos) + break; + text = text.substr(0, pos) + "" + text.substr(pos + GetSize(per_run_tempdir_name)); } std::string selfdir_name = proc_self_dirname(); @@ -854,11 +874,12 @@ struct abc_output_filter bool got_cr; int escape_seq_state; std::string linebuf; - std::string tempdir_name; + std::string global_tempdir_name; + std::string per_run_tempdir_name; bool show_tempdir; - abc_output_filter(RunAbcState& state, std::string tempdir_name, bool show_tempdir) - : state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir) + abc_output_filter(RunAbcState& state, std::string global_tempdir_name, std::string per_run_tempdir_name, bool show_tempdir) + : state(state), global_tempdir_name(global_tempdir_name), per_run_tempdir_name(per_run_tempdir_name), show_tempdir(show_tempdir) { got_cr = false; escape_seq_state = 0; @@ -885,7 +906,7 @@ struct abc_output_filter return; } if (ch == '\n') { - state.logs.log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); + state.logs.log("ABC: %s\n", replace_tempdir(linebuf, global_tempdir_name, per_run_tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -986,15 +1007,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module const AbcConfig &config = run_abc.config; if (config.cleanup) - run_abc.tempdir_name = get_base_tmpdir() + "/"; + run_abc.per_run_tempdir_name = get_base_tmpdir() + "/"; else - run_abc.tempdir_name = "_tmp_"; - run_abc.tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; - run_abc.tempdir_name = make_temp_dir(run_abc.tempdir_name); + run_abc.per_run_tempdir_name = "_tmp_"; + run_abc.per_run_tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; + run_abc.per_run_tempdir_name = make_temp_dir(run_abc.per_run_tempdir_name); log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", - module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); + module->name.c_str(), replace_tempdir(run_abc.per_run_tempdir_name, config.global_tempdir_name, run_abc.per_run_tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name); + std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.per_run_tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -1060,18 +1081,19 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3); if (config.abc_dress) - abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name); - abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name); + abc_script += stringf("; dress \"%s/input.blif\"", run_abc.per_run_tempdir_name); + abc_script += stringf("; write_blif %s/output.blif", run_abc.per_run_tempdir_name); abc_script = add_echos_to_abc_cmd(abc_script); -#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) - abc_script += "; echo \"YOSYS_ABC_DONE\"\n"; +#if defined(REUSE_YOSYS_ABC_PROCESSES) + if (config.is_yosys_abc()) + abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n"; #endif for (size_t i = 0; i+1 < abc_script.size(); i++) if (abc_script[i] == ';' && abc_script[i+1] == ' ') abc_script[i+1] = '\n'; - std::string buffer = stringf("%s/abc.script", run_abc.tempdir_name); + std::string buffer = stringf("%s/abc.script", run_abc.per_run_tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); @@ -1127,42 +1149,86 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module handle_loops(assign_map, module); } +#if defined(REUSE_YOSYS_ABC_PROCESSES) +static bool is_abc_prompt(const std::string &line, std::string &rest) { + size_t pos = 0; + while (true) { + // The prompt may not start at the start of the line, because + // ABC can output progress and maybe other data that isn't + // newline-terminated. + size_t start = line.find("abc ", pos); + if (start == std::string::npos) + return false; + pos = start + 4; + + size_t digits = 0; + while (pos + digits < line.size() && line[pos + digits] >= '0' && line[pos + digits] <= '9') + ++digits; + if (digits < 2) + return false; + if (line.substr(pos + digits, 2) == "> ") { + rest = line.substr(pos + digits + 2); + return true; + } + } +} + bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { std::string line; char buf[1024]; + bool seen_source_cmd = false; + bool seen_yosys_abc_done = false; while (true) { int ret = read(fd, buf, sizeof(buf) - 1); if (ret < 0) { - logs.log_error("Failed to read from ABC, errno=%d", errno); + logs.log_error("Failed to read from ABC, errno=%d\n", errno); return false; } if (ret == 0) { - logs.log_error("ABC exited prematurely"); + logs.log_error("ABC exited prematurely\n"); return false; } char *start = buf; char *end = buf + ret; while (start < end) { char *p = static_cast(memchr(start, '\n', end - start)); - if (p == nullptr) { - break; + char *upto = p == nullptr ? end : p + 1; + line.append(start, upto - start); + start = upto; + + std::string rest; + bool is_prompt = is_abc_prompt(line, rest); + if (is_prompt && seen_source_cmd) { + // This is the first prompt after we sourced the script. + // We are done here. + // We won't have seen a newline yet since ABC is waiting at the prompt. + if (!seen_yosys_abc_done) + logs.log_error("ABC script did not complete successfully\n"); + return seen_yosys_abc_done; } - line.append(start, p + 1 - start); - if (line.substr(0, 14) == "YOSYS_ABC_DONE") { - // Ignore any leftover output, there should only be a prompt perhaps - return true; + if (line.empty() || line[line.size() - 1] != '\n') { + // No newline yet, wait for more text + continue; } filt.next_line(line); + if (is_prompt && rest.substr(0, 7) == "source ") + seen_source_cmd = true; + if (line.substr(0, 14) == "YOSYS_ABC_DONE") + seen_yosys_abc_done = true; line.clear(); - start = p + 1; } line.append(start, end - start); } } +#endif +#if defined(REUSE_YOSYS_ABC_PROCESSES) void RunAbcState::run(ConcurrentStack &process_pool) +#else +void RunAbcState::run(ConcurrentStack &) +#endif { - std::string buffer = stringf("%s/input.blif", tempdir_name); + std::string buffer = stringf("%s/input.blif", per_run_tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) { logs.log("Opening %s for writing failed: %s\n", buffer, strerror(errno)); @@ -1285,15 +1351,19 @@ void RunAbcState::run(ConcurrentStack &process_pool) logs.log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", count_gates, GetSize(signal_list), count_input, count_output); - if (count_output > 0) - { - std::string tmp_script_name = stringf("%s/abc.script", tempdir_name); - logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, tempdir_name, config.show_tempdir)); + if (count_output == 0) { + log("Don't call ABC as there is nothing to map.\n"); + return; + } + int ret; + std::string tmp_script_name = stringf("%s/abc.script", per_run_tempdir_name); + do { + logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, config.global_tempdir_name, per_run_tempdir_name, config.show_tempdir)); errno = 0; - abc_output_filter filt(*this, tempdir_name, config.show_tempdir); + abc_output_filter filt(*this, config.global_tempdir_name, per_run_tempdir_name, config.show_tempdir); #ifdef YOSYS_LINK_ABC - string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name); + string temp_stdouterr_name = stringf("%s/stdouterr.txt", per_run_tempdir_name); FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); if (temp_stdouterr_w == NULL) log_error("ABC: cannot open a temporary file for output redirection"); @@ -1318,7 +1388,7 @@ void RunAbcState::run(ConcurrentStack &process_pool) abc_argv[2] = strdup("-f"); abc_argv[3] = strdup(tmp_script_name.c_str()); abc_argv[4] = 0; - int ret = abc::Abc_RealMain(4, abc_argv); + ret = abc::Abc_RealMain(4, abc_argv); free(abc_argv[0]); free(abc_argv[1]); free(abc_argv[2]); @@ -1333,39 +1403,42 @@ void RunAbcState::run(ConcurrentStack &process_pool) for (std::string line; std::getline(temp_stdouterr_r, line); ) filt.next_line(line + "\n"); temp_stdouterr_r.close(); -#elif defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) - AbcProcess process; - if (std::optional process_opt = process_pool.try_pop_back()) { - process = std::move(process_opt.value()); - } else if (std::optional process_opt = spawn_abc(config.exe_file.c_str(), logs)) { - process = std::move(process_opt.value()); - } else { - return; - } - std::string cmd = stringf( - "empty\n" - "source %s\n", tmp_script_name); - int ret = write(process.to_child_pipe, cmd.c_str(), cmd.size()); - if (ret != static_cast(cmd.size())) { - logs.log_error("write failed"); - return; - } - ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1; - if (ret == 0) { - process_pool.push_back(std::move(process)); - } + break; #else - std::string cmd = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str()); - int ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); -#endif - if (ret != 0) { - logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno); - return; +#if defined(REUSE_YOSYS_ABC_PROCESSES) + if (config.is_yosys_abc()) { + AbcProcess process; + if (std::optional process_opt = process_pool.try_pop_back()) { + process = std::move(process_opt.value()); + } else if (std::optional process_opt = spawn_abc(config.exe_file.c_str(), logs)) { + process = std::move(process_opt.value()); + } else { + return; + } + std::string cmd = stringf( + "empty\n" + "source %s\n", tmp_script_name); + ret = write(process.to_child_pipe, cmd.c_str(), cmd.size()); + if (ret != static_cast(cmd.size())) { + logs.log_error("write failed"); + return; + } + ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1; + if (ret == 0) { + process_pool.push_back(std::move(process)); + } + break; } - did_run = true; +#endif + std::string cmd = stringf("\"%s\" -s -f %s 2>&1", config.exe_file, tmp_script_name); + ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); +#endif + } while (false); + if (ret != 0) { + logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno); return; } - log("Don't call ABC as there is nothing to map.\n"); + did_run = true; } void emit_global_input_files(const AbcConfig &config) @@ -1437,7 +1510,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL return; } - std::string buffer = stringf("%s/%s", run_abc.tempdir_name, "output.blif"); + std::string buffer = stringf("%s/%s", run_abc.per_run_tempdir_name, "output.blif"); std::ifstream ifs; ifs.open(buffer); if (ifs.fail()) @@ -1724,7 +1797,7 @@ void AbcModuleState::finish() if (run_abc.config.cleanup) { log("Removing temp directory.\n"); - remove_directory(run_abc.tempdir_name); + remove_directory(run_abc.per_run_tempdir_name); } log_pop(); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8b61a9299..16df82bb6 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -219,9 +219,7 @@ struct Abc9Pass : public ScriptPass for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if ((arg == "-exe" || arg == "-script" || arg == "-D" || - /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" || - /*arg == "-box" ||*/ arg == "-W" || arg == "-genlib" || - arg == "-constr" || arg == "-dont_use" || arg == "-liberty") && + arg == "-lut" || arg == "-luts" || arg == "-W") && argidx+1 < args.size()) { if (arg == "-lut" || arg == "-luts") lut_mode = true; diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 4449065f8..2baf53a02 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -248,7 +248,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe } abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name); - if (design->scratchpad_get_bool("abc9.verify")) { + if (design->scratchpad_get_bool("abc9.verify", true)) { if (dff_mode) abc9_script += "; &verify -s"; else diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 21ffa075b..4e279c577 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -38,7 +38,8 @@ std::vector order_modules(Design *design, std::vector modules sort.edge(submodule, m); } } - log_assert(sort.sort()); + bool is_sorted = sort.sort(); + log_assert(is_sorted); return sort.sorted; } diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index a4552c71b..123687255 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -415,7 +415,7 @@ struct BufnormPass : public Pass { return mapped_bits.at(bit); }; - auto make_buffer_f = [&](const IdString &type, const SigSpec &src, const SigSpec &dst) + auto make_buffer_f = [&](IdString type, const SigSpec &src, const SigSpec &dst) { auto it = old_buffers.find(pair(type, dst)); diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc index 020597c4b..e72c250bb 100644 --- a/passes/techmap/dffunmap.cc +++ b/passes/techmap/dffunmap.cc @@ -78,7 +78,6 @@ struct DffunmapPass : public Pass { continue; FfData ff(&initvals, cell); - IdString name = cell->name; if (!ff.has_clk) continue; diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 1984f82f5..46ab7e520 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -40,10 +40,10 @@ int bindec(unsigned char v) r += (~((v & 2) - 1)) & 10; r += (~((v & 4) - 1)) & 100; r += (~((v & 8) - 1)) & 1000; - r += (~((v & 16) - 1)) & 10000; - r += (~((v & 32) - 1)) & 100000; - r += (~((v & 64) - 1)) & 1000000; - r += (~((v & 128) - 1)) & 10000000; + r += (~((v & 16) - 1)) & 10'000; + r += (~((v & 32) - 1)) & 100'000; + r += (~((v & 64) - 1)) & 1'000'000; + r += (~((v & 128) - 1)) & 10'000'000; return r; } diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index a9ae75c01..274a51d54 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -827,6 +827,17 @@ std::string vlog_identifier(std::string str) return str; } +void event2vl_wire(std::string &edge, LibertyExpression& parsed, const std::string& wire) +{ + edge.clear(); + if (parsed.kind == LibertyExpression::Kind::NOT) { + edge = "negedge " + wire; + // parsed = parsed.children[0]; + } else { + edge = "posedge " + wire; + } +} + void event2vl(const LibertyAst *ast, std::string &edge, std::string &expr) { edge.clear(); @@ -843,33 +854,160 @@ void event2vl(const LibertyAst *ast, std::string &edge, std::string &expr) } } -void clear_preset_var(std::string var, std::string type) +enum ClearPresetVar { + Error, + L, + H, + T, + X, +}; + +ClearPresetVar clear_preset_var(std::string type) { if (type.find('L') != std::string::npos) { + return ClearPresetVar::L; + } + if (type.find('H') != std::string::npos) { + return ClearPresetVar::H; + } + if (type.find('T') != std::string::npos) { + return ClearPresetVar::T; + } + if (type.find('X') != std::string::npos) { + return ClearPresetVar::X; + } + return ClearPresetVar::X; +} + +void print_clear_preset_var(std::string var, ClearPresetVar type) +{ + if (type == ClearPresetVar::L) { printf(" %s <= 0;\n", var.c_str()); return; } - if (type.find('H') != std::string::npos) { + if (type == ClearPresetVar::H) { printf(" %s <= 1;\n", var.c_str()); return; } - if (type.find('T') != std::string::npos) { + if (type == ClearPresetVar::T) { printf(" %s <= ~%s;\n", var.c_str(), var.c_str()); return; } - if (type.find('X') != std::string::npos) { + if (type == ClearPresetVar::X) { printf(" %s <= 'bx;\n", var.c_str()); return; } } +struct FfEdge { + std::string edge; + std::string expr; +}; +struct FfEdges { + FfEdge clock; + FfEdge clear; + FfEdge preset; + std::string edge; + void wired(FfEdge& edge, const LibertyAst* ast, const std::string& wire, const char* tag) { + auto* found = ast->find(tag); + if (!found) + return; + auto lexer = LibertyExpression::Lexer(found->value); + auto expr = LibertyExpression::parse(lexer); + event2vl_wire(edge.edge, expr, wire); + edge.expr = expr.vlog_str(); + } + FfEdges(LibertyAst* child, const std::string& clear_wire, const std::string& preset_wire) { + wired(clear, child, clear_wire, "clear"); + wired(preset, child, preset_wire, "preset"); + event2vl(child->find("clocked_on"), clock.edge, clock.expr); + edge = ""; + if (!clock.edge.empty()) + edge += (edge.empty() ? "" : ", ") + clock.edge; + if (!clear.edge.empty()) + edge += (edge.empty() ? "" : ", ") + clear.edge; + if (!preset.edge.empty()) + edge += (edge.empty() ? "" : ", ") + preset.edge; + } +}; + +struct FfVar { + std::string var; + std::string edge; + FfEdge clear; + FfEdge preset; + // Value for both asserted + const char* clear_preset_var_name; + std::string next_state; + const char* else_prefix = ""; +public: + void proc_header() { + printf(" always @(%s) begin\n", edge.c_str()); + } + void proc_footer() { + if (*else_prefix) + printf(" end\n"); + + printf(" end\n"); + } + void proc_cond(FfEdge& edge, const char* value) { + printf(" %sif (%s) begin\n", else_prefix, edge.expr.c_str()); + printf(" %s <= %s;\n", var.c_str(), value); + printf(" end\n"); + else_prefix = "else "; + } + void proc_cond_clear() { proc_cond(clear, "0"); } + void proc_cond_preset() { proc_cond(preset, "1"); } + void proc_next_state() { + if (*else_prefix) + printf(" %sbegin\n", else_prefix); + printf(" %s <= %s;\n", var.c_str(), next_state.c_str()); + } + void proc(LibertyAst* child) { + else_prefix = ""; + proc_header(); + if (!clear.expr.empty() && !preset.expr.empty()) { + ClearPresetVar clear_preset = clear_preset_var(find_non_null(child, clear_preset_var_name)->value); + if (clear_preset == ClearPresetVar::L) { + proc_cond_clear(); + proc_cond_preset(); + proc_next_state(); + proc_footer(); + return; + } else if (clear_preset == ClearPresetVar::H) { + // Notice that preset and clear are swapped + proc_cond_preset(); + proc_cond_clear(); + proc_next_state(); + proc_footer(); + return; + } else { + // Boo, we have to emit non-synthesizable verilog + printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear.expr.c_str(), preset.expr.c_str()); + print_clear_preset_var(var, clear_preset); + printf(" end\n"); + else_prefix = "else "; + } + } + if (!clear.expr.empty()) { + proc_cond_clear(); + } + if (!preset.expr.empty()) { + proc_cond_preset(); + } + proc_next_state(); + proc_footer(); + } +}; + void gen_verilogsim_cell(const LibertyAst *ast) { if (ast->find("statetable") != NULL) return; CHECK_NV(ast->args.size(), == 1); - printf("module %s (", vlog_identifier(ast->args[0]).c_str()); + auto module_name = vlog_identifier(ast->args[0]); + printf("module %s (", module_name.c_str()); bool first = true; for (auto child : ast->children) { if (child->id != "pin") @@ -883,13 +1021,29 @@ void gen_verilogsim_cell(const LibertyAst *ast) for (auto child : ast->children) { if (child->id != "ff" && child->id != "latch") continue; - printf(" reg "); first = true; + std::string iq = ""; for (auto arg : child->args) { + if (first) + printf(" reg "); printf("%s%s", first ? "" : ", ", vlog_identifier(arg).c_str()); + if (first) + iq = vlog_identifier(arg); first = false; } - printf(";\n"); + if (!first) + printf(";\n"); + first = true; + for (auto gchild : child->children) { + if (gchild->id == "clear" || gchild->id == "preset") { + if (first) + printf(" wire "); + printf("%s%s_%s", first ? "" : ", ", iq.c_str(), gchild->id.c_str()); + first = false; + } + } + if (!first) + printf(";\n"); } for (auto child : ast->children) { @@ -909,63 +1063,45 @@ void gen_verilogsim_cell(const LibertyAst *ast) if (child->id != "ff" || child->args.size() != 2) continue; - std::string iq_var = vlog_identifier(child->args[0]); - std::string iqn_var = vlog_identifier(child->args[1]); + auto iq_name = vlog_identifier(child->args[0]); + auto clear_wire = iq_name + "_clear"; + auto preset_wire = iq_name + "_preset"; + FfEdges edges(child, clear_wire, preset_wire); - std::string clock_edge, clock_expr; - event2vl(child->find("clocked_on"), clock_edge, clock_expr); - - std::string clear_edge, clear_expr; - event2vl(child->find("clear"), clear_edge, clear_expr); - - std::string preset_edge, preset_expr; - event2vl(child->find("preset"), preset_edge, preset_expr); - - std::string edge = ""; - if (!clock_edge.empty()) - edge += (edge.empty() ? "" : ", ") + clock_edge; - if (!clear_edge.empty()) - edge += (edge.empty() ? "" : ", ") + clear_edge; - if (!preset_edge.empty()) - edge += (edge.empty() ? "" : ", ") + preset_edge; - - if (edge.empty()) + if (edges.edge.empty()) continue; - printf(" always @(%s) begin\n", edge.c_str()); + std::string next_state = func2vl(find_non_null(child, "next_state")->value); + std::string not_next_state = std::string("~(") + next_state + ")"; - const char *else_prefix = ""; - if (!clear_expr.empty() && !preset_expr.empty()) { - printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear_expr.c_str(), preset_expr.c_str()); - clear_preset_var(iq_var, find_non_null(child, "clear_preset_var1")->value); - clear_preset_var(iqn_var, find_non_null(child, "clear_preset_var2")->value); - printf(" end\n"); - else_prefix = "else "; - } - if (!clear_expr.empty()) { - printf(" %sif (%s) begin\n", else_prefix, clear_expr.c_str()); - printf(" %s <= 0;\n", iq_var.c_str()); - printf(" %s <= 1;\n", iqn_var.c_str()); - printf(" end\n"); - else_prefix = "else "; - } - if (!preset_expr.empty()) { - printf(" %sif (%s) begin\n", else_prefix, preset_expr.c_str()); - printf(" %s <= 1;\n", iq_var.c_str()); - printf(" %s <= 0;\n", iqn_var.c_str()); - printf(" end\n"); - else_prefix = "else "; - } - if (*else_prefix) - printf(" %sbegin\n", else_prefix); - std::string expr = find_non_null(child, "next_state")->value; - printf(" // %s\n", expr.c_str()); - printf(" %s <= %s;\n", iq_var.c_str(), func2vl(expr).c_str()); - printf(" %s <= ~(%s);\n", iqn_var.c_str(), func2vl(expr).c_str()); - if (*else_prefix) - printf(" end\n"); - printf(" end\n"); + if (edges.clear.expr.length()) + std::swap(clear_wire, edges.clear.expr); + if (edges.preset.expr.length()) + std::swap(preset_wire, edges.preset.expr); + auto iq = FfVar { + .var = vlog_identifier(child->args[0]), + .edge = edges.edge, + .clear = edges.clear, + .preset = edges.preset, + .clear_preset_var_name = "clear_preset_var1", + .next_state = next_state, + }; + auto iqn = FfVar { + .var = vlog_identifier(child->args[1]), + .edge = edges.edge, + // Swapped clear and preset + .clear = edges.preset, + .preset = edges.clear, + .clear_preset_var_name = "clear_preset_var2", + .next_state = not_next_state, + }; + iq.proc(child); + iqn.proc(child); + if (edges.clear.expr.length()) + printf(" assign %s = %s;\n", edges.clear.expr.c_str(), clear_wire.c_str()); + if (edges.preset.expr.length()) + printf(" assign %s = %s;\n", edges.preset.expr.c_str(), preset_wire.c_str()); } for (auto child : ast->children) @@ -990,8 +1126,8 @@ void gen_verilogsim_cell(const LibertyAst *ast) const char *else_prefix = ""; if (!clear_expr.empty() && !preset_expr.empty()) { printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear_expr.c_str(), preset_expr.c_str()); - clear_preset_var(iq_var, find_non_null(child, "clear_preset_var1")->value); - clear_preset_var(iqn_var, find_non_null(child, "clear_preset_var2")->value); + print_clear_preset_var(iq_var, clear_preset_var(find_non_null(child, "clear_preset_var1")->value)); + print_clear_preset_var(iqn_var, clear_preset_var(find_non_null(child, "clear_preset_var2")->value)); printf(" end\n"); else_prefix = "else "; } diff --git a/passes/techmap/lut2bmux.cc b/passes/techmap/lut2bmux.cc new file mode 100644 index 000000000..42042c942 --- /dev/null +++ b/passes/techmap/lut2bmux.cc @@ -0,0 +1,58 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct Lut2BmuxPass : public Pass { + Lut2BmuxPass() : Pass("lut2bmux", "convert $lut to $bmux") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" lut2bmux [options] [selection]\n"); + log("\n"); + log("This pass converts $lut cells to $bmux cells.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing LUT2BMUX pass (convert $lut to $bmux).\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + for (auto cell : module->selected_cells()) { + if (cell->type == ID($lut)) { + cell->type = ID($bmux); + cell->setPort(ID::S, cell->getPort(ID::A)); + cell->setPort(ID::A, cell->getParam(ID::LUT)); + cell->unsetParam(ID::LUT); + cell->fixup_parameters(); + log("Converted %s.%s to BMUX cell.\n", log_id(module), log_id(cell)); + } + } + } +} Lut2BmuxPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index ef76e0deb..3d45734ec 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -int lut2mux(Cell *cell) +int lut2mux(Cell *cell, bool word_mode) { SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_y = cell->getPort(ID::Y); @@ -32,7 +32,10 @@ int lut2mux(Cell *cell) if (GetSize(sig_a) == 1) { - cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + if (!word_mode) + cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + else + cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } else { @@ -44,10 +47,13 @@ int lut2mux(Cell *cell) Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1)); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2)); + count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); + count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode); - cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + if (!word_mode) + cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + else + cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); } cell->module->remove(cell); @@ -55,26 +61,33 @@ int lut2mux(Cell *cell) } struct Lut2muxPass : public Pass { - Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { } + Lut2muxPass() : Pass("lut2mux", "convert $lut to $mux/$_MUX_") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" lut2mux [options] [selection]\n"); log("\n"); - log("This pass converts $lut cells to $_MUX_ gates.\n"); + log("This pass converts $lut cells to $mux/$_MUX_ gates.\n"); + log("\n"); + log(" -word\n"); + log(" Convert $lut cells with a single input to word-level $mux gates.\n"); + log(" The default is to convert them to bit-level $_MUX_ gates.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { - log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n"); + log_header(design, "Executing LUT2MUX pass (convert $lut to $mux/$_MUX_).\n"); + log("ARGS:"); for (auto &a: args) log(" [%s]", a.c_str()); log("\n"); size_t argidx; + bool word_mode = false; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-v") { - // continue; - // } + if (args[argidx] == "-word") { + word_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -83,7 +96,7 @@ struct Lut2muxPass : public Pass { for (auto cell : module->selected_cells()) { if (cell->type == ID($lut)) { IdString cell_name = cell->name; - int count = lut2mux(cell); + int count = lut2mux(cell, word_mode); log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count); } } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 938ed5355..0c7d1930e 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -27,7 +27,7 @@ USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN -static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) { +static void transfer_attr (Cell* to, const Cell* from, IdString attr) { if (from->has_attribute(attr)) to->attributes[attr] = from->attributes.at(attr); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index b49a40704..cf7ce56e2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -333,9 +333,6 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - - if (c->type.begins_with("\\$")) - c->type = c->type.substr(1); if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) { c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype)); @@ -436,13 +433,9 @@ struct TechmapWorker if (handled_cells.count(cell) > 0) continue; - std::string cell_type = cell->type.str(); - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - if (celltypeMap.count(cell_type) == 0) { - if (assert_mode && cell_type.back() != '_') - log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type)); + if (celltypeMap.count(cell->type) == 0) { + if (assert_mode && !cell->type.ends_with("_")) + log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); continue; } @@ -454,7 +447,7 @@ struct TechmapWorker if (GetSize(sig) == 0) continue; - for (auto &tpl_name : celltypeMap.at(cell_type)) { + for (auto &tpl_name : celltypeMap.at(cell->type)) { RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Wire *port = tpl->wire(conn.first); if (port && port->port_input) @@ -481,12 +474,7 @@ struct TechmapWorker log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; - std::string cell_type = cell->type.str(); - - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - for (auto &tpl_name : celltypeMap.at(cell_type)) + for (auto &tpl_name : celltypeMap.at(cell->type)) { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); @@ -508,8 +496,6 @@ struct TechmapWorker if (!extmapper_name.empty()) { - cell->type = cell_type; - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type)); @@ -935,11 +921,6 @@ struct TechmapWorker RTLIL::Module *m = design->addModule(m_name); tpl->cloneInto(m); - for (auto cell : m->cells()) { - if (cell->type.begins_with("\\$")) - cell->type = cell->type.substr(1); - } - module_queue.insert(m); } @@ -1168,7 +1149,7 @@ struct TechmapPass : public Pass { std::vector map_files; std::vector dont_map; - std::string verilog_frontend = "verilog -nooverwrite -noblackbox"; + std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells"; int max_iter = -1; size_t argidx; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 73af155bd..4d28e659b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -1143,7 +1143,29 @@ struct TestCellPass : public Pass { else uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv); if (!write_prefix.empty()) { - Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i)); + string writer = "write_rtlil"; + string suffix = "il"; + if (techmap_cmd.compare("aigmap") == 0) { + // try to convert to aiger + Pass::call(design, techmap_cmd); + bool is_unconverted = false; + for (auto *mod : design->selected_modules()) + for (auto *cell : mod->selected_cells()) + if (!cell->type.in(ID::$_NOT_, ID::$_AND_)) { + is_unconverted = true; + break; + } + if (is_unconverted) { + // skip unconverted cells + log_warning("Skipping %s\n", cell_type); + delete design; + break; + } else { + writer = "write_aiger -ascii"; + suffix = "aag"; + } + } + Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, cell_type.c_str()+1, i, suffix)); } else if (edges) { Pass::call(design, "dump gold"); run_edges_test(design, verbose); diff --git a/pyosys/generator.py b/pyosys/generator.py index 25f87d570..f1d429724 100644 --- a/pyosys/generator.py +++ b/pyosys/generator.py @@ -164,8 +164,7 @@ pyosys_headers = [ { "global_id_storage_", "global_id_index_", - "global_negative_id_storage_", - "global_negative_id_prefix_storage_", + "global_autoidx_id_storage_", "global_refcount_storage_", "global_free_idx_list_", "builtin_ff_cell_types", @@ -702,6 +701,16 @@ class PyosysWrapperGenerator(object): self.process_class_members(metadata, metadata, cls, basename) + if basename == "Design": + print( + '\t\t\t.def("run_pass", [](Design &s, std::vector cmd) { Pass::call(&s, cmd); })', + file=self.f, + ) + print( + '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(&s, cmd); })', + file=self.f, + ) + if expr := metadata.string_expr: print( f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})', diff --git a/pyosys/wrappers_tpl.cc b/pyosys/wrappers_tpl.cc index aa257e1b6..2e358029a 100644 --- a/pyosys/wrappers_tpl.cc +++ b/pyosys/wrappers_tpl.cc @@ -112,7 +112,7 @@ namespace pyosys { void notify_connect( RTLIL::Cell *cell, - const RTLIL::IdString &port, + RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig ) override { @@ -228,7 +228,7 @@ namespace pyosys { "notify_connect", py::overload_cast< RTLIL::Cell *, - const RTLIL::IdString &, + RTLIL::IdString, const RTLIL::SigSpec &, const RTLIL::SigSpec & >(&RTLIL::Monitor::notify_connect) diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc index a98619abd..6798f2a5d 100644 --- a/techlibs/common/prep.cc +++ b/techlibs/common/prep.cc @@ -211,6 +211,7 @@ struct PrepPass : public ScriptPass run("memory_collect"); } run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast"); + run("sort"); } if (check_label("check")) diff --git a/techlibs/fix_mod.py b/techlibs/fix_mod.py new file mode 100644 index 000000000..d6406108d --- /dev/null +++ b/techlibs/fix_mod.py @@ -0,0 +1,47 @@ +import sys +import subprocess +import re +import os + +def main(): + script = sys.argv.pop(0) + try: + verilog, yosys = sys.argv + except ValueError: + print(f"Expected to be called as 'python3 {script} '.") + exit(1) + + proc = subprocess.run([yosys, '-p', f'read_verilog -lib {verilog}; write_verilog -blackboxes -'], stdout=subprocess.PIPE) + modules = {} + in_mod = False + mod = "" + decl = "" + for line in proc.stdout.decode('utf-8').splitlines(keepends=True): + m = re.match(r'(module (\S+)\(.+)', line, re.S) + if m: + decl, mod = m.groups() + in_mod = True + elif in_mod: + decl += line + + if in_mod and decl.rstrip()[-1] == ';': + in_mod = False + modules[mod] = decl + + src = f'{verilog}.tmp' + os.rename(verilog, src) + dest = verilog + + with open(dest, 'w') as f_out: + with open(src, 'r') as f_in: + for line in f_in: + m = re.match(r'module (\S+) \(\.\.\.\)', line) + if m: + line = modules[m.group(1)] + print(line, end='', file=f_out) + + if src.endswith('.tmp'): + os.remove(src) + +if __name__ == "__main__": + main() diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index df1b79317..0744b1389 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -12,3 +12,4 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v)) diff --git a/techlibs/gowin/brams.txt b/techlibs/gowin/brams.txt index ee76dd73a..6898c9bd9 100644 --- a/techlibs/gowin/brams.txt +++ b/techlibs/gowin/brams.txt @@ -2,6 +2,7 @@ ram block $__GOWIN_SP_ { abits 14; widths 1 2 4 9 18 36 per_port; cost 128; + byte 9; init no_undef; port srsw "A" { clock posedge; @@ -24,6 +25,7 @@ ram block $__GOWIN_SP_ { rdwr old; } } + wrbe_separate; } } @@ -31,6 +33,7 @@ ram block $__GOWIN_DP_ { abits 14; widths 1 2 4 9 18 per_port; cost 128; + byte 9; init no_undef; port srsw "A" "B" { clock posedge; @@ -53,6 +56,7 @@ ram block $__GOWIN_DP_ { rdwr old; } } + wrbe_separate; } } @@ -60,6 +64,7 @@ ram block $__GOWIN_SDP_ { abits 14; widths 1 2 4 9 18 36 per_port; cost 128; + byte 9; init no_undef; port sr "R" { clock posedge; @@ -75,5 +80,6 @@ ram block $__GOWIN_SDP_ { port sw "W" { clock posedge; clken; + wrbe_separate; } } diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index 8e6cc6140..6187eadac 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -14,7 +14,7 @@ `define x8_width(width) (width / 9 * 8 + width % 9) `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]} `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]} -`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111}) +`define addrbe(width, addr, w_be) (width < 18 ? addr : width == 18 ? {addr[13:4], 2'b00, w_be[1:0]} : {addr[13:5], 1'b0, w_be[3:0]}) `define INIT(func) \ @@ -90,6 +90,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 36; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -97,13 +98,14 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; -wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); +wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); generate @@ -173,9 +175,11 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 18; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; parameter PORT_B_WIDTH = 18; parameter PORT_B_OPTION_WRITE_MODE = 0; +parameter PORT_B_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -183,6 +187,7 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; @@ -192,6 +197,7 @@ input PORT_B_WR_EN; input PORT_B_RD_SRST; input PORT_B_RD_ARST; input [13:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; @@ -199,8 +205,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); -wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR); +wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); +wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); generate @@ -306,6 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; parameter PORT_W_WIDTH = 18; +parameter PORT_W_WR_BE_WIDTH = 4; input PORT_R_CLK; input PORT_R_CLK_EN; @@ -318,12 +325,13 @@ input PORT_W_CLK; input PORT_W_CLK_EN; input PORT_W_WR_EN; input [13:0] PORT_W_ADDR; +input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST; -wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR); +wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE); wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN; generate diff --git a/techlibs/gowin/brams_map_gw5a.v b/techlibs/gowin/brams_map_gw5a.v index 246146ee5..8bc77bf4f 100644 --- a/techlibs/gowin/brams_map_gw5a.v +++ b/techlibs/gowin/brams_map_gw5a.v @@ -14,7 +14,7 @@ `define x8_width(width) (width / 9 * 8 + width % 9) `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]} `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]} -`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111}) +`define addrbe(width, addr, w_be) (width < 18 ? addr : width == 18 ? {addr[13:4], 2'b00, w_be[1:0]} : {addr[13:5], 1'b0, w_be[3:0]}) `define INIT(func) \ @@ -90,6 +90,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 36; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -97,13 +98,14 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; -wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); +wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); generate @@ -173,9 +175,11 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 18; parameter PORT_A_OPTION_WRITE_MODE = 0; +parameter PORT_A_WR_BE_WIDTH = 4; parameter PORT_B_WIDTH = 18; parameter PORT_B_OPTION_WRITE_MODE = 0; +parameter PORT_B_WR_BE_WIDTH = 4; input PORT_A_CLK; input PORT_A_CLK_EN; @@ -183,6 +187,7 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; @@ -192,6 +197,7 @@ input PORT_B_WR_EN; input PORT_B_RD_SRST; input PORT_B_RD_ARST; input [13:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; @@ -199,8 +205,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); -wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR); +wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); +wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); generate @@ -306,6 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; parameter PORT_W_WIDTH = 18; +parameter PORT_W_WR_BE_WIDTH = 4; input PORT_R_CLK; input PORT_R_CLK_EN; @@ -318,12 +325,13 @@ input PORT_W_CLK; input PORT_W_CLK_EN; input PORT_W_WR_EN; input [13:0] PORT_W_ADDR; +input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST; -wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR); +wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE); wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN; generate diff --git a/techlibs/gowin/cells_xtra_gw1n.v b/techlibs/gowin/cells_xtra_gw1n.v index 436fda0fa..0ab375ec8 100644 --- a/techlibs/gowin/cells_xtra_gw1n.v +++ b/techlibs/gowin/cells_xtra_gw1n.v @@ -1,41 +1,41 @@ // Created by cells_xtra.py -module LUT5 (...); +module LUT5(I0, I1, I2, I3, I4, F); parameter INIT = 32'h00000000; input I0, I1, I2, I3, I4; output F; endmodule -module LUT6 (...); +module LUT6(I0, I1, I2, I3, I4, I5, F); parameter INIT = 64'h0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5; output F; endmodule -module LUT7 (...); +module LUT7(I0, I1, I2, I3, I4, I5, I6, F); parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6; output F; endmodule -module LUT8 (...); +module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F); parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6, I7; output F; endmodule -module INV (...); +module INV(I, O); input I; output O; endmodule -module IODELAY (...); +module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); parameter C_STATIC_DLY = 0; input DI; input SDTAP; @@ -46,7 +46,7 @@ output DO; endmodule -module IEM (...); +module IEM(D, CLK, RESET, MCLK, LAG, LEAD); parameter WINSIZE = "SMALL"; parameter GSREN = "false"; parameter LSREN = "true"; @@ -55,14 +55,14 @@ output LAG, LEAD; endmodule -module ROM16 (...); +module ROM16(AD, DO); parameter INIT_0 = 16'h0000; input [3:0] AD; output DO; endmodule -module ROM (...); +module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; @@ -141,7 +141,7 @@ output [31:0] DO; endmodule -module ROMX9 (...); +module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; @@ -220,7 +220,7 @@ output [35:0] DO; endmodule -module pROM (...); +module pROM(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter RESET_MODE = "SYNC"; @@ -296,7 +296,7 @@ output [31:0] DO; endmodule -module pROMX9 (...); +module pROMX9(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter RESET_MODE = "SYNC"; @@ -372,7 +372,7 @@ output [35:0] DO; endmodule -module SDPB (...); +module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; parameter BIT_WIDTH_1 = 32; @@ -453,7 +453,7 @@ output [31:0] DO; endmodule -module SDPX9B (...); +module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 36; parameter BIT_WIDTH_1 = 36; @@ -534,7 +534,7 @@ output [35:0] DO; endmodule -module DPB (...); +module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -619,7 +619,7 @@ output [15:0] DOA, DOB; endmodule -module DPX9B (...); +module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -704,7 +704,7 @@ output [17:0] DOA, DOB; endmodule -module PADD18 (...); +module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [17:0] A; input [17:0] B; input ASEL; @@ -720,7 +720,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module PADD9 (...); +module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [8:0] A; input [8:0] B; input ASEL; @@ -736,7 +736,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module MULT9X9 (...); +module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [8:0] A,SIA; input [8:0] B,SIB; input ASIGN,BSIGN; @@ -756,7 +756,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT18X18 (...); +module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [17:0] A,SIA; input [17:0] B,SIB; input ASIGN,BSIGN; @@ -776,7 +776,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT36X36 (...); +module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); input [35:0] A; input [35:0] B; input ASIGN,BSIGN; @@ -794,7 +794,7 @@ parameter BSIGN_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU36X18 (...); +module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); input [17:0] A; input [35:0] B; input [53:0] C; @@ -819,7 +819,7 @@ parameter MULTALU36X18_MODE = 0; parameter C_ADD_SUB = 1'b0; endmodule -module MULTADDALU18X18 (...); +module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); input [17:0] A0; input [17:0] B0; input [17:0] A1; @@ -857,7 +857,7 @@ parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU18X18 (...); +module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO); input [17:0] A, B; input CLK,CE,RESET; input ASIGN, BSIGN; @@ -883,7 +883,7 @@ parameter C_ADD_SUB = 1'b0; parameter MULTALU18X18_MODE = 0; endmodule -module ALU54D (...); +module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); input [53:0] A, B; input ASIGN,BSIGN; input ACCLOAD; @@ -903,19 +903,19 @@ parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; endmodule -module BUFG (...); +module BUFG(O, I); output O; input I; endmodule -module BUFS (...); +module BUFS(O, I); output O; input I; endmodule -module PLL (...); +module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3); input CLKIN; input CLKFB; input RESET; @@ -956,39 +956,39 @@ parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW1N-4"; endmodule -module TLVDS_IBUF (...); +module TLVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module TLVDS_TBUF (...); +module TLVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module TLVDS_IOBUF (...); +module TLVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module ELVDS_IBUF (...); +module ELVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module ELVDS_TBUF (...); +module ELVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module ELVDS_IOBUF (...); +module ELVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module MIPI_IBUF (...); +module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN); output OH, OL, OB; inout IO, IOB; input I, IB; @@ -996,40 +996,40 @@ input OEN, OENB; input HSREN; endmodule -module MIPI_IBUF_HS (...); +module MIPI_IBUF_HS(OH, I, IB); output OH; input I, IB; endmodule -module MIPI_IBUF_LP (...); +module MIPI_IBUF_LP(OL, OB, I, IB); output OL; output OB; input I; input IB; endmodule -module MIPI_OBUF (...); +module MIPI_OBUF(O, OB, I, IB, MODESEL); output O, OB; input I, IB, MODESEL; endmodule -module MIPI_OBUF_A (...); +module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL); output O, OB; input I, IB, IL, MODESEL; endmodule -module ELVDS_IBUF_MIPI (...); +module ELVDS_IBUF_MIPI(OH, OL, I, IB); output OH, OL; input I, IB; endmodule -module I3C_IOBUF (...); +module I3C_IOBUF(O, IO, I, MODESEL); output O; inout IO; input I, MODESEL; endmodule -module CLKDIV (...); +module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT); input HCLKIN; input RESETN; input CALIB; @@ -1038,12 +1038,12 @@ parameter DIV_MODE = "2"; parameter GSREN = "false"; endmodule -module DHCEN (...); +module DHCEN(CLKIN, CE, CLKOUT); input CLKIN,CE; output CLKOUT; endmodule -module DLLDLY (...); +module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG); input CLKIN; input [7:0] DLLSTEP; input DIR,LOADN,MOVE; @@ -1054,7 +1054,7 @@ parameter DLY_SIGN = 1'b0; parameter DLY_ADJ = 0; endmodule -module FLASH96K (...); +module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT); input [5:0] RA,CA,PA; input [3:0] MODE; input [1:0] SEQ; @@ -1065,7 +1065,7 @@ input [31:0] DIN; output [31:0] DOUT; endmodule -module FLASH256K (...); +module FLASH256K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); input[6:0]XADR; input[5:0]YADR; input XE,YE,SE; @@ -1087,7 +1087,7 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule -module FLASH608K (...); +module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); input[8:0]XADR; input[5:0]YADR; input XE,YE,SE; @@ -1109,31 +1109,31 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule -module DCS (...); +module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; parameter DCS_MODE = "RISING"; endmodule -module DQCE (...); +module DQCE(CLKIN, CE, CLKOUT); input CLKIN; input CE; output CLKOUT; endmodule -module CLKDIV2 (...); +module CLKDIV2(HCLKIN, RESETN, CLKOUT); parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule -module DHCENC (...); +module DHCENC(CLKIN, CE, CLKOUT, CLKOUTN); input CLKIN, CE; output CLKOUT, CLKOUTN; endmodule -module FLASH64K (...); +module FLASH64K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, SLEEP, DIN, DOUT); input[4:0]XADR; input[5:0]YADR; input XE,YE,SE; @@ -1156,7 +1156,7 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule -module FLASH64KZ (...); +module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); input[4:0]XADR; input[5:0]YADR; input XE,YE,SE; diff --git a/techlibs/gowin/cells_xtra_gw2a.v b/techlibs/gowin/cells_xtra_gw2a.v index 4df48ab64..643723db6 100644 --- a/techlibs/gowin/cells_xtra_gw2a.v +++ b/techlibs/gowin/cells_xtra_gw2a.v @@ -1,41 +1,41 @@ // Created by cells_xtra.py -module LUT5 (...); +module LUT5(I0, I1, I2, I3, I4, F); parameter INIT = 32'h00000000; input I0, I1, I2, I3, I4; output F; endmodule -module LUT6 (...); +module LUT6(I0, I1, I2, I3, I4, I5, F); parameter INIT = 64'h0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5; output F; endmodule -module LUT7 (...); +module LUT7(I0, I1, I2, I3, I4, I5, I6, F); parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6; output F; endmodule -module LUT8 (...); +module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F); parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6, I7; output F; endmodule -module INV (...); +module INV(I, O); input I; output O; endmodule -module IDDR_MEM (...); +module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; input D, ICLK, PCLK; @@ -46,7 +46,7 @@ output Q0,Q1; endmodule -module ODDR_MEM (...); +module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; parameter TCLK_SOURCE = "DQSW"; @@ -57,7 +57,7 @@ output Q0, Q1; endmodule -module IDES4_MEM (...); +module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3); parameter GSREN = "false"; parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; @@ -68,7 +68,7 @@ output Q0,Q1,Q2,Q3; endmodule -module IDES8_MEM (...); +module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); parameter GSREN = "false"; parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; @@ -79,7 +79,7 @@ output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; endmodule -module OSER4_MEM (...); +module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; parameter HWL = "false"; @@ -92,7 +92,7 @@ output Q0, Q1; endmodule -module OSER8_MEM (...); +module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter GSREN = "false"; parameter LSREN = "true"; parameter HWL = "false"; @@ -105,7 +105,7 @@ output Q0, Q1; endmodule -module IODELAY (...); +module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); parameter C_STATIC_DLY = 0; input DI; input SDTAP; @@ -116,7 +116,7 @@ output DO; endmodule -module IEM (...); +module IEM(D, CLK, RESET, MCLK, LAG, LEAD); parameter WINSIZE = "SMALL"; parameter GSREN = "false"; parameter LSREN = "true"; @@ -125,14 +125,14 @@ output LAG, LEAD; endmodule -module ROM16 (...); +module ROM16(AD, DO); parameter INIT_0 = 16'h0000; input [3:0] AD; output DO; endmodule -module ROM (...); +module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; @@ -211,7 +211,7 @@ output [31:0] DO; endmodule -module ROMX9 (...); +module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; @@ -290,7 +290,7 @@ output [35:0] DO; endmodule -module pROM (...); +module pROM(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter RESET_MODE = "SYNC"; @@ -366,7 +366,7 @@ output [31:0] DO; endmodule -module pROMX9 (...); +module pROMX9(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter RESET_MODE = "SYNC"; @@ -442,7 +442,7 @@ output [35:0] DO; endmodule -module SDPB (...); +module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; parameter BIT_WIDTH_1 = 32; @@ -523,7 +523,7 @@ output [31:0] DO; endmodule -module SDPX9B (...); +module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 36; parameter BIT_WIDTH_1 = 36; @@ -604,7 +604,7 @@ output [35:0] DO; endmodule -module DPB (...); +module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -689,7 +689,7 @@ output [15:0] DOA, DOB; endmodule -module DPX9B (...); +module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -774,7 +774,7 @@ output [17:0] DOA, DOB; endmodule -module PADD18 (...); +module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [17:0] A; input [17:0] B; input ASEL; @@ -790,7 +790,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module PADD9 (...); +module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT); input [8:0] A; input [8:0] B; input ASEL; @@ -806,7 +806,7 @@ parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule -module MULT9X9 (...); +module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [8:0] A,SIA; input [8:0] B,SIB; input ASIGN,BSIGN; @@ -826,7 +826,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT18X18 (...); +module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); input [17:0] A,SIA; input [17:0] B,SIB; input ASIGN,BSIGN; @@ -846,7 +846,7 @@ parameter SOA_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULT36X36 (...); +module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); input [35:0] A; input [35:0] B; input ASIGN,BSIGN; @@ -864,7 +864,7 @@ parameter BSIGN_REG = 1'b0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU36X18 (...); +module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); input [17:0] A; input [35:0] B; input [53:0] C; @@ -889,7 +889,7 @@ parameter MULTALU36X18_MODE = 0; parameter C_ADD_SUB = 1'b0; endmodule -module MULTADDALU18X18 (...); +module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); input [17:0] A0; input [17:0] B0; input [17:0] A1; @@ -927,7 +927,7 @@ parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; endmodule -module MULTALU18X18 (...); +module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO); input [17:0] A, B; input CLK,CE,RESET; input ASIGN, BSIGN; @@ -953,7 +953,7 @@ parameter C_ADD_SUB = 1'b0; parameter MULTALU18X18_MODE = 0; endmodule -module ALU54D (...); +module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); input [53:0] A, B; input ASIGN,BSIGN; input ACCLOAD; @@ -973,19 +973,19 @@ parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; endmodule -module BUFG (...); +module BUFG(O, I); output O; input I; endmodule -module BUFS (...); +module BUFS(O, I); output O; input I; endmodule -module PLL (...); +module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3); input CLKIN; input CLKFB; input RESET; @@ -1026,39 +1026,39 @@ parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW2A-18"; endmodule -module TLVDS_IBUF (...); +module TLVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module TLVDS_TBUF (...); +module TLVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module TLVDS_IOBUF (...); +module TLVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module ELVDS_IBUF (...); +module ELVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module ELVDS_TBUF (...); +module ELVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module ELVDS_IOBUF (...); +module ELVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module CLKDIV (...); +module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT); input HCLKIN; input RESETN; input CALIB; @@ -1067,12 +1067,13 @@ parameter DIV_MODE = "2"; parameter GSREN = "false"; endmodule -module DHCEN (...); +module DHCEN(CLKIN, CE, CLKOUT); input CLKIN,CE; output CLKOUT; endmodule -module DQS (...); +module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID +, RBURST, RFLAG, WFLAG); input DQSIN,PCLK,FCLK,RESET; input [3:0] READ; input [2:0] RCLKSEL; @@ -1089,7 +1090,7 @@ output RVALID,RBURST, RFLAG, WFLAG; parameter GSREN = "false"; endmodule -module DLLDLY (...); +module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG); input CLKIN; input [7:0] DLLSTEP; input DIR,LOADN,MOVE; @@ -1100,67 +1101,67 @@ parameter DLY_SIGN = 1'b0; parameter DLY_ADJ = 0; endmodule -module DCS (...); +module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; parameter DCS_MODE = "RISING"; endmodule -module DQCE (...); +module DQCE(CLKIN, CE, CLKOUT); input CLKIN; input CE; output CLKOUT; endmodule -module CLKDIV2 (...); +module CLKDIV2(HCLKIN, RESETN, CLKOUT); parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule -module IBUF_R (...); +module IBUF_R(I, RTEN, O); input I; input RTEN; output O; endmodule -module IOBUF_R (...); +module IOBUF_R(I, OEN, RTEN, O, IO); input I,OEN; input RTEN; output O; inout IO; endmodule -module ELVDS_IBUF_R (...); +module ELVDS_IBUF_R(O, I, IB, RTEN); output O; input I, IB; input RTEN; endmodule -module ELVDS_IOBUF_R (...); +module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN); output O; inout IO, IOB; input I, OEN; input RTEN; endmodule -module OTP (...); +module OTP(CSB, SCLK, DOUT); input CSB, SCLK; output DOUT; endmodule -module SAMB (...); +module SAMB(SPIAD, LOADN_SPIAD); input [23:0] SPIAD; input LOADN_SPIAD; endmodule -module ELVDS_IBUF_MIPI (...); +module ELVDS_IBUF_MIPI(OH, OL, I, IB); output OH, OL; input I, IB; endmodule -module MIPI_IBUF (...); +module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN); output OH, OL, OB; inout IO, IOB; input I, IB; @@ -1168,7 +1169,7 @@ input OEN, OENB; input HSREN; endmodule -module I3C_IOBUF (...); +module I3C_IOBUF(O, IO, I, MODESEL); output O; inout IO; input I, MODESEL; diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index b2dc06236..dd6a540b3 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -1,75 +1,75 @@ // Created by cells_xtra.py -module LUT5 (...); +module LUT5(I0, I1, I2, I3, I4, F); parameter INIT = 32'h00000000; input I0, I1, I2, I3, I4; output F; endmodule -module LUT6 (...); +module LUT6(I0, I1, I2, I3, I4, I5, F); parameter INIT = 64'h0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5; output F; endmodule -module LUT7 (...); +module LUT7(I0, I1, I2, I3, I4, I5, I6, F); parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6; output F; endmodule -module LUT8 (...); +module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F); parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; input I0, I1, I2, I3, I4, I5, I6, I7; output F; endmodule -module ROM16 (...); +module ROM16(AD, DO); parameter INIT_0 = 16'h0000; input [3:0] AD; output DO; endmodule -module INV (...); +module INV(I, O); input I; output O; endmodule -module TLVDS_IBUF (...); +module TLVDS_IBUF(O, I, IB); output O; input I, IB; endmodule -module TLVDS_TBUF (...); +module TLVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module TLVDS_IOBUF (...); +module TLVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module ELVDS_TBUF (...); +module ELVDS_TBUF(O, OB, I, OEN); output O, OB; input I, OEN; endmodule -module ELVDS_IOBUF (...); +module ELVDS_IOBUF(O, IO, IOB, I, OEN); output O; inout IO, IOB; input I, OEN; endmodule -module MIPI_IBUF (...); +module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSEN, HSREN); output OH, OL, OB; inout IO, IOB; input I, IB; @@ -77,32 +77,33 @@ input OEN, OENB; input HSEN, HSREN; endmodule -module MIPI_OBUF_A (...); +module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL, IO, IOB, OEN, OENB); output O, OB; input I, IB, IL, MODESEL; inout IO, IOB; input OEN, OENB; endmodule -module ELVDS_IOBUF_R (...); +module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN); output O; inout IO, IOB; input I, OEN; input RTEN; endmodule -module I3C_IOBUF (...); +module I3C_IOBUF(O, IO, I, MODESEL); output O; inout IO; input I, MODESEL; endmodule -module TLVDS_IBUF_ADC (...); +module TLVDS_IBUF_ADC(I, IB, ADCEN); input I, IB; input ADCEN; endmodule -module MIPI_CPHY_IBUF (...); +module MIPI_CPHY_IBUF(OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2, IO0, IOB0, IO1, IOB1, IO2, IOB2, I0, IB0, I1, IB1, I2, IB2 +, OEN, OENB, HSEN); output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2; inout IO0, IOB0, IO1, IOB1, IO2, IOB2; input I0, IB0, I1, IB1, I2, IB2; @@ -110,14 +111,15 @@ input OEN, OENB; input HSEN; endmodule -module MIPI_CPHY_OBUF (...); +module MIPI_CPHY_OBUF(O0, OB0, O1, OB1, O2, OB2, I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2, IO0, IOB0, IO1, IOB1, IO2, IOB2 +, OEN, OENB, MODESEL, VCOME); output O0, OB0, O1, OB1, O2, OB2; input I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2; inout IO0, IOB0, IO1, IOB1, IO2, IOB2; input OEN, OENB, MODESEL, VCOME; endmodule -module SDPB (...); +module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, BLKSELA, BLKSELB, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; parameter BIT_WIDTH_1 = 32; @@ -198,7 +200,7 @@ output [31:0] DO; endmodule -module SDPX9B (...); +module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, BLKSELA, BLKSELB, DI, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 36; parameter BIT_WIDTH_1 = 36; @@ -279,7 +281,7 @@ output [35:0] DO; endmodule -module DPB (...); +module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -364,7 +366,7 @@ output [15:0] DOA, DOB; endmodule -module DPX9B (...); +module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); parameter READ_MODE0 = 1'b0; parameter READ_MODE1 = 1'b0; parameter WRITE_MODE0 = 2'b00; @@ -449,7 +451,7 @@ output [17:0] DOA, DOB; endmodule -module pROM (...); +module pROM(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 32; parameter RESET_MODE = "SYNC"; @@ -525,7 +527,7 @@ output [31:0] DO; endmodule -module pROMX9 (...); +module pROMX9(CLK, CE, OCE, RESET, AD, DO); parameter READ_MODE = 1'b0; parameter BIT_WIDTH = 36; parameter RESET_MODE = "SYNC"; @@ -601,7 +603,7 @@ output [35:0] DO; endmodule -module SDP36KE (...); +module SDP36KE(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, DIP, BLKSELA, BLKSELB, DECCI, SECCI, DO, DOP, DECCO, SECCO, ECCP); parameter ECC_WRITE_EN="TRUE"; parameter ECC_READ_EN="TRUE"; parameter READ_MODE = 1'b0; @@ -768,7 +770,7 @@ output [7:0] ECCP; endmodule -module SDP136K (...); +module SDP136K(CLKA, CLKB, WE, RE, ADA, ADB, DI, DO); input CLKA, CLKB; input WE, RE; input [10:0] ADA, ADB; @@ -776,7 +778,7 @@ input [67:0] DI; output [67:0] DO; endmodule -module MULTADDALU12X12 (...); +module MULTADDALU12X12(DOUT, CASO, A0, B0, A1, B1, CASI, ACCSEL, CASISEL, ADDSUB, CLK, CE, RESET); parameter A0REG_CLK = "BYPASS"; parameter A0REG_CE = "CE0"; parameter A0REG_RESET = "RESET0"; @@ -842,7 +844,7 @@ input [1:0] ADDSUB; input [1:0] CLK, CE, RESET; endmodule -module MULTALU27X18 (...); +module MULTALU27X18(DOUT, CASO, SOA, A, SIA, B, C, D, CASI, ACCSEL, PSEL, ASEL, PADDSUB, CSEL, CASISEL, ADDSUB, CLK, CE, RESET); parameter AREG_CLK = "BYPASS"; parameter AREG_CE = "CE0"; parameter AREG_RESET = "RESET0"; @@ -937,7 +939,7 @@ input [1:0] ADDSUB; input [1:0] CLK, CE, RESET; endmodule -module MULT12X12 (...); +module MULT12X12(DOUT, A, B, CLK, CE, RESET); parameter AREG_CLK = "BYPASS"; parameter AREG_CE = "CE0"; parameter AREG_RESET = "RESET0"; @@ -956,7 +958,7 @@ input [11:0] A, B; input [1:0] CLK, CE, RESET; endmodule -module MULT27X36 (...); +module MULT27X36(DOUT, A, B, D, CLK, CE, RESET, PSEL, PADDSUB); parameter AREG_CLK = "BYPASS"; parameter AREG_CE = "CE0"; parameter AREG_RESET = "RESET0"; @@ -992,7 +994,7 @@ input PSEL; input PADDSUB; endmodule -module MULTACC (...); +module MULTACC(DATAO, CASO, CE, CLK, COFFIN0, COFFIN1, COFFIN2, DATAIN0, DATAIN1, DATAIN2, RSTN, CASI); output [23:0] DATAO, CASO; input CE, CLK; input [5:0] COFFIN0, COFFIN1, COFFIN2; @@ -1010,7 +1012,7 @@ parameter CASI_EN = "FALSE"; parameter CASO_EN = "FALSE"; endmodule -module IDDR_MEM (...); +module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); input D, ICLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -1019,7 +1021,7 @@ output Q0,Q1; endmodule -module ODDR_MEM (...); +module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); parameter TCLK_SOURCE = "DQSW"; parameter TXCLK_POL = 1'b0; input D0, D1; @@ -1028,7 +1030,7 @@ output Q0, Q1; endmodule -module IDES4_MEM (...); +module IDES4_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3); input PCLK, D, ICLK, FCLK, RESET, CALIB; input [2:0] WADDR; input [2:0] RADDR; @@ -1036,7 +1038,7 @@ output Q0,Q1,Q2,Q3; endmodule -module IDES8_MEM (...); +module IDES8_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); input PCLK, D, ICLK, FCLK, RESET, CALIB; input [2:0] WADDR; input [2:0] RADDR; @@ -1044,19 +1046,20 @@ output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; endmodule -module IDES14 (...); +module IDES14(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13); input D, FCLK, PCLK, CALIB,RESET; output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13; endmodule -module IDES32 (...); +module IDES32(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 +, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31); input D, FCLK, PCLK, CALIB,RESET; output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31; endmodule -module OSER4_MEM (...); +module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter HWL = "false"; parameter TCLK_SOURCE = "DQSW"; parameter TXCLK_POL = 1'b0; @@ -1067,7 +1070,7 @@ output Q0, Q1; endmodule -module OSER8_MEM (...); +module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); parameter HWL = "false"; parameter TCLK_SOURCE = "DQSW"; parameter TXCLK_POL = 1'b0; @@ -1078,13 +1081,13 @@ output Q0, Q1; endmodule -module OSER14 (...); +module OSER14(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, PCLK, FCLK, RESET, Q); input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13; input PCLK, FCLK, RESET; output Q; endmodule -module IODELAY (...); +module IODELAY(DI, SDTAP, VALUE, DLYSTEP, DF, DO); parameter C_STATIC_DLY = 0; parameter DYN_DLY_EN = "FALSE"; parameter ADAPT_EN = "FALSE"; @@ -1097,7 +1100,7 @@ output DO; endmodule -module OSIDES32 (...); +module OSIDES32(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, SDTAP0, SDTAP1, VALUE0, VALUE1, DLYSTEP0, DLYSTEP1); output [31:0] Q; input D; input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; @@ -1114,7 +1117,8 @@ parameter DYN_DLY_EN_1 = "FALSE"; parameter ADAPT_EN_1 = "FALSE"; endmodule -module OSIDES64 (...); +module OSIDES64(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, DF2, DF3, SDTAP0, SDTAP1, SDTAP2, SDTAP3, VALUE0, VALUE1, VALUE2, VALUE3, DLYSTEP0 +, DLYSTEP1, DLYSTEP2, DLYSTEP3); output [63:0] Q; input D; input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN; @@ -1137,20 +1141,20 @@ parameter DYN_DLY_EN_3 = "FALSE"; parameter ADAPT_EN_3 = "FALSE"; endmodule -module DCE (...); +module DCE(CLKIN, CE, CLKOUT); input CLKIN; input CE; output CLKOUT; endmodule -module DCS (...); +module DCS(CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE, CLKSEL, CLKOUT); input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; parameter DCS_MODE = "RISING"; endmodule -module DDRDLL (...); +module DDRDLL(CLKIN, STOP, UPDNCNTL, RESET, STEP, LOCK); input CLKIN; input STOP; input UPDNCNTL; @@ -1163,7 +1167,7 @@ parameter SCAL_EN = "TRUE"; parameter DIV_SEL = 1'b0; endmodule -module DLLDLY (...); +module DLLDLY(CLKIN, DLLSTEP, CSTEP, LOADN, MOVE, CLKOUT, FLAG); input CLKIN; input [7:0] DLLSTEP, CSTEP; input LOADN,MOVE; @@ -1176,7 +1180,7 @@ parameter ADAPT_EN = "FALSE"; parameter STEP_SEL = 1'b0; endmodule -module CLKDIV (...); +module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT); input HCLKIN; input RESETN; input CALIB; @@ -1184,24 +1188,24 @@ output CLKOUT; parameter DIV_MODE = "2"; endmodule -module CLKDIV2 (...); +module CLKDIV2(HCLKIN, RESETN, CLKOUT); input HCLKIN, RESETN; output CLKOUT; endmodule -module DHCE (...); +module DHCE(CLKIN, CEN, CLKOUT); input CLKIN; input CEN; output CLKOUT; endmodule -module OSCA (...); +module OSCA(OSCOUT, OSCEN); parameter FREQ_DIV = 100; output OSCOUT; input OSCEN; endmodule -module OSCB (...); +module OSCB(OSCOUT, OSCREF, OSCEN, FMODE, RTRIM, RTCTRIM); parameter FREQ_MODE = "25"; parameter FREQ_DIV = 10; parameter DYN_TRIM_EN = "FALSE"; @@ -1212,7 +1216,9 @@ input [7:0] RTRIM; input [5:0] RTCTRIM; endmodule -module PLL (...); +module PLL(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, FBDSEL, IDSEL, MDSEL, MDSEL_FRAC, ODSEL0, ODSEL0_FRAC, ODSEL1, ODSEL2, ODSEL3, ODSEL4, ODSEL5, ODSEL6, DT0, DT1, DT2 +, DT3, ICPSEL, LPFRES, LPFCAP, PSSEL, PSDIR, PSPULSE, ENCLK0, ENCLK1, ENCLK2, ENCLK3, ENCLK4, ENCLK5, ENCLK6, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, LOCK, CLKOUT0, CLKOUT1 +, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT); input CLKIN; input CLKFB; input RESET; @@ -1354,7 +1360,8 @@ parameter LPF_CAP = 2'b00; parameter SSC_EN = "FALSE"; endmodule -module PLLA (...); +module PLLA(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, PSSEL, PSDIR, PSPULSE, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, MDCLK, MDOPC, MDAINC, MDWDI, MDRDO, LOCK, CLKOUT0, CLKOUT1 +, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT); input CLKIN; input CLKFB; input RESET; @@ -1462,7 +1469,14 @@ parameter LPF_CAP = 2'b00; parameter SSC_EN = "FALSE"; endmodule -module AE350_SOC (...); +module AE350_SOC(POR_N, HW_RSTN, CORE_CLK, DDR_CLK, AHB_CLK, APB_CLK, DBG_TCK, RTC_CLK, CORE_CE, AXI_CE, DDR_CE, AHB_CE, APB_CE, APB2AHB_CE, SCAN_TEST, SCAN_EN, PRESETN, HRESETN, DDR_RSTN, GP_INT, DMA_REQ +, DMA_ACK, CORE0_WFI_MODE, WAKEUP_IN, RTC_WAKEUP, TEST_CLK, TEST_MODE, TEST_RSTN, ROM_HADDR, ROM_HRDATA, ROM_HREADY, ROM_HRESP, ROM_HTRANS, ROM_HWRITE, APB_PADDR, APB_PENABLE, APB_PRDATA, APB_PREADY, APB_PSEL, APB_PWDATA, APB_PWRITE, APB_PSLVERR +, APB_PPROT, APB_PSTRB, EXTS_HRDATA, EXTS_HREADYIN, EXTS_HRESP, EXTS_HADDR, EXTS_HBURST, EXTS_HPROT, EXTS_HSEL, EXTS_HSIZE, EXTS_HTRANS, EXTS_HWDATA, EXTS_HWRITE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL +, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE, DDR_HADDR, DDR_HBURST, DDR_HPROT, DDR_HRDATA, DDR_HREADY, DDR_HRESP, DDR_HSIZE, DDR_HTRANS, DDR_HWDATA, DDR_HWRITE, TMS_IN, TRST_IN, TDI_IN, TDO_OUT, TDO_OE, SPI2_HOLDN_IN, SPI2_WPN_IN +, SPI2_CLK_IN, SPI2_CSN_IN, SPI2_MISO_IN, SPI2_MOSI_IN, SPI2_HOLDN_OUT, SPI2_HOLDN_OE, SPI2_WPN_OUT, SPI2_WPN_OE, SPI2_CLK_OUT, SPI2_CLK_OE, SPI2_CSN_OUT, SPI2_CSN_OE, SPI2_MISO_OUT, SPI2_MISO_OE, SPI2_MOSI_OUT, SPI2_MOSI_OE, I2C_SCL_IN, I2C_SDA_IN, I2C_SCL, I2C_SDA, UART1_TXD +, UART1_RTSN, UART1_RXD, UART1_CTSN, UART1_DSRN, UART1_DCDN, UART1_RIN, UART1_DTRN, UART1_OUT1N, UART1_OUT2N, UART2_TXD, UART2_RTSN, UART2_RXD, UART2_CTSN, UART2_DCDN, UART2_DSRN, UART2_RIN, UART2_DTRN, UART2_OUT1N, UART2_OUT2N, CH0_PWM, CH0_PWMOE +, CH1_PWM, CH1_PWMOE, CH2_PWM, CH2_PWMOE, CH3_PWM, CH3_PWMOE, GPIO_IN, GPIO_OE, GPIO_OUT, SCAN_IN, INTEG_TCK, INTEG_TDI, INTEG_TMS, INTEG_TRST, INTEG_TDO, SCAN_OUT, PGEN_CHAIN_I, PRDYN_CHAIN_O, EMA, EMAW, EMAS +, RET1N, RET2N); input POR_N; input HW_RSTN; input CORE_CLK; @@ -1614,7 +1628,8 @@ input RET1N; input RET2N; endmodule -module AE350_RAM (...); +module AE350_RAM(POR_N, HW_RSTN, CORE_CLK, AHB_CLK, APB_CLK, RTC_CLK, CORE_CE, AXI_CE, AHB_CE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE +, EMA, EMAW, EMAS, RET1N, RET2N); input POR_N; input HW_RSTN; input CORE_CLK; @@ -1643,20 +1658,20 @@ input RET1N; input RET2N; endmodule -module SAMB (...); +module SAMB(SPIAD, LOAD, ADWSEL); parameter MODE = 2'b00; input [23:0] SPIAD; input LOAD; input ADWSEL; endmodule -module OTP (...); +module OTP(CLK, READ, SHIFT, DOUT); parameter MODE = 2'b01; input CLK, READ, SHIFT; output DOUT; endmodule -module CMSER (...); +module CMSER(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERRINJECT, ERRINJLOC); output RUNNING; output CRCERR; output CRCDONE; @@ -1675,7 +1690,7 @@ input ERRINJECT; input [6:0] ERRINJLOC; endmodule -module CMSERA (...); +module CMSERA(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERR0LOC, ERR1LOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC); output RUNNING; output CRCERR; output CRCDONE; @@ -1695,7 +1710,7 @@ input ERR0INJECT,ERR1INJECT; input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule -module CMSERB (...); +module CMSERB(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC); output RUNNING; output CRCERR; output CRCDONE; @@ -1714,13 +1729,13 @@ input ERR0INJECT,ERR1INJECT; input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule -module SAMBA (...); +module SAMBA(SPIAD, LOAD); parameter MODE = 2'b00; input SPIAD; input LOAD; endmodule -module LICD (...); +module LICD(); parameter STAGE_NUM = 2'b00; parameter ENCDEC_NUM = 2'b00; parameter CODE_WIDTH = 2'b00; @@ -1728,7 +1743,13 @@ module LICD (...); parameter INTERLEAVE_MODE = 3'b000; endmodule -module MIPI_DPHY (...); +module MIPI_DPHY(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N +, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1 +, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0 +, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1 +, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK, D1LN_DESKEW_DONE +, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK +, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK); output RX_CLK_O, TX_CLK_O; output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; @@ -2024,7 +2045,13 @@ parameter TEST_P_IMP_LN3 = 1'b0 ; parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule -module MIPI_DPHYA (...); +module MIPI_DPHYA(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N +, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1 +, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0 +, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1 +, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, SPLL_CKN, SPLL_CKP, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3 +, ALPEDO_LANECK, D1LN_DESKEW_DONE, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2 +, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK); output RX_CLK_O, TX_CLK_O; output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; @@ -2323,7 +2350,12 @@ parameter TEST_P_IMP_LN3 = 1'b0 ; parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule -module MIPI_CPHY (...); +module MIPI_CPHY(D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD, D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR, D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA, D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O +, HSTX_FIFO_AE, HSTX_FIFO_AF, HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR, RX_CLK_MUXED, TX_CLK_1X_O, DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C, MDRP_RDATA, D0A, D0B, D0C, D1A, D1B +, D1C, D2A, D2B, D2C, D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN, D0LN_HSTX_DATA, D1LN_HSTX_DATA, D2LN_HSTX_DATA, D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD, D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS, D0LN_RX_CLK_1X_I, D1LN_RX_CLK_1X_I +, D2LN_RX_CLK_1X_I, D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N, HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2, MDRP_A_D_I, MDRP_A_INC_I, MDRP_CLK_I, MDRP_OPCODE_I, PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX +, ARST_RXLN0, ARST_RXLN1, ARST_RXLN2, ARSTN_TX, RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2, TX_CLK_1X_I, TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2, TXHCLK_EN, DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2 +, GPLL_CK0, GPLL_CK90, GPLL_CK180, GPLL_CK270, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP); output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD; output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD; output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD; @@ -2455,29 +2487,30 @@ parameter EQ_PBIAS_LN2 = 4'b0100; parameter EQ_ZLD_LN2 = 4'b1000; endmodule -module GTR12_QUAD (...); +module GTR12_QUAD(); parameter POSITION = "Q0"; endmodule -module GTR12_UPAR (...); +module GTR12_UPAR(); endmodule -module GTR12_PMAC (...); +module GTR12_PMAC(); endmodule -module GTR12_QUADA (...); +module GTR12_QUADA(); endmodule -module GTR12_UPARA (...); +module GTR12_UPARA(); endmodule -module GTR12_PMACA (...); +module GTR12_PMACA(); endmodule -module GTR12_QUADB (...); +module GTR12_QUADB(); endmodule -module DQS (...); +module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID +, RBURST, RFLAG, WFLAG); input DQSIN,PCLK,FCLK,RESET; input [3:0] READ; input [2:0] RCLKSEL; diff --git a/techlibs/gowin/dsp_map.v b/techlibs/gowin/dsp_map.v new file mode 100644 index 000000000..f03bcdff0 --- /dev/null +++ b/techlibs/gowin/dsp_map.v @@ -0,0 +1,70 @@ +module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y); + + parameter A_WIDTH = 9; + parameter B_WIDTH = 9; + parameter Y_WIDTH = 18; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT9X9 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .CE(1'b0), + .RESET(1'b0), + .A(A), + .SIA({A_WIDTH{1'b0}}), + .ASEL(1'b0), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .SIB({B_WIDTH{1'b0}}), + .BSEL(1'b0), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); + +endmodule + +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + + parameter A_WIDTH = 18; + parameter B_WIDTH = 18; + parameter Y_WIDTH = 36; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT18X18 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .CE(1'b0), + .RESET(1'b0), + .A(A), + .SIA({A_WIDTH{1'b0}}), + .ASEL(1'b0), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .SIB({B_WIDTH{1'b0}}), + .BSEL(1'b0), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); + +endmodule + +module \$__MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y); + + parameter A_WIDTH = 36; + parameter B_WIDTH = 36; + parameter Y_WIDTH = 72; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT36X36 __TECHMAP_REPLACE__ ( + .CLK(1'b0), + .RESET(1'b0), + .CE(1'b0), + .A(A), + .ASIGN(A_SIGNED ? 1'b1 : 1'b0), + .B(B), + .BSIGN(B_SIGNED ? 1'b1 : 1'b0), + .DOUT(Y) + ); + +endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index b9902659c..3d1414e9e 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -29,6 +29,21 @@ struct SynthGowinPass : public ScriptPass { SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { } + struct DSPRule { + int a_maxwidth; + int b_maxwidth; + int a_minwidth; + int b_minwidth; + std::string prim; + }; + + const std::vector dsp_rules = { + {36, 36, 22, 22, "$__MUL36X36"}, + {18, 18, 10, 4, "$__MUL18X18"}, + {18, 18, 4, 10, "$__MUL18X18"}, + {9, 9, 4, 4, "$__MUL9X9"}, + }; + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -97,13 +112,16 @@ struct SynthGowinPass : public ScriptPass log(" -setundef\n"); log(" set undriven wires and parameters to zero\n"); log("\n"); + log(" -nodsp\n"); + log(" do not infer DSP multipliers\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_opt, vout_file, json_file, family; - bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef; + bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef, nodsp; void clear_flags() override { @@ -123,6 +141,7 @@ struct SynthGowinPass : public ScriptPass noalu = false; no_rw_check = false; setundef = false; + nodsp = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -209,6 +228,10 @@ struct SynthGowinPass : public ScriptPass setundef = true; continue; } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } break; } extra_args(args, argidx, design); @@ -239,17 +262,40 @@ struct SynthGowinPass : public ScriptPass run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } - if (flatten && check_label("flatten", "(unless -noflatten)")) - { - run("proc"); - run("flatten"); - run("tribuf -logic"); - run("deminout"); - } - if (check_label("coarse")) { - run("synth -run coarse" + no_rw_check_opt); + run("proc"); + if (flatten || help_mode) + run("flatten", "(unless -noflatten)"); + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + + if (help_mode) { + run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp and if -family gw1n or gw2a)"); + run("techmap -map +/gowin/dsp_map.v", "(unless -nodsp and if -family gw1n or gw2a)"); + } else if (!nodsp && (family == "gw1n" || family == "gw2a")) { + for (const auto &rule : dsp_rules) { + run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s", + rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim)); + run("chtype -set $mul t:$__soft_mul"); + } + run("techmap -map +/gowin/dsp_map.v"); + } + + run("alumacc"); + run("opt"); + run("memory -nomap" + no_rw_check_opt); + run("opt_clean"); } if (check_label("map_ram")) @@ -311,6 +357,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_luts")) { + run("sort"); if (nowidelut && abc9) { run("read_verilog -icells -lib -specify +/abc9_model.v"); run("abc9 -maxlut 4 -W 500"); diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc index 82218ff11..f62019617 100644 --- a/techlibs/ice40/ice40_wrapcarry.cc +++ b/techlibs/ice40/ice40_wrapcarry.cc @@ -138,7 +138,7 @@ struct Ice40WrapCarryPass : public Pass { lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; else if (a.first == ID::src) src = a.second; - else if (a.first.in(IdString{"\\SB_LUT4.name"}, ID::keep, ID::module_not_derived)) + else if (a.first.in(IdString{"\\SB_LUT4.name"}, ID::keep, ID::module_not_derived, ID::src)) continue; else log_abort(); diff --git a/techlibs/lattice/cells_bb_ecp5.v b/techlibs/lattice/cells_bb_ecp5.v index 1b1b9a1f4..61f3da502 100644 --- a/techlibs/lattice/cells_bb_ecp5.v +++ b/techlibs/lattice/cells_bb_ecp5.v @@ -1,24 +1,29 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) -module PUR (...); +module PUR(PUR); parameter RST_PULSE = 1; input PUR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module PDPW16KD (...); +module PDPW16KD(DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15 +, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6, ADW5, ADW4, ADW3 +, ADW2, ADW1, ADW0, BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27 +, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6 +, DO5, DO4, DO3, DO2, DO1, DO0); parameter CLKRMUX = "CLKR"; parameter CLKWMUX = "CLKW"; parameter DATA_WIDTH_W = 36; @@ -208,7 +213,18 @@ module PDPW16KD (...); endmodule (* blackbox *) -module MULT18X18D (...); +module MULT18X18D(A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, B17, B16, B15 +, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, C17, C16, C15, C14, C13, C12 +, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, CLK3, CLK2, CLK1, CLK0, CE3 +, CE2, CE1, CE0, RST3, RST2, RST1, RST0, SRIA17, SRIA16, SRIA15, SRIA14, SRIA13, SRIA12, SRIA11, SRIA10, SRIA9, SRIA8, SRIA7, SRIA6, SRIA5, SRIA4 +, SRIA3, SRIA2, SRIA1, SRIA0, SRIB17, SRIB16, SRIB15, SRIB14, SRIB13, SRIB12, SRIB11, SRIB10, SRIB9, SRIB8, SRIB7, SRIB6, SRIB5, SRIB4, SRIB3, SRIB2, SRIB1 +, SRIB0, SROA17, SROA16, SROA15, SROA14, SROA13, SROA12, SROA11, SROA10, SROA9, SROA8, SROA7, SROA6, SROA5, SROA4, SROA3, SROA2, SROA1, SROA0, SROB17, SROB16 +, SROB15, SROB14, SROB13, SROB12, SROB11, SROB10, SROB9, SROB8, SROB7, SROB6, SROB5, SROB4, SROB3, SROB2, SROB1, SROB0, ROA17, ROA16, ROA15, ROA14, ROA13 +, ROA12, ROA11, ROA10, ROA9, ROA8, ROA7, ROA6, ROA5, ROA4, ROA3, ROA2, ROA1, ROA0, ROB17, ROB16, ROB15, ROB14, ROB13, ROB12, ROB11, ROB10 +, ROB9, ROB8, ROB7, ROB6, ROB5, ROB4, ROB3, ROB2, ROB1, ROB0, ROC17, ROC16, ROC15, ROC14, ROC13, ROC12, ROC11, ROC10, ROC9, ROC8, ROC7 +, ROC6, ROC5, ROC4, ROC3, ROC2, ROC1, ROC0, P35, P34, P33, P32, P31, P30, P29, P28, P27, P26, P25, P24, P23, P22 +, P21, P20, P19, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1 +, P0, SIGNEDP); parameter REG_INPUTA_CLK = "NONE"; parameter REG_INPUTA_CE = "CE0"; parameter REG_INPUTA_RST = "RST0"; @@ -470,7 +486,28 @@ module MULT18X18D (...); endmodule (* blackbox *) -module ALU54B (...); +module ALU54B(CE3, CE2, CE1, CE0, CLK3, CLK2, CLK1, CLK0, RST3, RST2, RST1, RST0, SIGNEDIA, SIGNEDIB, SIGNEDCIN, A35, A34, A33, A32, A31, A30 +, A29, A28, A27, A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9 +, A8, A7, A6, A5, A4, A3, A2, A1, A0, B35, B34, B33, B32, B31, B30, B29, B28, B27, B26, B25, B24 +, B23, B22, B21, B20, B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3 +, B2, B1, B0, C53, C52, C51, C50, C49, C48, C47, C46, C45, C44, C43, C42, C41, C40, C39, C38, C37, C36 +, C35, C34, C33, C32, C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17, C16, C15 +, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, CFB53, CFB52, CFB51, CFB50, CFB49, CFB48 +, CFB47, CFB46, CFB45, CFB44, CFB43, CFB42, CFB41, CFB40, CFB39, CFB38, CFB37, CFB36, CFB35, CFB34, CFB33, CFB32, CFB31, CFB30, CFB29, CFB28, CFB27 +, CFB26, CFB25, CFB24, CFB23, CFB22, CFB21, CFB20, CFB19, CFB18, CFB17, CFB16, CFB15, CFB14, CFB13, CFB12, CFB11, CFB10, CFB9, CFB8, CFB7, CFB6 +, CFB5, CFB4, CFB3, CFB2, CFB1, CFB0, MA35, MA34, MA33, MA32, MA31, MA30, MA29, MA28, MA27, MA26, MA25, MA24, MA23, MA22, MA21 +, MA20, MA19, MA18, MA17, MA16, MA15, MA14, MA13, MA12, MA11, MA10, MA9, MA8, MA7, MA6, MA5, MA4, MA3, MA2, MA1, MA0 +, MB35, MB34, MB33, MB32, MB31, MB30, MB29, MB28, MB27, MB26, MB25, MB24, MB23, MB22, MB21, MB20, MB19, MB18, MB17, MB16, MB15 +, MB14, MB13, MB12, MB11, MB10, MB9, MB8, MB7, MB6, MB5, MB4, MB3, MB2, MB1, MB0, CIN53, CIN52, CIN51, CIN50, CIN49, CIN48 +, CIN47, CIN46, CIN45, CIN44, CIN43, CIN42, CIN41, CIN40, CIN39, CIN38, CIN37, CIN36, CIN35, CIN34, CIN33, CIN32, CIN31, CIN30, CIN29, CIN28, CIN27 +, CIN26, CIN25, CIN24, CIN23, CIN22, CIN21, CIN20, CIN19, CIN18, CIN17, CIN16, CIN15, CIN14, CIN13, CIN12, CIN11, CIN10, CIN9, CIN8, CIN7, CIN6 +, CIN5, CIN4, CIN3, CIN2, CIN1, CIN0, OP10, OP9, OP8, OP7, OP6, OP5, OP4, OP3, OP2, OP1, OP0, R53, R52, R51, R50 +, R49, R48, R47, R46, R45, R44, R43, R42, R41, R40, R39, R38, R37, R36, R35, R34, R33, R32, R31, R30, R29 +, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R12, R11, R10, R9, R8 +, R7, R6, R5, R4, R3, R2, R1, R0, CO53, CO52, CO51, CO50, CO49, CO48, CO47, CO46, CO45, CO44, CO43, CO42, CO41 +, CO40, CO39, CO38, CO37, CO36, CO35, CO34, CO33, CO32, CO31, CO30, CO29, CO28, CO27, CO26, CO25, CO24, CO23, CO22, CO21, CO20 +, CO19, CO18, CO17, CO16, CO15, CO14, CO13, CO12, CO11, CO10, CO9, CO8, CO7, CO6, CO5, CO4, CO3, CO2, CO1, CO0, EQZ +, EQZM, EQOM, EQPAT, EQPATB, OVER, UNDER, OVERUNDER, SIGNEDR); parameter REG_INPUTC0_CLK = "NONE"; parameter REG_INPUTC0_CE = "CE0"; parameter REG_INPUTC0_RST = "RST0"; @@ -970,7 +1007,7 @@ module ALU54B (...); endmodule (* blackbox *) -module CLKDIVF (...); +module CLKDIVF(CLKI, RST, ALIGNWD, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input CLKI; @@ -980,7 +1017,7 @@ module CLKDIVF (...); endmodule (* blackbox *) -module PCSCLKDIV (...); +module PCSCLKDIV(CLKI, RST, SEL2, SEL1, SEL0, CDIV1, CDIVX); parameter GSR = "DISABLED"; input CLKI; input RST; @@ -992,7 +1029,7 @@ module PCSCLKDIV (...); endmodule (* blackbox *) -module DCSC (...); +module DCSC(CLK1, CLK0, SEL1, SEL0, MODESEL, DCSOUT); parameter DCSMODE = "POS"; input CLK1; input CLK0; @@ -1003,21 +1040,21 @@ module DCSC (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) -module ECLKSYNCB (...); +module ECLKSYNCB(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -1025,7 +1062,7 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DELAYF (...); +module DELAYF(A, LOADN, MOVE, DIRECTION, Z, CFLAG); parameter DEL_MODE = "USER_DEFINED"; parameter DEL_VALUE = 0; input A; @@ -1037,7 +1074,7 @@ module DELAYF (...); endmodule (* blackbox *) -module DELAYG (...); +module DELAYG(A, Z); parameter DEL_MODE = "USER_DEFINED"; parameter DEL_VALUE = 0; input A; @@ -1045,13 +1082,14 @@ module DELAYG (...); endmodule (* blackbox *) (* keep *) -module USRMCLK (...); +module USRMCLK(USRMCLKI, USRMCLKTS); input USRMCLKI; input USRMCLKTS; endmodule (* blackbox *) -module DQSBUFM (...); +module DQSBUFM(DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, ECLK, SCLK, RST, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, PAUSE, RDLOADN, RDMOVE +, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID, BURSTDET, RDCFLAG, WRCFLAG); parameter DQS_LI_DEL_VAL = 4; parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; parameter DQS_LO_DEL_VAL = 0; @@ -1098,7 +1136,7 @@ module DQSBUFM (...); endmodule (* blackbox *) -module DDRDLLA (...); +module DDRDLLA(CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0); parameter FORCE_MAX_DELAY = "NO"; parameter GSR = "ENABLED"; input CLK; @@ -1118,7 +1156,7 @@ module DDRDLLA (...); endmodule (* blackbox *) -module DLLDELD (...); +module DLLDELD(A, DDRDEL, LOADN, MOVE, DIRECTION, Z, CFLAG); input A; input DDRDEL; input LOADN; @@ -1129,7 +1167,7 @@ module DLLDELD (...); endmodule (* blackbox *) -module IDDRX1F (...); +module IDDRX1F(D, SCLK, RST, Q0, Q1); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1139,7 +1177,7 @@ module IDDRX1F (...); endmodule (* blackbox *) -module IDDRX2F (...); +module IDDRX2F(D, SCLK, ECLK, RST, ALIGNWD, Q3, Q2, Q1, Q0); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1153,7 +1191,7 @@ module IDDRX2F (...); endmodule (* blackbox *) -module IDDR71B (...); +module IDDR71B(D, SCLK, ECLK, RST, ALIGNWD, Q6, Q5, Q4, Q3, Q2, Q1, Q0); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1170,7 +1208,7 @@ module IDDR71B (...); endmodule (* blackbox *) -module IDDRX2DQA (...); +module IDDRX2DQA(SCLK, ECLK, DQSR90, D, RST, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, Q3, Q2, Q1, Q0, QWL); parameter GSR = "ENABLED"; input SCLK; input ECLK; @@ -1191,7 +1229,7 @@ module IDDRX2DQA (...); endmodule (* blackbox *) -module ODDRX1F (...); +module ODDRX1F(SCLK, RST, D0, D1, Q); parameter GSR = "ENABLED"; input SCLK; input RST; @@ -1201,7 +1239,7 @@ module ODDRX1F (...); endmodule (* blackbox *) -module ODDRX2F (...); +module ODDRX2F(SCLK, ECLK, RST, D3, D2, D1, D0, Q); parameter GSR = "ENABLED"; input SCLK; input ECLK; @@ -1214,7 +1252,7 @@ module ODDRX2F (...); endmodule (* blackbox *) -module ODDR71B (...); +module ODDR71B(SCLK, ECLK, RST, D6, D5, D4, D3, D2, D1, D0, Q); parameter GSR = "ENABLED"; input SCLK; input ECLK; @@ -1230,7 +1268,7 @@ module ODDR71B (...); endmodule (* blackbox *) -module OSHX2A (...); +module OSHX2A(D1, D0, SCLK, ECLK, RST, Q); parameter GSR = "ENABLED"; input D1; input D0; @@ -1241,7 +1279,7 @@ module OSHX2A (...); endmodule (* blackbox *) -module TSHX2DQA (...); +module TSHX2DQA(T1, T0, SCLK, ECLK, DQSW270, RST, Q); parameter GSR = "ENABLED"; parameter REGSET = "SET"; input T1; @@ -1254,7 +1292,7 @@ module TSHX2DQA (...); endmodule (* blackbox *) -module TSHX2DQSA (...); +module TSHX2DQSA(T1, T0, SCLK, ECLK, DQSW, RST, Q); parameter GSR = "ENABLED"; parameter REGSET = "SET"; input T1; @@ -1267,7 +1305,7 @@ module TSHX2DQSA (...); endmodule (* blackbox *) -module ODDRX2DQA (...); +module ODDRX2DQA(D3, D2, D1, D0, DQSW270, SCLK, ECLK, RST, Q); parameter GSR = "ENABLED"; input D3; input D2; @@ -1281,7 +1319,7 @@ module ODDRX2DQA (...); endmodule (* blackbox *) -module ODDRX2DQSB (...); +module ODDRX2DQSB(D3, D2, D1, D0, SCLK, ECLK, DQSW, RST, Q); parameter GSR = "ENABLED"; input D3; input D2; @@ -1295,7 +1333,8 @@ module ODDRX2DQSB (...); endmodule (* blackbox *) -module EHXPLLL (...); +module EHXPLLL(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, STDBY, PLLWAKESYNC, RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK +, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -1357,7 +1396,7 @@ module EHXPLLL (...); endmodule (* blackbox *) -module DTR (...); +module DTR(STARTPULSE, DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0); parameter DTR_TEMP = 25; input STARTPULSE; output DTROUT7; @@ -1371,13 +1410,13 @@ module DTR (...); endmodule (* blackbox *) -module OSCG (...); +module OSCG(OSC); parameter DIV = 128; output OSC; endmodule (* blackbox *) -module EXTREFB (...); +module EXTREFB(REFCLKP, REFCLKN, REFCLKO); parameter REFCK_PWDNB = "DONTCARE"; parameter REFCK_RTERM = "DONTCARE"; parameter REFCK_DCBIAS_EN = "DONTCARE"; @@ -1389,7 +1428,7 @@ module EXTREFB (...); endmodule (* blackbox *) (* keep *) -module JTAGG (...); +module JTAGG(TCK, TMS, TDI, JTDO2, JTDO1, TDO, JTDI, JTCK, JRTI2, JRTI1, JSHIFT, JUPDATE, JRSTN, JCE2, JCE1); parameter ER1 = "ENABLED"; parameter ER2 = "ENABLED"; (* iopad_external_pin *) @@ -1414,7 +1453,20 @@ module JTAGG (...); endmodule (* blackbox *) (* keep *) -module DCUA (...); +module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2 +, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, CH0_FF_TX_D_12, CH1_FF_TX_D_12 +, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23 +, CH1_FF_TX_D_23, CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX +, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB +, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, CH0_SCIEN, CH1_SCIEN +, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7 +, D_SCAN_MODE, D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND +, D_TXPLL_LOL_TO_ND, CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3 +, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, CH0_FF_RX_D_14 +, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE +, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE +, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2 +, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, D_REFCLKI, D_FFS_PLOL); parameter D_MACROPDB = "DONTCARE"; parameter D_IB_PWDNB = "DONTCARE"; parameter D_XGE_MODE = "DONTCARE"; diff --git a/techlibs/lattice/cells_bb_nexus.v b/techlibs/lattice/cells_bb_nexus.v index 6cf3a645d..42da827d6 100644 --- a/techlibs/lattice/cells_bb_nexus.v +++ b/techlibs/lattice/cells_bb_nexus.v @@ -1,6 +1,7 @@ // Created by cells_xtra.py from Lattice models -module ACC54 (...); +module ACC54(SFTCTRL, DSPIN, PP, CINPUT, LOAD, M9ADDSUB, ADDSUB, CIN, CASIN, CEO, RSTO, CEC, RSTC, CLK, SIGNEDI, SUM1, SUM0, DSPOUT, CASCOUT, ROUNDEN, CECIN +, CECTRL, RSTCIN, RSTCTRL); parameter SIGN = "DISABLED"; parameter M9ADDSUB_CTRL = "ADDITION"; parameter ADDSUB_CTRL = "ADD_ADD_CTRL_54_BIT_ADDER"; @@ -60,7 +61,8 @@ module ACC54 (...); input RSTCTRL; endmodule -module ADC (...); +module ADC(DN0, DN1, DP0, DP1, ADCEN, CAL, CALRDY, CHAEN, CHASEL, CHBEN, CHBSEL, CLKDCLK, CLKFAB, COG, COMP1IN, COMP1IP, COMP1OL, COMP2IN, COMP2IP, COMP2OL, COMP3IN +, COMP3IP, COMP3OL, CONVSTOP, DA, DB, EOC, GPION, GPIOP, RESETN, RSTN, SOC, COMP1O, COMP2O, COMP3O); parameter ADC_ENP = "ENABLED"; parameter CLK_DIV = "2"; parameter CTLCOMPSW1 = "DISABLED"; @@ -120,7 +122,8 @@ module ADC (...); output COMP3O; endmodule -module ALUREG (...); +module ALUREG(ALUCLK, ALUFLAGC, ALUFLAGV, ALUFLAGZ, ALUFORWARDA, ALUFORWARDB, ALUIREGEN, ALUOREGEN, ALURST, DATAA, DATAB, DATAC, OPC, OPCCUSTOM, RADDRA, RADDRB, RDATAA, RDATAB, REGCLK, REGCLKEN, REGRST +, RESULT, WADDR, WDROTATE, WDSIGNEXT, WDSIZE, WDATA, WREN); parameter ALURST_ACTIVELOW = "DISABLE"; parameter GSR = "ENABLED"; parameter INREG = "DISABLE"; @@ -163,21 +166,21 @@ module ALUREG (...); endmodule (* keep *) -module BB_ADC (...); +module BB_ADC(IOPAD, INADC); (* iopad_external_pin *) inout IOPAD; output INADC; endmodule (* keep *) -module BB_CDR (...); +module BB_CDR(IOPAD, INADC); (* iopad_external_pin *) inout IOPAD; output INADC; endmodule (* keep *) -module BB_I3C_A (...); +module BB_I3C_A(IOPAD, PADDI, PADDO, PADDT, I3CRESEN, I3CWKPU); (* iopad_external_pin *) inout IOPAD; output PADDI; @@ -187,7 +190,7 @@ module BB_I3C_A (...); input I3CWKPU; endmodule -module BFD1P3KX (...); +module BFD1P3KX(DOUT, DIN, DT, CEOUT, CLKOUT, SROUT, CEIN, CLKIN, SRIN, QOUT, QIN, QT); parameter GSR = "ENABLED"; parameter OUTSET = "RESET"; parameter INSET = "RESET"; @@ -206,7 +209,7 @@ module BFD1P3KX (...); output QT; endmodule -module BFD1P3LX (...); +module BFD1P3LX(DOUT, DIN, DT, CEOUT, CLKOUT, SROUT, CEIN, CLKIN, SRIN, QOUT, QIN, QT); parameter GSR = "ENABLED"; parameter OUTSET = "RESET"; parameter INSET = "RESET"; @@ -226,7 +229,7 @@ module BFD1P3LX (...); endmodule (* keep *) -module BNKREF18 (...); +module BNKREF18(STDBYINR, STDBYDIF, PVTCODE); parameter BANK = "0b0000"; parameter STANDBY_DIFFIO = "DISABLED"; parameter STANDBY_INR = "DISABLED"; @@ -236,7 +239,7 @@ module BNKREF18 (...); endmodule (* keep *) -module CONFIG_LMMI (...); +module CONFIG_LMMI(LMMICLK, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIREADY, LMMIRDATAVALID, LMMIRESETN, RSTSMCLK, SMCLK); parameter LMMI_EN = "DIS"; input LMMICLK; input LMMIREQUEST; @@ -251,7 +254,7 @@ module CONFIG_LMMI (...); input SMCLK; endmodule -module DDRDLL (...); +module DDRDLL(CODE, FREEZE, LOCK, CLKIN, RST, DCNTL, UDDCNTL_N); parameter GSR = "ENABLED"; parameter ENA_ROUNDOFF = "ENABLED"; parameter FORCE_MAX_DELAY = "CODE_OR_LOCK_FROM_DLL_LOOP"; @@ -264,7 +267,7 @@ module DDRDLL (...); input UDDCNTL_N; endmodule -module DELAYA (...); +module DELAYA(A, LOAD_N, MOVE, DIRECTION, COARSE0, COARSE1, RANKSELECT, RANKENABLE, RANK0UPDATE, RANK1UPDATE, Z, EDETERR, CFLAG); parameter DEL_MODE = "USER_DEFINED"; parameter DEL_VALUE = "0"; parameter COARSE_DELAY_MODE = "STATIC"; @@ -286,7 +289,7 @@ module DELAYA (...); output CFLAG; endmodule -module DELAYB (...); +module DELAYB(A, Z); parameter DEL_VALUE = "0"; parameter COARSE_DELAY = "0NS"; parameter DEL_MODE = "USER_DEFINED"; @@ -295,7 +298,7 @@ module DELAYB (...); endmodule (* keep *) -module DIFFIO18 (...); +module DIFFIO18(PADDO, DOLP, IOPAD, PADDI, INLP, PADDT, INADC, HSRXEN, HSTXEN); parameter PULLMODE = "DOWN"; parameter ENADC_IN = "DISABLED"; parameter MIPI = "DISABLED"; @@ -311,7 +314,7 @@ module DIFFIO18 (...); input HSTXEN; endmodule -module DLLDEL (...); +module DLLDEL(CLKIN, CLKOUT, CODE, COUT, DIR, LOAD_N, MOVE); parameter ADJUST = "0"; parameter DEL_ADJUST = "PLUS"; parameter ENABLE = "ENABLED"; @@ -324,7 +327,12 @@ module DLLDEL (...); input MOVE; endmodule -module DP16K_MODE (...); +module DP16K_MODE(DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, DIA9, DIA10, DIA11, DIA12, DIA13, DIA14, DIA15, DIA16, DIA17, DIB0, DIB1, DIB2 +, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, DIB9, DIB10, DIB11, DIB12, DIB13, DIB14, DIB15, DIB16, DIB17, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5 +, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, ADA13, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 +, ADB13, CLKA, CLKB, CEA, CEB, WEA, WEB, CSA0, CSA1, CSA2, CSB0, CSB1, CSB2, RSTA, RSTB, DOA0, DOA1, DOA2, DOA3, DOA4, DOA5 +, DOA6, DOA7, DOA8, DOA9, DOA10, DOA11, DOA12, DOA13, DOA14, DOA15, DOA16, DOA17, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 +, DOB9, DOB10, DOB11, DOB12, DOB13, DOB14, DOB15, DOB16, DOB17); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -517,7 +525,7 @@ module DP16K_MODE (...); output DOB17; endmodule -module DP16K (...); +module DP16K(DIA, DIB, ADA, ADB, CLKA, CLKB, CEA, CEB, WEA, WEB, CSA, CSB, RSTA, RSTB, DOA, DOB); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -613,7 +621,20 @@ module DP16K (...); endmodule (* keep *) -module DPHY (...); +module DPHY(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, BITCKEXT, CKN, CKP, CLKREF, D0ACTIVE, D0BYTCNT, D0ERRCNT, D0PASS, D0VALID, D1ACTIVE, D1BYTCNT, D1ERRCNT +, D1PASS, D1VALID, D2ACTIVE, D2BYTCNT, D2ERRCNT, D2PASS, D2VALID, D3ACTIVE, D3BYTCNT, D3ERRCNT, D3PASS, D3VALID, DCTSTOUT, DN0, DN1, DN2, DN3, DP0, DP1, DP2, DP3 +, LOCK, PDDPHY, PDPLL, SCCLKIN, UDIR, UED0THEN, UERCLP0, UERCLP1, UERCTRL, UERE, UERSTHS, UERSSHS, UERSE, UFRXMODE, UTXMDTX, URXACTHS, URXCKE, URXCKINE, URXDE, URXDHS, URXLPDTE +, URXSKCHS, URXDRX, URXSHS, URE0D3DP, URE1D3DN, URE2CKDP, URE3CKDN, URXULPSE, URXVDE, URXVDHS, USSTT, UTDIS, UTXCKE, UDE0D0TN, UDE1D1TN, UDE2D2TN, UDE3D3TN, UDE4CKTN, UDE5D0RN, UDE6D1RN, UDE7D2RN +, UTXDHS, UTXENER, UTXRRS, UTXRYP, UTXRYSK, UTXRD0EN, UTRD0SEN, UTXSKD0N, UTXTGE0, UTXTGE1, UTXTGE2, UTXTGE3, UTXULPSE, UTXUPSEX, UTXVDE, UTXWVDHS, UUSAN, U1DIR, U1ENTHEN, U1ERCLP0, U1ERCLP1 +, U1ERCTRL, U1ERE, U1ERSTHS, U1ERSSHS, U1ERSE, U1FRXMD, U1FTXST, U1RXATHS, U1RXCKE, U1RXDE, U1RXDHS, U1RXDTE, U1RXSKS, U1RXSK, U1RXSHS, U1RE0D, U1RE1CN, U1RE2D, U1RE3N, U1RXUPSE, U1RXVDE +, U1RXVDHS, U1SSTT, U1TDIS, U1TREQ, U1TDE0D3, U1TDE1CK, U1TDE2D0, U1TDE3D1, U1TDE4D2, U1TDE5D3, U1TDE6, U1TDE7, U1TXDHS, U1TXLPD, U1TXRYE, U1TXRY, U1TXRYSK, U1TXREQ, U1TXREQH, U1TXSK, U1TXTGE0 +, U1TXTGE1, U1TXTGE2, U1TXTGE3, U1TXUPSE, U1TXUPSX, U1TXVDE, U1TXWVHS, U1USAN, U2DIR, U2END2, U2ERCLP0, U2ERCLP1, U2ERCTRL, U2ERE, U2ERSTHS, U2ERSSHS, U2ERSE, U2FRXMD, U2FTXST, U2RXACHS, U2RXCKE +, U2RXDE, U2RXDHS, U2RPDTE, U2RXSK, U2RXSKC, U2RXSHS, U2RE0D2, U2RE1D2, U2RE2D3, U2RE3D3, U2RXUPSE, U2RXVDE, U2RXVDHS, U2SSTT, U2TDIS, U2TREQ, U2TDE0D0, U2TDE1D1, U2TDE2D2, U2TDE3D3, U2TDE4CK +, U2TDE5D0, U2TDE6D1, U2TDE7D2, U2TXDHS, U2TPDTE, U2TXRYE, U2TXRYH, U2TXRYSK, U2TXREQ, U2TXREQH, U2TXSKC, U2TXTGE0, U2TXTGE1, U2TXTGE2, U2TXTGE3, U2TXUPSE, U2TXUPSX, U2TXVDE, U2TXWVHS, U2USAN, U3DIR +, U3END3, U3ERCLP0, U3ERCLP1, U3ERCTRL, U3ERE, U3ERSTHS, U3ERSSHS, U3ERSE, U3FRXMD, U3FTXST, U3RXATHS, U3RXCKE, U3RXDE, U3RXDHS, U3RPDTE, U3RXSK, U3RXSKC, U3RXSHS, U3RE0CK, U3RE1CK, U3RE2 +, U3RE3, U3RXUPSE, U3RXVDE, U3RXVDHS, U3SSTT, U3TDISD2, U3TREQD2, U3TDE0D3, U3TDE1D0, U3TDE2D1, U3TDE3D2, U3TDE4D3, U3TDE5CK, U3TDE6, U3TDE7, U3TXDHS, U3TXLPDT, U3TXRY, U3TXRYHS, U3TXRYSK, U3TXREQ +, U3TXREQH, U3TXSKC, U3TXTGE0, U3TXTGE1, U3TXTGE2, U3TXTGE3, U3TXULPS, U3TXUPSX, U3TXVD3, U3TXWVHS, U3USAN, UCENCK, UCRXCKAT, UCRXUCKN, UCSSTT, UCTXREQH, UCTXUPSC, UCTXUPSX, UCUSAN, LTSTEN, LTSTLANE +, URWDCKHS, UTRNREQ, UTWDCKHS, UCRXWCHS, CLKLBACT); parameter GSR = "ENABLED"; parameter AUTO_PD_EN = "POWERED_UP"; parameter CFG_NUM_LANES = "ONE_LANE"; @@ -935,7 +956,8 @@ module DPHY (...); output CLKLBACT; endmodule -module DPSC512K (...); +module DPSC512K(DIA, DIB, ADA, ADB, CLK, CEA, CEB, WEA, WEB, CSA, CSB, RSTA, RSTB, BENA_N, BENB_N, CEOUTA, CEOUTB, DOA, DOB, ERRDECA, ERRDECB +); parameter OUTREG_A = "NO_REG"; parameter OUTREG_B = "NO_REG"; parameter GSR = "ENABLED"; @@ -1093,7 +1115,8 @@ module DPSC512K (...); output [1:0] ERRDECB; endmodule -module DQSBUF (...); +module DQSBUF(BTDETECT, BURSTDETECT, DATAVALID, DQSI, DQSW, DQSWRD, PAUSE, RDCLKSEL, RDDIR, RDLOADN, RDPNTR, READ, READCOUT, READMOVE, RST, SCLK, SELCLK, DQSR90, DQSW270, WRCOUT, WRDIR +, WRLOAD_N, WRLVCOUT, WRLVDIR, WRLVLOAD_N, WRLVMOVE, WRMOVE, WRPNTR, ECLKIN, RSTSMCNT, DLLCODE); parameter GSR = "ENABLED"; parameter ENABLE_FIFO = "DISABLED"; parameter FORCE_READ = "DISABLED"; @@ -1148,7 +1171,12 @@ module DQSBUF (...); input [8:0] DLLCODE; endmodule -module EBR_CORE (...); +module EBR_CORE(DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, DIA9, DIA10, DIA11, DIA12, DIA13, DIA14, DIA15, DIA16, DIA17, DIB0, DIB1, DIB2 +, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, DIB9, DIB10, DIB11, DIB12, DIB13, DIB14, DIB15, DIB16, DIB17, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5 +, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, ADA13, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 +, ADB13, CLKA, CLKB, WEA, WEB, CEA, CEB, RSTA, RSTB, CSA0, CSA1, CSA2, CSB0, CSB1, CSB2, FULLF, AFULL, EMPTYF, AEMPTY, DOA0, DOA1 +, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOA9, DOA10, DOA11, DOA12, DOA13, DOA14, DOA15, DOA16, DOA17, DOB0, DOB1, DOB2, DOB3, DOB4 +, DOB5, DOB6, DOB7, DOB8, DOB9, DOB10, DOB11, DOB12, DOB13, DOB14, DOB15, DOB16, DOB17, ONEERR, TWOERR); parameter INIT_DATA = "STATIC"; parameter DATA_WIDTH_A = "X36"; parameter DATA_WIDTH_B = "X36"; @@ -1354,7 +1382,8 @@ module EBR_CORE (...); output TWOERR; endmodule -module EBR (...); +module EBR(DIA, DIB, ADA, ADB, CLKA, CLKB, WEA, WEB, CEA, CEB, RSTA, RSTB, CSA, CSB, FULLF, AFULL, EMPTYF, AEMPTY, DOA, DOB, ONEERR +, TWOERR); parameter INIT_DATA = "STATIC"; parameter DATA_WIDTH_A = "X36"; parameter DATA_WIDTH_B = "X36"; @@ -1461,7 +1490,7 @@ module EBR (...); output TWOERR; endmodule -module ECLKDIV (...); +module ECLKDIV(DIVOUT, DIVRST, ECLKIN, SLIP); parameter ECLK_DIV = "DISABLE"; parameter GSR = "ENABLED"; output DIVOUT; @@ -1470,14 +1499,14 @@ module ECLKDIV (...); input SLIP; endmodule -module ECLKSYNC (...); +module ECLKSYNC(ECLKIN, ECLKOUT, STOP); parameter STOP_EN = "DISABLE"; input ECLKIN; output ECLKOUT; input STOP; endmodule -module FBMUX (...); +module FBMUX(ENEXT, FBKCK, LGYRDYN, INTLOCK, WKUPSYNC, FBKCLK); parameter INTFB = "IGNORED"; parameter SEL_FBK = "DIVA"; parameter CLKMUX_FB = "CMUX_CLKOP"; @@ -1490,7 +1519,11 @@ module FBMUX (...); input [15:0] FBKCLK; endmodule -module FIFO16K_MODE (...); +module FIFO16K_MODE(DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, DIA9, DIA10, DIA11, DIA12, DIA13, DIA14, DIA15, DIA16, DIA17, DIB0, DIB1, DIB2 +, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, DIB9, DIB10, DIB11, DIB12, DIB13, DIB14, DIB15, DIB16, DIB17, CKA, CKB, CEA, CEB, CSA0, CSA1 +, CSA2, CSB0, CSB1, CSB2, RSTA, RSTB, DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOA9, DOA10, DOA11, DOA12, DOA13, DOA14 +, DOA15, DOA16, DOA17, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, DOB9, DOB10, DOB11, DOB12, DOB13, DOB14, DOB15, DOB16, DOB17 +, ALMOSTFULL, FULL, ALMOSTEMPTY, EMPTY, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -1596,7 +1629,7 @@ module FIFO16K_MODE (...); output TWOBITERR; endmodule -module FIFO16K (...); +module FIFO16K(DIA, DIB, CKA, CKB, CEA, CEB, CSA, CSB, RSTA, RSTB, DOA, DOB, ALMOSTFULL, FULL, ALMOSTEMPTY, EMPTY, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_A = "X18"; parameter DATA_WIDTH_B = "X18"; parameter OUTREG_A = "BYPASSED"; @@ -1630,7 +1663,7 @@ module FIFO16K (...); output TWOBITERR; endmodule -module HSE (...); +module HSE(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, ASFCLKI, ASFEMPTYO, ASFFULLO, ASFRDI, ASFRESETI, ASFWRI, CFG_CLK, HSE_CLK, HSELRSTN); parameter MCGLBGSRNDIS = "EN"; parameter MCHSEDISABLE = "EN"; parameter MCHSEOTPEN = "DIS"; @@ -1654,7 +1687,8 @@ module HSE (...); input HSELRSTN; endmodule -module I2CFIFO (...); +module I2CFIFO(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, ALTSCLIN, ALTSCLOEN, ALTSCLOUT, ALTSDAIN, ALTSDAOEN, ALTSDAOUT, BUSBUSY, FIFORESET, I2CLSRRSTN, INSLEEP, IRQ, MRDCMPL +, RXFIFOAF, RXFIFOE, RXFIFOF, SCLIN, SCLOE, SCLOEN, SCLOUT, SDAIN, SDAOE, SDAOEN, SDAOUT, SLVADDRMATCH, SLVADDRMATCHSCL, SRDWR, TXFIFOAE, TXFIFOE, TXFIFOF); parameter BRNBASEDELAY = "0b0000"; parameter CR1CKDIS = "EN"; parameter CR1FIFOMODE = "REG"; @@ -1733,7 +1767,7 @@ module I2CFIFO (...); output TXFIFOF; endmodule -module IDDR71 (...); +module IDDR71(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1749,7 +1783,7 @@ module IDDR71 (...); output Q6; endmodule -module IDDRX1 (...); +module IDDRX1(D, SCLK, RST, Q0, Q1); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1758,7 +1792,7 @@ module IDDRX1 (...); output Q1; endmodule -module IDDRX2DQ (...); +module IDDRX2DQ(D, DQSR90, ECLK, SCLK, RST, RDPNTR0, RDPNTR1, RDPNTR2, WRPNTR0, WRPNTR1, WRPNTR2, Q0, Q1, Q2, Q3); parameter GSR = "ENABLED"; input D; input DQSR90; @@ -1777,7 +1811,7 @@ module IDDRX2DQ (...); output Q3; endmodule -module IDDRX2 (...); +module IDDRX2(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1790,7 +1824,7 @@ module IDDRX2 (...); output Q3; endmodule -module IDDRX4DQ (...); +module IDDRX4DQ(D, DQSR90, ECLK, SCLK, RST, RDPNTR0, RDPNTR1, RDPNTR2, WRPNTR0, WRPNTR1, WRPNTR2, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); parameter GSR = "ENABLED"; input D; input DQSR90; @@ -1813,7 +1847,7 @@ module IDDRX4DQ (...); output Q7; endmodule -module IDDRX4 (...); +module IDDRX4(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1830,7 +1864,7 @@ module IDDRX4 (...); output Q7; endmodule -module IDDRX5 (...); +module IDDRX5(D, SCLK, RST, ECLK, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9); parameter GSR = "ENABLED"; input D; input SCLK; @@ -1849,7 +1883,7 @@ module IDDRX5 (...); output Q9; endmodule -module IFD1P3BX (...); +module IFD1P3BX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1858,7 +1892,7 @@ module IFD1P3BX (...); output Q; endmodule -module IFD1P3DX (...); +module IFD1P3DX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1867,7 +1901,7 @@ module IFD1P3DX (...); output Q; endmodule -module IFD1P3IX (...); +module IFD1P3IX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1876,7 +1910,7 @@ module IFD1P3IX (...); output Q; endmodule -module IFD1P3JX (...); +module IFD1P3JX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -1886,7 +1920,7 @@ module IFD1P3JX (...); endmodule (* keep *) -module JTAG (...); +module JTAG(JCE1, JCE2, JRSTN, JRTI1, JRTI2, JSHIFT, JTDI, JUPDATE, JTDO1, JTDO2, SMCLK, TCK, JTCK, TDI, TDO_OEN, TDO, TMS); parameter MCER1EXIST = "NEXIST"; parameter MCER2EXIST = "NEXIST"; output JCE1; @@ -1908,7 +1942,8 @@ module JTAG (...); input TMS; endmodule -module LRAM (...); +module LRAM(ADA, ADB, BENA_N, BENB_N, CEA, CEB, CLK, CSA, CSB, DIA, DIB, DOA, DOB, DPS, ERRDECA, ERRDECB, OCEA, OCEB, OEA, OEB, RSTA +, RSTB, WEA, WEB, ERRDET, LRAMREADY); parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; @@ -2077,7 +2112,7 @@ module LRAM (...); output LRAMREADY; endmodule -module M18X36 (...); +module M18X36(SFTCTRL, PH36, PL36, SGNED18H, SGNED18L, P72, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X36 = "ENABLED"; parameter MULT36 = "DISABLED"; @@ -2094,7 +2129,7 @@ module M18X36 (...); input ROUNDEN; endmodule -module MULT18 (...); +module MULT18(SFTCTRL, ARHSIGN, BRHSIGN, ARH, BRH, ARL, BRL, PL18, PH18, SIGNED18, P36, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X18 = "ENABLED"; parameter ROUNDHALFUP = "DISABLED"; @@ -2114,7 +2149,7 @@ module MULT18 (...); input ROUNDEN; endmodule -module MULT36 (...); +module MULT36(PH72, PL72, PML72, PMH72); parameter MULT36X36 = "ENABLED"; input [72:0] PH72; input [72:0] PL72; @@ -2122,7 +2157,7 @@ module MULT36 (...); output [71:0] PMH72; endmodule -module MULT9 (...); +module MULT9(A, ASIGNED, BR, AS1, AS2, ASSIGNED1, ASSIGNED2, BRSIGNED, CLK, CEA, RSTA, AO, BO, AOSIGNED, BOSIGNED, AR, ARSIGNED, P18, CEP, RSTP); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter ASIGNED_OPERAND_EN = "DISABLED"; parameter BYPASS_MULT9 = "USED"; @@ -2155,7 +2190,8 @@ module MULT9 (...); input RSTP; endmodule -module MULTADDSUB18X18WIDE (...); +module MULTADDSUB18X18WIDE(A0, B0, A1, B1, C, CLK, CEA0, CEA1, RSTA0, RSTA1, CEB0, CEB1, RSTB0, RSTB1, CEC, RSTC, RSTCTRL, CECTRL, SIGNED, RSTPIPE, CEPIPE +, Z, RSTOUT, CEOUT, LOADC, ADDSUB); parameter REGINPUTAB0 = "REGISTER"; parameter REGINPUTAB1 = "REGISTER"; parameter REGINPUTC = "REGISTER"; @@ -2194,7 +2230,8 @@ module MULTADDSUB18X18WIDE (...); input [1:0] ADDSUB; endmodule -module MULTADDSUB9X9WIDE (...); +module MULTADDSUB9X9WIDE(A0, B0, A1, B1, A2, B2, A3, B3, C, CLK, CEA0A1, CEA2A3, RSTA0A1, RSTA2A3, CEB0B1, CEB2B3, RSTB0B1, RSTB2B3, CEC, RSTC, RSTCTRL +, CECTRL, SIGNED, RSTPIPE, CEPIPE, RSTOUT, CEOUT, LOADC, ADDSUB, Z); parameter REGINPUTAB0 = "REGISTER"; parameter REGINPUTAB1 = "REGISTER"; parameter REGINPUTAB2 = "REGISTER"; @@ -2240,14 +2277,14 @@ module MULTADDSUB9X9WIDE (...); endmodule (* keep *) -module MULTIBOOT (...); +module MULTIBOOT(AUTOREBOOT, MSPIMADDR); parameter MSPIADDR = "0b00000000000000000000000000000000"; parameter SOURCESEL = "DIS"; input AUTOREBOOT; input [31:0] MSPIMADDR; endmodule -module ODDR71 (...); +module ODDR71(D0, D1, D2, D3, D4, D5, D6, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2262,7 +2299,7 @@ module ODDR71 (...); output Q; endmodule -module ODDRX1 (...); +module ODDRX1(D0, D1, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2271,7 +2308,7 @@ module ODDRX1 (...); output Q; endmodule -module ODDRX2DQS (...); +module ODDRX2DQS(D0, D1, D2, D3, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2284,7 +2321,7 @@ module ODDRX2DQS (...); output Q; endmodule -module ODDRX2DQ (...); +module ODDRX2DQ(D0, D1, D2, D3, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2297,7 +2334,7 @@ module ODDRX2DQ (...); output Q; endmodule -module ODDRX2 (...); +module ODDRX2(D0, D1, D2, D3, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2309,7 +2346,7 @@ module ODDRX2 (...); output Q; endmodule -module ODDRX4DQS (...); +module ODDRX4DQS(D0, D1, D2, D3, D4, D5, D6, D7, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2326,7 +2363,7 @@ module ODDRX4DQS (...); output Q; endmodule -module ODDRX4DQ (...); +module ODDRX4DQ(D0, D1, D2, D3, D4, D5, D6, D7, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2343,7 +2380,7 @@ module ODDRX4DQ (...); output Q; endmodule -module ODDRX4 (...); +module ODDRX4(D0, D1, D2, D3, D4, D5, D6, D7, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2359,7 +2396,7 @@ module ODDRX4 (...); output Q; endmodule -module ODDRX5 (...); +module ODDRX5(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, SCLK, RST, ECLK, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2377,7 +2414,7 @@ module ODDRX5 (...); output Q; endmodule -module OFD1P3BX (...); +module OFD1P3BX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2386,7 +2423,7 @@ module OFD1P3BX (...); output Q; endmodule -module OFD1P3DX (...); +module OFD1P3DX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2395,7 +2432,7 @@ module OFD1P3DX (...); output Q; endmodule -module OFD1P3IX (...); +module OFD1P3IX(D, SP, CK, CD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2404,7 +2441,7 @@ module OFD1P3IX (...); output Q; endmodule -module OFD1P3JX (...); +module OFD1P3JX(D, SP, CK, PD, Q); parameter GSR = "ENABLED"; input D; input SP; @@ -2413,7 +2450,7 @@ module OFD1P3JX (...); output Q; endmodule -module OSHX2 (...); +module OSHX2(D0, D1, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2423,7 +2460,7 @@ module OSHX2 (...); output Q; endmodule -module OSHX4 (...); +module OSHX4(D0, D1, D2, D3, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input D0; input D1; @@ -2435,7 +2472,11 @@ module OSHX4 (...); output Q; endmodule -module PCIE (...); +module PCIE(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, ACJNOUT, ACJPOUT, AUXCK, CKUSRI, CKUSRO, ECKIN, ECKIND2, ECKINDO, ERSTN, ERSTND2, ERXCKD2, ERXCKDO +, ERXRSND2, ETXCKD2, ETXCKDO, ETXRSND2, FLR, FLRACK, MINTLEG, MINTO, PERSTN, PMCTRL, PMCTRLEN, PMDPAST, PRMSGSD, PRNOSNP, PRNSNPRE, PRSNOOP, PRSNPRE, PPBDREG, PPBDSEL, REXTCK, REXTRST +, RSTUSRN, UDLLKUP, ULTSDIS, UPLLKUP, UTLLKUP, UCFGADDR, UCFGF, UCFGRDD, UCFGRDE, UCFGRDY, UCFGSERD, UCFGVD, UCFGWRBE, UCFGWRD, UCFGWRDN, USERAUPD, USERTRS, VRXCMDD, VRXCINIT, VRXCNH, VRXCNINF +, VRXCRRE, VRXD, VRXDP, VRXEOP, VRXERR, VRXF, VRXRDY, VRXSEL, VRXSOP, VRXVD, VXCDINIT, VXCDNH, VTXCRRE, VXD, VXDP, VXEOP, VXEOPN, VXRDY, VXSOP, VXVD, TESTOUT +, S0REFCKN, S0REFCKP, S0REFRET, S0REXT, S0RXN, S0RXP, S0TXN, S0TXP, CLKREQI, CLKREQO, CLKREQOE); parameter ENABLE_USER_CFG = "DISABLED"; parameter PWDN_N = "DISABLED"; parameter GSR = "ENABLED"; @@ -3595,7 +3636,12 @@ module PCIE (...); output CLKREQOE; endmodule -module PDP16K_MODE (...); +module PDP16K_MODE(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20 +, DI21, DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35, ADW0, ADW1, ADW2, ADW3, ADW4, ADW5 +, ADW6, ADW7, ADW8, ADW9, ADW10, ADW11, ADW12, ADW13, ADR0, ADR1, ADR2, ADR3, ADR4, ADR5, ADR6, ADR7, ADR8, ADR9, ADR10, ADR11, ADR12 +, ADR13, CLKW, CLKR, CEW, CER, CSW0, CSW1, CSW2, CSR0, CSR1, CSR2, RST, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8 +, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29 +, DO30, DO31, DO32, DO33, DO34, DO35, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -3785,7 +3831,7 @@ module PDP16K_MODE (...); output TWOBITERR; endmodule -module PDP16K (...); +module PDP16K(DI, ADW, ADR, CLKW, CLKR, CEW, CER, CSW, CSR, RST, DO, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -3875,7 +3921,12 @@ module PDP16K (...); output TWOBITERR; endmodule -module PDPSC16K_MODE (...); +module PDPSC16K_MODE(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20 +, DI21, DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35, ADW0, ADW1, ADW2, ADW3, ADW4, ADW5 +, ADW6, ADW7, ADW8, ADW9, ADW10, ADW11, ADW12, ADW13, ADR0, ADR1, ADR2, ADR3, ADR4, ADR5, ADR6, ADR7, ADR8, ADR9, ADR10, ADR11, ADR12 +, ADR13, CLK, CER, CEW, CSW0, CSW1, CSW2, CSR0, CSR1, CSR2, RST, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9 +, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30 +, DO31, DO32, DO33, DO34, DO35, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -4064,7 +4115,7 @@ module PDPSC16K_MODE (...); output TWOBITERR; endmodule -module PDPSC16K (...); +module PDPSC16K(DI, ADW, ADR, CLK, CER, CEW, CSW, CSR, RST, DO, ONEBITERR, TWOBITERR); parameter DATA_WIDTH_W = "X36"; parameter DATA_WIDTH_R = "X36"; parameter OUTREG = "BYPASSED"; @@ -4153,7 +4204,7 @@ module PDPSC16K (...); output TWOBITERR; endmodule -module PDPSC512K (...); +module PDPSC512K(DI, ADW, ADR, CLK, CEW, CER, WE, CSW, CSR, RSTR, BYTEEN_N, DO, ERRDECA, ERRDECB); parameter OUTREG = "NO_REG"; parameter GSR = "ENABLED"; parameter RESETMODE = "SYNC"; @@ -4303,7 +4354,9 @@ module PDPSC512K (...); output [1:0] ERRDECB; endmodule -module PLL (...); +module PLL(INTFBKOP, INTFBKOS, INTFBKOS2, INTFBKOS3, INTFBKOS4, INTFBKOS5, DIR, DIRSEL, LOADREG, DYNROTATE, LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, PLLPOWERDOWN_N, REFCK +, CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, CLKOS5, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, ENCLKOS4, ENCLKOS5, FBKCK, INTLOCK, LEGACY, LEGRDYN, LOCK, PFDDN, PFDUP, PLLRESET, STDBY +, REFMUXCK, REGQA, REGQB, REGQB1, CLKOUTDL, ROTDEL, DIRDEL, ROTDELP1, GRAYTEST, BINTEST, DIRDELP1, GRAYACT, BINACT); parameter BW_CTL_BIAS = "0b0101"; parameter CLKOP_TRIM = "0b0000"; parameter CLKOS_TRIM = "0b0000"; @@ -4478,7 +4531,8 @@ module PLL (...); input [1:0] BINACT; endmodule -module PREADD9 (...); +module PREADD9(B, BSIGNED, C, BRS1, BRS2, BLS1, BLS2, BRSS1, BRSS2, BLSS1, BLSS2, PRCASIN, CLK, RSTB, CEB, RSTCL, CECL, BRSO, BLSO, BRSOSGND, BLSOSGND +, PRCASOUT, BR, BRSIGNED); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter SUBSTRACT_EN = "SUBTRACTION"; parameter CSIGNED = "DISABLED"; @@ -4520,7 +4574,7 @@ module PREADD9 (...); output BRSIGNED; endmodule -module REFMUX (...); +module REFMUX(REFCK, ZRSEL3, REFSEL, REFCLK1, REFCLK2); parameter REFSEL_ATT = "MC1"; parameter SEL1 = "SELECT_REFCLK1"; parameter SEL_REF2 = "REFCLK2_0"; @@ -4532,7 +4586,7 @@ module REFMUX (...); input [7:0] REFCLK2; endmodule -module REG18 (...); +module REG18(PM, PP, CEP, RSTP, CLK); parameter REGBYPS = "REGISTER"; parameter GSR = "ENABLED"; parameter RESET = "SYNC"; @@ -4544,7 +4598,7 @@ module REG18 (...); endmodule (* keep *) -module SEDC (...); +module SEDC(SEDENABLE, SEDCCOF, SEDCENABLE, SEDCMODE, SEDCSTART, SEDCBUSY, SEDCERR, SEDCERRC, SEDCERRCRC, SEDCERRM, SEDCFRMERRLOC, OSCCLKSEDC, RSTSEDC, SEDCDSRERRLOCCIB); parameter SEDCEN = "DIS"; input SEDENABLE; input SEDCCOF; @@ -4562,7 +4616,7 @@ module SEDC (...); output [12:0] SEDCDSRERRLOCCIB; endmodule -module SEIO18 (...); +module SEIO18(PADDO, DOLP, IOPAD, PADDI, INLP, PADDT, INADC); parameter PULLMODE = "DOWN"; parameter MIPI = "DISABLED"; parameter ENADC_IN = "DISABLED"; @@ -4576,7 +4630,7 @@ module SEIO18 (...); output INADC; endmodule -module SEIO33 (...); +module SEIO33(IOPAD, PADDI, PADDO, PADDT, I3CRESEN, I3CWKPU); parameter PULLMODE = "DOWN"; (* iopad_external_pin *) inout IOPAD; @@ -4587,7 +4641,7 @@ module SEIO33 (...); input I3CWKPU; endmodule -module SGMIICDR (...); +module SGMIICDR(LMMICLK, LMMIRESET_N, LMMIREQUEST, LMMIWRRD_N, LMMIOFFSET, LMMIWDATA, LMMIRDATA, LMMIRDATAVALID, LMMIREADY, DCALIRST, DFACQRST, RRST, SPCLK, SRCLK, SRXD, RSTBFBW, RSTBRXF, SGMIIIN, SREFCLK, CDRLOL); parameter GSR = "ENABLED"; parameter DCOITUNE4LSB = "0_PERCENT"; parameter DCOCTLGI = "0_PERCENT"; @@ -4644,7 +4698,9 @@ module SGMIICDR (...); output CDRLOL; endmodule -module SP16K_MODE (...); +module SP16K_MODE(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, AD0, AD1, AD2 +, AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD10, AD11, AD12, AD13, CLK, CE, WE, CS0, CS1, CS2, RST, DO0, DO1, DO2 +, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17); parameter DATA_WIDTH = "X18"; parameter OUTREG = "BYPASSED"; parameter RESETMODE = "SYNC"; @@ -4775,7 +4831,7 @@ module SP16K_MODE (...); output DO17; endmodule -module SP16K (...); +module SP16K(DI, AD, CLK, CE, WE, CS, RST, DO); parameter DATA_WIDTH = "X18"; parameter OUTREG = "BYPASSED"; parameter RESETMODE = "SYNC"; @@ -4857,7 +4913,7 @@ module SP16K (...); output [17:0] DO; endmodule -module SP512K (...); +module SP512K(DI, AD, CLK, CE, WE, CS, RSTOUT, CEOUT, BYTEEN_N, DO, ERRDECA, ERRDECB); parameter OUTREG = "NO_REG"; parameter GSR = "ENABLED"; parameter RESETMODE = "SYNC"; @@ -5005,7 +5061,7 @@ module SP512K (...); output [1:0] ERRDECB; endmodule -module TSHX2DQS (...); +module TSHX2DQS(T0, T1, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5016,7 +5072,7 @@ module TSHX2DQS (...); output Q; endmodule -module TSHX2DQ (...); +module TSHX2DQ(T0, T1, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5027,7 +5083,7 @@ module TSHX2DQ (...); output Q; endmodule -module TSHX4DQS (...); +module TSHX4DQS(T0, T1, T2, T3, DQSW, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5040,7 +5096,7 @@ module TSHX4DQS (...); output Q; endmodule -module TSHX4DQ (...); +module TSHX4DQ(T0, T1, T2, T3, DQSW270, ECLK, SCLK, RST, Q); parameter GSR = "ENABLED"; input T0; input T1; @@ -5054,7 +5110,7 @@ module TSHX4DQ (...); endmodule (* keep *) -module WDT (...); +module WDT(WDTRELOAD, WDT_CLK, WDT_RST); parameter WDTEN = "DIS"; parameter WDTMODE = "SINGLE"; parameter WDTVALUE = "0b000000000000000000"; @@ -5063,7 +5119,7 @@ module WDT (...); input WDT_RST; endmodule -module MIPI (...); +module MIPI(BP, BN, AP, AN, TP, TN, IHS, HSRXEN, HSTXEN, OHS, OLSP, OLSN); parameter MIPI_ID = "0"; (* iopad_external_pin *) inout BP; @@ -5082,7 +5138,8 @@ module MIPI (...); endmodule (* keep *) -module CONFIG_IP_CORE (...); +module CONFIG_IP_CORE(CFGDONECIB, CIBTSALL, FREEZEIOCIB, LASTADDRCIB15, LASTADDRCIB14, LASTADDRCIB13, LASTADDRCIB12, LASTADDRCIB11, LASTADDRCIB10, LASTADDRCIB9, LASTADDRCIB8, LASTADDRCIB7, LASTADDRCIB6, LASTADDRCIB5, LASTADDRCIB4, LASTADDRCIB3, LASTADDRCIB2, LASTADDRCIB1, LASTADDRCIB0, MBISTENABLEN, MBISTRRMATCH +, MBISTTRRAEN); parameter DONEPHASE = "DIS"; parameter DSRFCTRL = "0b00"; parameter ENTSALL = "DIS"; @@ -5135,11 +5192,11 @@ module CONFIG_IP_CORE (...); input MBISTTRRAEN; endmodule -module TSALLA (...); +module TSALLA(TSALL); input TSALL; endmodule -module OSCA (...); +module OSCA(HFOUTEN, HFSDSCEN, HFCLKOUT, LFCLKOUT, HFCLKCFG, HFSDCOUT); parameter HF_CLK_DIV = "1"; parameter HF_SED_SEC_DIV = "1"; parameter HF_OSC_EN = "ENABLED"; @@ -5152,7 +5209,7 @@ module OSCA (...); output HFSDCOUT; endmodule -module OSC (...); +module OSC(HFCLKOUT, HFSDSCEN, LFCLKOUT, HFSDCOUT, HSE_CLK, JTAG_LRST_N, LMMI_CLK, LMMI_CLK_O, LMMI_LRST_N, LMMI_RST, SEDC_CLK, SEDC_LRST_N, SEDC_RST, CFG_CLK, SMCLK_RST, WDT_CLK, WDT_LRST_N, WDT_RST); parameter DTR_EN = "ENABLED"; parameter HF_CLK_DIV = "1"; parameter HF_SED_SEC_DIV = "1"; @@ -5187,7 +5244,22 @@ module OSC (...); output WDT_RST; endmodule -module ACC54_CORE (...); +module ACC54_CORE(SFTCTRL3, SFTCTRL2, SFTCTRL1, SFTCTRL0, DSPIN53, DSPIN52, DSPIN51, DSPIN50, DSPIN49, DSPIN48, DSPIN47, DSPIN46, DSPIN45, DSPIN44, DSPIN43, DSPIN42, DSPIN41, DSPIN40, DSPIN39, DSPIN38, DSPIN37 +, DSPIN36, DSPIN35, DSPIN34, DSPIN33, DSPIN32, DSPIN31, DSPIN30, DSPIN29, DSPIN28, DSPIN27, DSPIN26, DSPIN25, DSPIN24, DSPIN23, DSPIN22, DSPIN21, DSPIN20, DSPIN19, DSPIN18, DSPIN17, DSPIN16 +, DSPIN15, DSPIN14, DSPIN13, DSPIN12, DSPIN11, DSPIN10, DSPIN9, DSPIN8, DSPIN7, DSPIN6, DSPIN5, DSPIN4, DSPIN3, DSPIN2, DSPIN1, DSPIN0, PP71, PP70, PP69, PP68, PP67 +, PP66, PP65, PP64, PP63, PP62, PP61, PP60, PP59, PP58, PP57, PP56, PP55, PP54, PP53, PP52, PP51, PP50, PP49, PP48, PP47, PP46 +, PP45, PP44, PP43, PP42, PP41, PP40, PP39, PP38, PP37, PP36, PP35, PP34, PP33, PP32, PP31, PP30, PP29, PP28, PP27, PP26, PP25 +, PP24, PP23, PP22, PP21, PP20, PP19, PP18, PP17, PP16, PP15, PP14, PP13, PP12, PP11, PP10, PP9, PP8, PP7, PP6, PP5, PP4 +, PP3, PP2, PP1, PP0, CINPUT53, CINPUT52, CINPUT51, CINPUT50, CINPUT49, CINPUT48, CINPUT47, CINPUT46, CINPUT45, CINPUT44, CINPUT43, CINPUT42, CINPUT41, CINPUT40, CINPUT39, CINPUT38, CINPUT37 +, CINPUT36, CINPUT35, CINPUT34, CINPUT33, CINPUT32, CINPUT31, CINPUT30, CINPUT29, CINPUT28, CINPUT27, CINPUT26, CINPUT25, CINPUT24, CINPUT23, CINPUT22, CINPUT21, CINPUT20, CINPUT19, CINPUT18, CINPUT17, CINPUT16 +, CINPUT15, CINPUT14, CINPUT13, CINPUT12, CINPUT11, CINPUT10, CINPUT9, CINPUT8, CINPUT7, CINPUT6, CINPUT5, CINPUT4, CINPUT3, CINPUT2, CINPUT1, CINPUT0, LOAD, M9ADDSUB1, M9ADDSUB0, ADDSUB1, ADDSUB0 +, CIN, CASIN1, CASIN0, CEO, RSTO, CEC, RSTC, CLK, SIGNEDI, SUM135, SUM134, SUM133, SUM132, SUM131, SUM130, SUM129, SUM128, SUM127, SUM126, SUM125, SUM124 +, SUM123, SUM122, SUM121, SUM120, SUM119, SUM118, SUM117, SUM116, SUM115, SUM114, SUM113, SUM112, SUM111, SUM110, SUM19, SUM18, SUM17, SUM16, SUM15, SUM14, SUM13 +, SUM12, SUM11, SUM10, SUM035, SUM034, SUM033, SUM032, SUM031, SUM030, SUM029, SUM028, SUM027, SUM026, SUM025, SUM024, SUM023, SUM022, SUM021, SUM020, SUM019, SUM018 +, SUM017, SUM016, SUM015, SUM014, SUM013, SUM012, SUM011, SUM010, SUM09, SUM08, SUM07, SUM06, SUM05, SUM04, SUM03, SUM02, SUM01, SUM00, DSPOUT53, DSPOUT52, DSPOUT51 +, DSPOUT50, DSPOUT49, DSPOUT48, DSPOUT47, DSPOUT46, DSPOUT45, DSPOUT44, DSPOUT43, DSPOUT42, DSPOUT41, DSPOUT40, DSPOUT39, DSPOUT38, DSPOUT37, DSPOUT36, DSPOUT35, DSPOUT34, DSPOUT33, DSPOUT32, DSPOUT31, DSPOUT30 +, DSPOUT29, DSPOUT28, DSPOUT27, DSPOUT26, DSPOUT25, DSPOUT24, DSPOUT23, DSPOUT22, DSPOUT21, DSPOUT20, DSPOUT19, DSPOUT18, DSPOUT17, DSPOUT16, DSPOUT15, DSPOUT14, DSPOUT13, DSPOUT12, DSPOUT11, DSPOUT10, DSPOUT9 +, DSPOUT8, DSPOUT7, DSPOUT6, DSPOUT5, DSPOUT4, DSPOUT3, DSPOUT2, DSPOUT1, DSPOUT0, CASCOUT1, CASCOUT0, ROUNDEN, CECIN, CECTRL, RSTCIN, RSTCTRL); parameter SIGN = "DISABLED"; parameter M9ADDSUB_CTRL = "ADDITION"; parameter ADDSUB_CTRL = "ADD_ADD_CTRL_54_BIT_ADDER"; @@ -5554,7 +5626,11 @@ module ACC54_CORE (...); input RSTCTRL; endmodule -module ADC_CORE (...); +module ADC_CORE(ADCEN, CAL, CALRDY, CHAEN, CHASEL3, CHASEL2, CHASEL1, CHASEL0, CHBEN, CHBSEL3, CHBSEL2, CHBSEL1, CHBSEL0, CLKDCLK, CLKFAB, COG, COMP1IN, COMP1IP, COMP1OL, COMP2IN, COMP2IP +, COMP2OL, COMP3IN, COMP3IP, COMP3OL, CONVSTOP, DA11, DA10, DA9, DA8, DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0, DB11, DB10, DB9, DB8 +, DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0, DN1, DN0, DP1, DP0, EOC, GPION15, GPION14, GPION13, GPION12, GPION11, GPION10, GPION9, GPION8 +, GPION7, GPION6, GPION5, GPION4, GPION3, GPION2, GPION1, GPION0, GPIOP15, GPIOP14, GPIOP13, GPIOP12, GPIOP11, GPIOP10, GPIOP9, GPIOP8, GPIOP7, GPIOP6, GPIOP5, GPIOP4, GPIOP3 +, GPIOP2, GPIOP1, GPIOP0, RESETN, RSTN, RSVDH, RSVDL, SOC, COMP1O, COMP2O, COMP3O); parameter ADC_ENP = "ENABLED"; parameter CLK_DIV = "2"; parameter CTLCOMPSW1 = "DISABLED"; @@ -5674,7 +5750,18 @@ module ADC_CORE (...); output COMP3O; endmodule -module ALUREG_CORE (...); +module ALUREG_CORE(OPCGLOADCLK, ALUCLK, ALUFLAGC, ALUFLAGV, ALUFLAGZ, ALUFORWARDA, ALUFORWARDB, ALUIREGEN, ALUOREGEN, ALURST, DATAA31, DATAA30, DATAA29, DATAA28, DATAA27, DATAA26, DATAA25, DATAA24, DATAA23, DATAA22, DATAA21 +, DATAA20, DATAA19, DATAA18, DATAA17, DATAA16, DATAA15, DATAA14, DATAA13, DATAA12, DATAA11, DATAA10, DATAA9, DATAA8, DATAA7, DATAA6, DATAA5, DATAA4, DATAA3, DATAA2, DATAA1, DATAA0 +, DATAB31, DATAB30, DATAB29, DATAB28, DATAB27, DATAB26, DATAB25, DATAB24, DATAB23, DATAB22, DATAB21, DATAB20, DATAB19, DATAB18, DATAB17, DATAB16, DATAB15, DATAB14, DATAB13, DATAB12, DATAB11 +, DATAB10, DATAB9, DATAB8, DATAB7, DATAB6, DATAB5, DATAB4, DATAB3, DATAB2, DATAB1, DATAB0, DATAC4, DATAC3, DATAC2, DATAC1, DATAC0, OPC6, OPC5, OPC4, OPC3, OPC2 +, OPC1, OPC0, OPCCUSTOM, RADDRA4, RADDRA3, RADDRA2, RADDRA1, RADDRA0, RADDRB4, RADDRB3, RADDRB2, RADDRB1, RADDRB0, RDATAA31, RDATAA30, RDATAA29, RDATAA28, RDATAA27, RDATAA26, RDATAA25, RDATAA24 +, RDATAA23, RDATAA22, RDATAA21, RDATAA20, RDATAA19, RDATAA18, RDATAA17, RDATAA16, RDATAA15, RDATAA14, RDATAA13, RDATAA12, RDATAA11, RDATAA10, RDATAA9, RDATAA8, RDATAA7, RDATAA6, RDATAA5, RDATAA4, RDATAA3 +, RDATAA2, RDATAA1, RDATAA0, RDATAB31, RDATAB30, RDATAB29, RDATAB28, RDATAB27, RDATAB26, RDATAB25, RDATAB24, RDATAB23, RDATAB22, RDATAB21, RDATAB20, RDATAB19, RDATAB18, RDATAB17, RDATAB16, RDATAB15, RDATAB14 +, RDATAB13, RDATAB12, RDATAB11, RDATAB10, RDATAB9, RDATAB8, RDATAB7, RDATAB6, RDATAB5, RDATAB4, RDATAB3, RDATAB2, RDATAB1, RDATAB0, REGCLK, REGCLKEN, REGRST, RESULT31, RESULT30, RESULT29, RESULT28 +, RESULT27, RESULT26, RESULT25, RESULT24, RESULT23, RESULT22, RESULT21, RESULT20, RESULT19, RESULT18, RESULT17, RESULT16, RESULT15, RESULT14, RESULT13, RESULT12, RESULT11, RESULT10, RESULT9, RESULT8, RESULT7 +, RESULT6, RESULT5, RESULT4, RESULT3, RESULT2, RESULT1, RESULT0, SCANCLK, SCANRST, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0, WDROTATE1, WDROTATE0, WDSIGNEXT, WDSIZE1, WDSIZE0, WDATA31, WDATA30 +, WDATA29, WDATA28, WDATA27, WDATA26, WDATA25, WDATA24, WDATA23, WDATA22, WDATA21, WDATA20, WDATA19, WDATA18, WDATA17, WDATA16, WDATA15, WDATA14, WDATA13, WDATA12, WDATA11, WDATA10, WDATA9 +, WDATA8, WDATA7, WDATA6, WDATA5, WDATA4, WDATA3, WDATA2, WDATA1, WDATA0, WREN); parameter ALURST_ACTIVELOW = "DISABLE"; parameter GSR = "ENABLED"; parameter INREG = "DISABLE"; @@ -5929,7 +6016,8 @@ module ALUREG_CORE (...); input WREN; endmodule -module BNKREF18_CORE (...); +module BNKREF18_CORE(STDBYINR, STDBYDIF, PVTSNKI6, PVTSNKI5, PVTSNKI4, PVTSNKI3, PVTSNKI2, PVTSNKI1, PVTSNKI0, PVTSRCI6, PVTSRCI5, PVTSRCI4, PVTSRCI3, PVTSRCI2, PVTSRCI1, PVTSRCI0, PVTCODE6, PVTCODE5, PVTCODE4, PVTCODE3, PVTCODE2 +, PVTCODE1, PVTCODE0, PVTSEL); parameter BANK = "0b0000"; parameter STANDBY_DIFFIO = "DISABLED"; parameter STANDBY_INR = "DISABLED"; @@ -5959,7 +6047,8 @@ module BNKREF18_CORE (...); input PVTSEL; endmodule -module BNKREF33_CORE (...); +module BNKREF33_CORE(PVTSEL, PVTSNKI6, PVTSNKI5, PVTSNKI4, PVTSNKI3, PVTSNKI2, PVTSNKI1, PVTSNKI0, PVTSRCI6, PVTSRCI5, PVTSRCI4, PVTSRCI3, PVTSRCI2, PVTSRCI1, PVTSRCI0, PVTCODE6, PVTCODE5, PVTCODE4, PVTCODE3, PVTCODE2, PVTCODE1 +, PVTCODE0); parameter BANK = "0b0000"; input PVTSEL; input PVTSNKI6; @@ -5985,7 +6074,7 @@ module BNKREF33_CORE (...); output PVTCODE0; endmodule -module DIFFIO18_CORE (...); +module DIFFIO18_CORE(I, DOLP, B, O, INLP, T, INADC, HSRXEN, HSTXEN); parameter MIPI_ID = "0"; parameter PULLMODE = "DOWN"; parameter ENADC_IN = "DISABLED"; @@ -6003,7 +6092,7 @@ module DIFFIO18_CORE (...); endmodule (* keep *) -module CONFIG_CLKRST_CORE (...); +module CONFIG_CLKRST_CORE(HSE_CLK, JTAG_LRST_N, LMMI_CLK, LMMI_CLK_O, LMMI_LRST_N, LMMI_RST, OSCCLK, SEDC_CLK, SEDC_LRST_N, SEDC_RST, CFG_CLK, SMCLK_RST, WDT_CLK, WDT_LRST_N, WDT_RST); parameter MCJTAGGSRNDIS = "EN"; parameter MCLMMIGSRNDIS = "EN"; parameter MCSEDCGSRNDIS = "EN"; @@ -6027,7 +6116,11 @@ module CONFIG_CLKRST_CORE (...); endmodule (* keep *) -module CONFIG_HSE_CORE (...); +module CONFIG_HSE_CORE(ASFCLKI, ASFEMPTYO, ASFFULLO, ASFRDI, ASFRESETI, ASFWRI, CFG_CLK, HSE_CLK, HSELRSTN, LMMICLK, LMMIOFFSET17, LMMIOFFSET16, LMMIOFFSET15, LMMIOFFSET14, LMMIOFFSET13, LMMIOFFSET12, LMMIOFFSET11, LMMIOFFSET10, LMMIOFFSET9, LMMIOFFSET8, LMMIOFFSET7 +, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA31, LMMIRDATA30, LMMIRDATA29, LMMIRDATA28, LMMIRDATA27, LMMIRDATA26, LMMIRDATA25, LMMIRDATA24, LMMIRDATA23, LMMIRDATA22, LMMIRDATA21, LMMIRDATA20, LMMIRDATA19, LMMIRDATA18 +, LMMIRDATA17, LMMIRDATA16, LMMIRDATA15, LMMIRDATA14, LMMIRDATA13, LMMIRDATA12, LMMIRDATA11, LMMIRDATA10, LMMIRDATA9, LMMIRDATA8, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST +, LMMIRESETN, LMMIWDATA31, LMMIWDATA30, LMMIWDATA29, LMMIWDATA28, LMMIWDATA27, LMMIWDATA26, LMMIWDATA25, LMMIWDATA24, LMMIWDATA23, LMMIWDATA22, LMMIWDATA21, LMMIWDATA20, LMMIWDATA19, LMMIWDATA18, LMMIWDATA17, LMMIWDATA16, LMMIWDATA15, LMMIWDATA14, LMMIWDATA13, LMMIWDATA12 +, LMMIWDATA11, LMMIWDATA10, LMMIWDATA9, LMMIWDATA8, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, OTM); parameter MCGLBGSRNDIS = "EN"; parameter MCHSEDISABLE = "EN"; parameter MCHSEOTPEN = "DIS"; @@ -6132,7 +6225,7 @@ module CONFIG_HSE_CORE (...); endmodule (* keep *) -module CONFIG_JTAG_CORE (...); +module CONFIG_JTAG_CORE(JCE1, JCE2, JRSTN, JRTI1, JRTI2, JSHIFT, JTDI, JUPDATE, JTDO1, JTDO2, SMCLK, TCK, JTCK, TDI, TDO_OEN, TDO, TMS); parameter MCER1EXIST = "NEXIST"; parameter MCER2EXIST = "NEXIST"; output JCE1; @@ -6155,7 +6248,8 @@ module CONFIG_JTAG_CORE (...); endmodule (* keep *) -module CONFIG_LMMI_CORE (...); +module CONFIG_LMMI_CORE(LMMIOFFSET7, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMICLK, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIRESETN, LMMIREQUEST +, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, RSTSMCLK, SMCLK); parameter LMMI_EN = "DIS"; input LMMIOFFSET7; input LMMIOFFSET6; @@ -6192,7 +6286,8 @@ module CONFIG_LMMI_CORE (...); endmodule (* keep *) -module CONFIG_MULTIBOOT_CORE (...); +module CONFIG_MULTIBOOT_CORE(CIBAUTOREBOOT, CIBMSPIMADDR31, CIBMSPIMADDR30, CIBMSPIMADDR29, CIBMSPIMADDR28, CIBMSPIMADDR27, CIBMSPIMADDR26, CIBMSPIMADDR25, CIBMSPIMADDR24, CIBMSPIMADDR23, CIBMSPIMADDR22, CIBMSPIMADDR21, CIBMSPIMADDR20, CIBMSPIMADDR19, CIBMSPIMADDR18, CIBMSPIMADDR17, CIBMSPIMADDR16, CIBMSPIMADDR15, CIBMSPIMADDR14, CIBMSPIMADDR13, CIBMSPIMADDR12 +, CIBMSPIMADDR11, CIBMSPIMADDR10, CIBMSPIMADDR9, CIBMSPIMADDR8, CIBMSPIMADDR7, CIBMSPIMADDR6, CIBMSPIMADDR5, CIBMSPIMADDR4, CIBMSPIMADDR3, CIBMSPIMADDR2, CIBMSPIMADDR1, CIBMSPIMADDR0); parameter MSPIADDR = "0b00000000000000000000000000000000"; parameter SOURCESEL = "DIS"; input CIBAUTOREBOOT; @@ -6231,7 +6326,8 @@ module CONFIG_MULTIBOOT_CORE (...); endmodule (* keep *) -module CONFIG_SEDC_CORE (...); +module CONFIG_SEDC_CORE(CIBSED1ENABLE, CIBSEDCCOF, CIBSEDCENABLE, CIBSEDCMODE, CIBSEDCSTART, OSCCLKSEDC, RSTSEDC, SEDCBUSYCIB, SEDCDSRERRLOCCIB12, SEDCDSRERRLOCCIB11, SEDCDSRERRLOCCIB10, SEDCDSRERRLOCCIB9, SEDCDSRERRLOCCIB8, SEDCDSRERRLOCCIB7, SEDCDSRERRLOCCIB6, SEDCDSRERRLOCCIB5, SEDCDSRERRLOCCIB4, SEDCDSRERRLOCCIB3, SEDCDSRERRLOCCIB2, SEDCDSRERRLOCCIB1, SEDCDSRERRLOCCIB0 +, SEDCERR1CIB, SEDCERRCCIB, SEDCERRCRCCIB, SEDCERRMCIB, SEDCFRMERRLOCCIB15, SEDCFRMERRLOCCIB14, SEDCFRMERRLOCCIB13, SEDCFRMERRLOCCIB12, SEDCFRMERRLOCCIB11, SEDCFRMERRLOCCIB10, SEDCFRMERRLOCCIB9, SEDCFRMERRLOCCIB8, SEDCFRMERRLOCCIB7, SEDCFRMERRLOCCIB6, SEDCFRMERRLOCCIB5, SEDCFRMERRLOCCIB4, SEDCFRMERRLOCCIB3, SEDCFRMERRLOCCIB2, SEDCFRMERRLOCCIB1, SEDCFRMERRLOCCIB0); parameter SEDCEN = "DIS"; input CIBSED1ENABLE; input CIBSEDCCOF; @@ -6277,7 +6373,7 @@ module CONFIG_SEDC_CORE (...); endmodule (* keep *) -module CONFIG_WDT_CORE (...); +module CONFIG_WDT_CORE(CIBWDTRELOAD, WDT_CLK, WDT_RST); parameter WDTEN = "DIS"; parameter WDTMODE = "SINGLE"; parameter WDTVALUE = "0b000000000000000000"; @@ -6286,7 +6382,8 @@ module CONFIG_WDT_CORE (...); input WDT_RST; endmodule -module DDRDLL_CORE (...); +module DDRDLL_CORE(CODE8, CODE7, CODE6, CODE5, CODE4, CODE3, CODE2, CODE1, CODE0, FREEZE, LOCK, CLKIN, RST, DCNTL8, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1 +, DCNTL0, UDDCNTL_N); parameter GSR = "ENABLED"; parameter ENA_ROUNDOFF = "ENABLED"; parameter FORCE_MAX_DELAY = "CODE_OR_LOCK_FROM_DLL_LOOP"; @@ -6315,7 +6412,7 @@ module DDRDLL_CORE (...); input UDDCNTL_N; endmodule -module DLLDEL_CORE (...); +module DLLDEL_CORE(CLKIN, CLKOUT, CODE8, CODE7, CODE6, CODE5, CODE4, CODE3, CODE2, CODE1, CODE0, COUT, DIR, LOAD_N, MOVE); parameter ADJUST = "0"; parameter DEL_ADJUST = "PLUS"; parameter ENABLE = "DISABLED"; @@ -6336,7 +6433,37 @@ module DLLDEL_CORE (...); input MOVE; endmodule -module DPHY_CORE (...); +module DPHY_CORE(BITCKEXT, CKN, CKP, CLKREF, D0ACTIVE1, D0ACTIVE0, D0BYTCNT9, D0BYTCNT8, D0BYTCNT7, D0BYTCNT6, D0BYTCNT5, D0BYTCNT4, D0BYTCNT3, D0BYTCNT2, D0BYTCNT1, D0BYTCNT0, D0ERRCNT9, D0ERRCNT8, D0ERRCNT7, D0ERRCNT6, D0ERRCNT5 +, D0ERRCNT4, D0ERRCNT3, D0ERRCNT2, D0ERRCNT1, D0ERRCNT0, D0PASS1, D0PASS0, D0VALID1, D0VALID0, D1ACTIVE1, D1ACTIVE0, D1BYTCNT9, D1BYTCNT8, D1BYTCNT7, D1BYTCNT6, D1BYTCNT5, D1BYTCNT4, D1BYTCNT3, D1BYTCNT2, D1BYTCNT1, D1BYTCNT0 +, D1ERRCNT9, D1ERRCNT8, D1ERRCNT7, D1ERRCNT6, D1ERRCNT5, D1ERRCNT4, D1ERRCNT3, D1ERRCNT2, D1ERRCNT1, D1ERRCNT0, D1PASS1, D1PASS0, D1VALID1, D1VALID0, D2ACTIVE1, D2ACTIVE0, D2BYTCNT9, D2BYTCNT8, D2BYTCNT7, D2BYTCNT6, D2BYTCNT5 +, D2BYTCNT4, D2BYTCNT3, D2BYTCNT2, D2BYTCNT1, D2BYTCNT0, D2ERRCNT9, D2ERRCNT8, D2ERRCNT7, D2ERRCNT6, D2ERRCNT5, D2ERRCNT4, D2ERRCNT3, D2ERRCNT2, D2ERRCNT1, D2ERRCNT0, D2PASS1, D2PASS0, D2VALID1, D2VALID0, D3ACTIVE1, D3ACTIVE0 +, D3BYTCNT9, D3BYTCNT8, D3BYTCNT7, D3BYTCNT6, D3BYTCNT5, D3BYTCNT4, D3BYTCNT3, D3BYTCNT2, D3BYTCNT1, D3BYTCNT0, D3ERRCNT9, D3ERRCNT8, D3ERRCNT7, D3ERRCNT6, D3ERRCNT5, D3ERRCNT4, D3ERRCNT3, D3ERRCNT2, D3ERRCNT1, D3ERRCNT0, D3PASS1 +, D3PASS0, D3VALID1, D3VALID0, DCTSTOUT9, DCTSTOUT8, DCTSTOUT7, DCTSTOUT6, DCTSTOUT5, DCTSTOUT4, DCTSTOUT3, DCTSTOUT2, DCTSTOUT1, DCTSTOUT0, DN0, DN1, DN2, DN3, DP0, DP1, DP2, DP3 +, LOCK, PDDPHY, PDPLL, SCCLKIN, SCRSTNIN, UDIR, UED0THEN, UERCLP0, UERCLP1, UERCTRL, UERE, UERSTHS, UERSSHS, UERSE, UFRXMODE, UTXMDTX, URXACTHS, URXCKE, URXCKINE, URXDE7, URXDE6 +, URXDE5, URXDE4, URXDE3, URXDE2, URXDE1, URXDE0, URXDHS15, URXDHS14, URXDHS13, URXDHS12, URXDHS11, URXDHS10, URXDHS9, URXDHS8, URXDHS7, URXDHS6, URXDHS5, URXDHS4, URXDHS3, URXDHS2, URXDHS1 +, URXDHS0, URXLPDTE, URXSKCHS, URXDRX, URXSHS3, URXSHS2, URXSHS1, URXSHS0, URE0D3DP, URE1D3DN, URE2CKDP, URE3CKDN, URXULPSE, URXVDE, URXVDHS3, URXVDHS2, URXVDHS1, URXVDHS0, USSTT, UTDIS, UTXCKE +, UDE0D0TN, UDE1D1TN, UDE2D2TN, UDE3D3TN, UDE4CKTN, UDE5D0RN, UDE6D1RN, UDE7D2RN, UTXDHS31, UTXDHS30, UTXDHS29, UTXDHS28, UTXDHS27, UTXDHS26, UTXDHS25, UTXDHS24, UTXDHS23, UTXDHS22, UTXDHS21, UTXDHS20, UTXDHS19 +, UTXDHS18, UTXDHS17, UTXDHS16, UTXDHS15, UTXDHS14, UTXDHS13, UTXDHS12, UTXDHS11, UTXDHS10, UTXDHS9, UTXDHS8, UTXDHS7, UTXDHS6, UTXDHS5, UTXDHS4, UTXDHS3, UTXDHS2, UTXDHS1, UTXDHS0, UTXENER, UTXRRS +, UTXRYP, UTXRYSK, UTXRD0EN, UTRD0SEN, UTXSKD0N, UTXTGE0, UTXTGE1, UTXTGE2, UTXTGE3, UTXULPSE, UTXUPSEX, UTXVDE, UTXWVDHS3, UTXWVDHS2, UTXWVDHS1, UTXWVDHS0, UUSAN, U1DIR, U1ENTHEN, U1ERCLP0, U1ERCLP1 +, U1ERCTRL, U1ERE, U1ERSTHS, U1ERSSHS, U1ERSE, U1FRXMD, U1FTXST, U1RXATHS, U1RXCKE, U1RXDE7, U1RXDE6, U1RXDE5, U1RXDE4, U1RXDE3, U1RXDE2, U1RXDE1, U1RXDE0, U1RXDHS15, U1RXDHS14, U1RXDHS13, U1RXDHS12 +, U1RXDHS11, U1RXDHS10, U1RXDHS9, U1RXDHS8, U1RXDHS7, U1RXDHS6, U1RXDHS5, U1RXDHS4, U1RXDHS3, U1RXDHS2, U1RXDHS1, U1RXDHS0, U1RXDTE, U1RXSKS, U1RXSK, U1RXSHS3, U1RXSHS2, U1RXSHS1, U1RXSHS0, U1RE0D, U1RE1CN +, U1RE2D, U1RE3N, U1RXUPSE, U1RXVDE, U1RXVDHS3, U1RXVDHS2, U1RXVDHS1, U1RXVDHS0, U1SSTT, U1TDIS, U1TREQ, U1TDE0D3, U1TDE1CK, U1TDE2D0, U1TDE3D1, U1TDE4D2, U1TDE5D3, U1TDE6, U1TDE7, U1TXDHS31, U1TXDHS30 +, U1TXDHS29, U1TXDHS28, U1TXDHS27, U1TXDHS26, U1TXDHS25, U1TXDHS24, U1TXDHS23, U1TXDHS22, U1TXDHS21, U1TXDHS20, U1TXDHS19, U1TXDHS18, U1TXDHS17, U1TXDHS16, U1TXDHS15, U1TXDHS14, U1TXDHS13, U1TXDHS12, U1TXDHS11, U1TXDHS10, U1TXDHS9 +, U1TXDHS8, U1TXDHS7, U1TXDHS6, U1TXDHS5, U1TXDHS4, U1TXDHS3, U1TXDHS2, U1TXDHS1, U1TXDHS0, U1TXLPD, U1TXRYE, U1TXRY, U1TXRYSK, U1TXREQ, U1TXREQH, U1TXSK, U1TXTGE0, U1TXTGE1, U1TXTGE2, U1TXTGE3, U1TXUPSE +, U1TXUPSX, U1TXVDE, U1TXWVHS3, U1TXWVHS2, U1TXWVHS1, U1TXWVHS0, U1USAN, U2DIR, U2END2, U2ERCLP0, U2ERCLP1, U2ERCTRL, U2ERE, U2ERSTHS, U2ERSSHS, U2ERSE, U2FRXMD, U2FTXST, U2RXACHS, U2RXCKE, U2RXDE7 +, U2RXDE6, U2RXDE5, U2RXDE4, U2RXDE3, U2RXDE2, U2RXDE1, U2RXDE0, U2RXDHS15, U2RXDHS14, U2RXDHS13, U2RXDHS12, U2RXDHS11, U2RXDHS10, U2RXDHS9, U2RXDHS8, U2RXDHS7, U2RXDHS6, U2RXDHS5, U2RXDHS4, U2RXDHS3, U2RXDHS2 +, U2RXDHS1, U2RXDHS0, U2RPDTE, U2RXSK, U2RXSKC, U2RXSHS3, U2RXSHS2, U2RXSHS1, U2RXSHS0, U2RE0D2, U2RE1D2, U2RE2D3, U2RE3D3, U2RXUPSE, U2RXVDE, U2RXVDHS3, U2RXVDHS2, U2RXVDHS1, U2RXVDHS0, U2SSTT, U2TDIS +, U2TREQ, U2TDE0D0, U2TDE1D1, U2TDE2D2, U2TDE3D3, U2TDE4CK, U2TDE5D0, U2TDE6D1, U2TDE7D2, U2TXDHS31, U2TXDHS30, U2TXDHS29, U2TXDHS28, U2TXDHS27, U2TXDHS26, U2TXDHS25, U2TXDHS24, U2TXDHS23, U2TXDHS22, U2TXDHS21, U2TXDHS20 +, U2TXDHS19, U2TXDHS18, U2TXDHS17, U2TXDHS16, U2TXDHS15, U2TXDHS14, U2TXDHS13, U2TXDHS12, U2TXDHS11, U2TXDHS10, U2TXDHS9, U2TXDHS8, U2TXDHS7, U2TXDHS6, U2TXDHS5, U2TXDHS4, U2TXDHS3, U2TXDHS2, U2TXDHS1, U2TXDHS0, U2TPDTE +, U2TXRYE, U2TXRYH, U2TXRYSK, U2TXREQ, U2TXREQH, U2TXSKC, U2TXTGE0, U2TXTGE1, U2TXTGE2, U2TXTGE3, U2TXUPSE, U2TXUPSX, U2TXVDE, U2TXWVHS3, U2TXWVHS2, U2TXWVHS1, U2TXWVHS0, U2USAN, U3DIR, U3END3, U3ERCLP0 +, U3ERCLP1, U3ERCTRL, U3ERE, U3ERSTHS, U3ERSSHS, U3ERSE, U3FRXMD, U3FTXST, U3RXATHS, U3RXCKE, U3RXDE7, U3RXDE6, U3RXDE5, U3RXDE4, U3RXDE3, U3RXDE2, U3RXDE1, U3RXDE0, U3RXDHS15, U3RXDHS14, U3RXDHS13 +, U3RXDHS12, U3RXDHS11, U3RXDHS10, U3RXDHS9, U3RXDHS8, U3RXDHS7, U3RXDHS6, U3RXDHS5, U3RXDHS4, U3RXDHS3, U3RXDHS2, U3RXDHS1, U3RXDHS0, U3RPDTE, U3RXSK, U3RXSKC, U3RXSHS3, U3RXSHS2, U3RXSHS1, U3RXSHS0, U3RE0CK +, U3RE1CK, U3RE2, U3RE3, U3RXUPSE, U3RXVDE, U3RXVDHS3, U3RXVDHS2, U3RXVDHS1, U3RXVDHS0, U3SSTT, U3TDISD2, U3TREQD2, U3TDE0D3, U3TDE1D0, U3TDE2D1, U3TDE3D2, U3TDE4D3, U3TDE5CK, U3TDE6, U3TDE7, U3TXDHS31 +, U3TXDHS30, U3TXDHS29, U3TXDHS28, U3TXDHS27, U3TXDHS26, U3TXDHS25, U3TXDHS24, U3TXDHS23, U3TXDHS22, U3TXDHS21, U3TXDHS20, U3TXDHS19, U3TXDHS18, U3TXDHS17, U3TXDHS16, U3TXDHS15, U3TXDHS14, U3TXDHS13, U3TXDHS12, U3TXDHS11, U3TXDHS10 +, U3TXDHS9, U3TXDHS8, U3TXDHS7, U3TXDHS6, U3TXDHS5, U3TXDHS4, U3TXDHS3, U3TXDHS2, U3TXDHS1, U3TXDHS0, U3TXLPDT, U3TXRY, U3TXRYHS, U3TXRYSK, U3TXREQ, U3TXREQH, U3TXSKC, U3TXTGE0, U3TXTGE1, U3TXTGE2, U3TXTGE3 +, U3TXULPS, U3TXUPSX, U3TXVD3, U3TXWVHS3, U3TXWVHS2, U3TXWVHS1, U3TXWVHS0, U3USAN, UCENCK, UCRXCKAT, UCRXUCKN, UCSSTT, UCTXREQH, UCTXUPSC, UCTXUPSX, UCUSAN, SCANCLK, SCANRST, LMMICLK, LMMIOFFSET4, LMMIOFFSET3 +, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, LTSTEN, LTSTLANE1, LTSTLANE0, URWDCKHS, UTRNREQ +, UTWDCKHS, UCRXWCHS, OPCGLDCK, CLKLBACT); parameter GSR = "ENABLED"; parameter AUTO_PD_EN = "POWERED_UP"; parameter CFG_NUM_LANES = "ONE_LANE"; @@ -7014,7 +7141,9 @@ module DPHY_CORE (...); output CLKLBACT; endmodule -module DQSBUF_CORE (...); +module DQSBUF_CORE(BTDETECT, BURSTDETECT, DATAVALID, DQSI, DQSW, DQSWRD, PAUSE, RDCLKSEL3, RDCLKSEL2, RDCLKSEL1, RDCLKSEL0, RDDIR, RDLOADN, RDPNTR2, RDPNTR1, RDPNTR0, READ3, READ2, READ1, READ0, READCOUT +, READMOVE, RST, SCLK, SELCLK, DQSR90, DQSW270, WRCOUT, WRDIR, WRLOAD_N, WRLVCOUT, WRLVDIR, WRLVLOAD_N, WRLVMOVE, WRMOVE, WRPNTR2, WRPNTR1, WRPNTR0, ECLKIN, RSTSMCNT, DLLCODE8, DLLCODE7 +, DLLCODE6, DLLCODE5, DLLCODE4, DLLCODE3, DLLCODE2, DLLCODE1, DLLCODE0); parameter GSR = "ENABLED"; parameter ENABLE_FIFO = "DISABLED"; parameter FORCE_READ = "DISABLED"; @@ -7087,7 +7216,7 @@ module DQSBUF_CORE (...); input DLLCODE0; endmodule -module ECLKDIV_CORE (...); +module ECLKDIV_CORE(DIVOUT, DIVRST, ECLKIN, SLIP, TESTINP3, TESTINP2, TESTINP1, TESTINP0); parameter ECLK_DIV = "DISABLE"; parameter GSR = "ENABLED"; output DIVOUT; @@ -7100,14 +7229,15 @@ module ECLKDIV_CORE (...); input TESTINP0; endmodule -module ECLKSYNC_CORE (...); +module ECLKSYNC_CORE(ECLKIN, ECLKOUT, STOP); parameter STOP_EN = "DISABLE"; input ECLKIN; output ECLKOUT; input STOP; endmodule -module FBMUX_CORE (...); +module FBMUX_CORE(ENEXT, FBKCK, LGYRDYN, INTLOCK, WKUPSYNC, FBKCLK15, FBKCLK14, FBKCLK13, FBKCLK12, FBKCLK11, FBKCLK10, FBKCLK9, FBKCLK8, FBKCLK7, FBKCLK6, FBKCLK5, FBKCLK4, FBKCLK3, FBKCLK2, FBKCLK1, FBKCLK0 +); parameter INTFB = "IGNORED"; parameter SEL_FBK = "DIVA"; parameter CLKMUX_FB = "CMUX_CLKOP"; @@ -7135,7 +7265,9 @@ module FBMUX_CORE (...); input FBKCLK0; endmodule -module I2CFIFO_CORE (...); +module I2CFIFO_CORE(ALTSCLIN, ALTSCLOEN, ALTSCLOUT, ALTSDAIN, ALTSDAOEN, ALTSDAOUT, BUSBUSY, FIFORESET, I2CLSRRSTN, INSLEEP, IRQ, LMMICLK, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5 +, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, MRDCMPL, OPCGLOADCLK, RXFIFOAF +, RXFIFOE, RXFIFOF, SCANCLK, SCANRST, SCLIN, SCLOE, SCLOEN, SCLOUT, SDAIN, SDAOE, SDAOEN, SDAOUT, SLEEPCLKSELN, SLVADDRMATCH, SLVADDRMATCHSCL, SRDWR, TXFIFOAE, TXFIFOE, TXFIFOF); parameter BRNBASEDELAY = "0b0000"; parameter CR1CKDIS = "EN"; parameter CR1FIFOMODE = "REG"; @@ -7237,7 +7369,16 @@ module I2CFIFO_CORE (...); output TXFIFOF; endmodule -module LRAM_CORE (...); +module LRAM_CORE(ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7 +, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, BENA_N3, BENA_N2, BENA_N1, BENA_N0, BENB_N3, BENB_N2, BENB_N1, BENB_N0, CEA, CEB, CLK, CSA, CSB, DIA31 +, DIA30, DIA29, DIA28, DIA27, DIA26, DIA25, DIA24, DIA23, DIA22, DIA21, DIA20, DIA19, DIA18, DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10 +, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, DIB31, DIB30, DIB29, DIB28, DIB27, DIB26, DIB25, DIB24, DIB23, DIB22, DIB21 +, DIB20, DIB19, DIB18, DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0 +, DOA31, DOA30, DOA29, DOA28, DOA27, DOA26, DOA25, DOA24, DOA23, DOA22, DOA21, DOA20, DOA19, DOA18, DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11 +, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB31, DOB30, DOB29, DOB28, DOB27, DOB26, DOB25, DOB24, DOB23, DOB22 +, DOB21, DOB20, DOB19, DOB18, DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1 +, DOB0, DPS, ERRDECA1, ERRDECA0, ERRDECB1, ERRDECB0, IGN, INITN, OCEA, OCEB, OEA, OEB, RSTA, RSTB, STDBYN, TBISTN, WEA, WEB, ERRDET, LRAMREADY, OPCGLOADCLK +, SCANCLK, SCANRST); parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; @@ -7571,7 +7712,12 @@ module LRAM_CORE (...); input SCANRST; endmodule -module MULT18_CORE (...); +module MULT18_CORE(SFTCTRL3, SFTCTRL2, SFTCTRL1, SFTCTRL0, ARHSIGN, BRHSIGN, ARH8, ARH7, ARH6, ARH5, ARH4, ARH3, ARH2, ARH1, ARH0, BRH8, BRH7, BRH6, BRH5, BRH4, BRH3 +, BRH2, BRH1, BRH0, ARL8, ARL7, ARL6, ARL5, ARL4, ARL3, ARL2, ARL1, ARL0, BRL8, BRL7, BRL6, BRL5, BRL4, BRL3, BRL2, BRL1, BRL0 +, PL1819, PL1818, PL1817, PL1816, PL1815, PL1814, PL1813, PL1812, PL1811, PL1810, PL189, PL188, PL187, PL186, PL185, PL184, PL183, PL182, PL181, PL180, PH1819 +, PH1818, PH1817, PH1816, PH1815, PH1814, PH1813, PH1812, PH1811, PH1810, PH189, PH188, PH187, PH186, PH185, PH184, PH183, PH182, PH181, PH180, SIGNED18, P3637 +, P3636, P3635, P3634, P3633, P3632, P3631, P3630, P3629, P3628, P3627, P3626, P3625, P3624, P3623, P3622, P3621, P3620, P3619, P3618, P3617, P3616 +, P3615, P3614, P3613, P3612, P3611, P3610, P369, P368, P367, P366, P365, P364, P363, P362, P361, P360, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X18 = "ENABLED"; parameter ROUNDHALFUP = "DISABLED"; @@ -7701,7 +7847,14 @@ module MULT18_CORE (...); input ROUNDEN; endmodule -module MULT18X36_CORE (...); +module MULT18X36_CORE(SFTCTRL3, SFTCTRL2, SFTCTRL1, SFTCTRL0, PH3637, PH3636, PH3635, PH3634, PH3633, PH3632, PH3631, PH3630, PH3629, PH3628, PH3627, PH3626, PH3625, PH3624, PH3623, PH3622, PH3621 +, PH3620, PH3619, PH3618, PH3617, PH3616, PH3615, PH3614, PH3613, PH3612, PH3611, PH3610, PH369, PH368, PH367, PH366, PH365, PH364, PH363, PH362, PH361, PH360 +, PL3637, PL3636, PL3635, PL3634, PL3633, PL3632, PL3631, PL3630, PL3629, PL3628, PL3627, PL3626, PL3625, PL3624, PL3623, PL3622, PL3621, PL3620, PL3619, PL3618, PL3617 +, PL3616, PL3615, PL3614, PL3613, PL3612, PL3611, PL3610, PL369, PL368, PL367, PL366, PL365, PL364, PL363, PL362, PL361, PL360, SGNED18H, SGNED18L, P7272, P7271 +, P7270, P7269, P7268, P7267, P7266, P7265, P7264, P7263, P7262, P7261, P7260, P7259, P7258, P7257, P7256, P7255, P7254, P7253, P7252, P7251, P7250 +, P7249, P7248, P7247, P7246, P7245, P7244, P7243, P7242, P7241, P7240, P7239, P7238, P7237, P7236, P7235, P7234, P7233, P7232, P7231, P7230, P7229 +, P7228, P7227, P7226, P7225, P7224, P7223, P7222, P7221, P7220, P7219, P7218, P7217, P7216, P7215, P7214, P7213, P7212, P7211, P7210, P729, P728 +, P727, P726, P725, P724, P723, P722, P721, P720, ROUNDEN); parameter SFTEN = "DISABLED"; parameter MULT18X36 = "ENABLED"; parameter MULT36 = "DISABLED"; @@ -7867,7 +8020,20 @@ module MULT18X36_CORE (...); input ROUNDEN; endmodule -module MULT36_CORE (...); +module MULT36_CORE(PH7272, PH7271, PH7270, PH7269, PH7268, PH7267, PH7266, PH7265, PH7264, PH7263, PH7262, PH7261, PH7260, PH7259, PH7258, PH7257, PH7256, PH7255, PH7254, PH7253, PH7252 +, PH7251, PH7250, PH7249, PH7248, PH7247, PH7246, PH7245, PH7244, PH7243, PH7242, PH7241, PH7240, PH7239, PH7238, PH7237, PH7236, PH7235, PH7234, PH7233, PH7232, PH7231 +, PH7230, PH7229, PH7228, PH7227, PH7226, PH7225, PH7224, PH7223, PH7222, PH7221, PH7220, PH7219, PH7218, PH7217, PH7216, PH7215, PH7214, PH7213, PH7212, PH7211, PH7210 +, PH729, PH728, PH727, PH726, PH725, PH724, PH723, PH722, PH721, PH720, PL7272, PL7271, PL7270, PL7269, PL7268, PL7267, PL7266, PL7265, PL7264, PL7263, PL7262 +, PL7261, PL7260, PL7259, PL7258, PL7257, PL7256, PL7255, PL7254, PL7253, PL7252, PL7251, PL7250, PL7249, PL7248, PL7247, PL7246, PL7245, PL7244, PL7243, PL7242, PL7241 +, PL7240, PL7239, PL7238, PL7237, PL7236, PL7235, PL7234, PL7233, PL7232, PL7231, PL7230, PL7229, PL7228, PL7227, PL7226, PL7225, PL7224, PL7223, PL7222, PL7221, PL7220 +, PL7219, PL7218, PL7217, PL7216, PL7215, PL7214, PL7213, PL7212, PL7211, PL7210, PL729, PL728, PL727, PL726, PL725, PL724, PL723, PL722, PL721, PL720, PML7271 +, PML7270, PML7269, PML7268, PML7267, PML7266, PML7265, PML7264, PML7263, PML7262, PML7261, PML7260, PML7259, PML7258, PML7257, PML7256, PML7255, PML7254, PML7253, PML7252, PML7251, PML7250 +, PML7249, PML7248, PML7247, PML7246, PML7245, PML7244, PML7243, PML7242, PML7241, PML7240, PML7239, PML7238, PML7237, PML7236, PML7235, PML7234, PML7233, PML7232, PML7231, PML7230, PML7229 +, PML7228, PML7227, PML7226, PML7225, PML7224, PML7223, PML7222, PML7221, PML7220, PML7219, PML7218, PML7217, PML7216, PML7215, PML7214, PML7213, PML7212, PML7211, PML7210, PML729, PML728 +, PML727, PML726, PML725, PML724, PML723, PML722, PML721, PML720, PMH7271, PMH7270, PMH7269, PMH7268, PMH7267, PMH7266, PMH7265, PMH7264, PMH7263, PMH7262, PMH7261, PMH7260, PMH7259 +, PMH7258, PMH7257, PMH7256, PMH7255, PMH7254, PMH7253, PMH7252, PMH7251, PMH7250, PMH7249, PMH7248, PMH7247, PMH7246, PMH7245, PMH7244, PMH7243, PMH7242, PMH7241, PMH7240, PMH7239, PMH7238 +, PMH7237, PMH7236, PMH7235, PMH7234, PMH7233, PMH7232, PMH7231, PMH7230, PMH7229, PMH7228, PMH7227, PMH7226, PMH7225, PMH7224, PMH7223, PMH7222, PMH7221, PMH7220, PMH7219, PMH7218, PMH7217 +, PMH7216, PMH7215, PMH7214, PMH7213, PMH7212, PMH7211, PMH7210, PMH729, PMH728, PMH727, PMH726, PMH725, PMH724, PMH723, PMH722, PMH721, PMH720); parameter MULT36X36 = "ENABLED"; input PH7272; input PH7271; @@ -8161,7 +8327,11 @@ module MULT36_CORE (...); output PMH720; endmodule -module MULT9_CORE (...); +module MULT9_CORE(A8, A7, A6, A5, A4, A3, A2, A1, A0, ASIGNED, BR8, BR7, BR6, BR5, BR4, BR3, BR2, BR1, BR0, AS18, AS17 +, AS16, AS15, AS14, AS13, AS12, AS11, AS10, AS28, AS27, AS26, AS25, AS24, AS23, AS22, AS21, AS20, ASSIGNED1, ASSIGNED2, BRSIGNED, CLK, CEA +, RSTA, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1, AO0, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1, BO0, AOSIGNED, BOSIGNED +, AR8, AR7, AR6, AR5, AR4, AR3, AR2, AR1, AR0, ARSIGNED, P1819, P1818, P1817, P1816, P1815, P1814, P1813, P1812, P1811, P1810, P189 +, P188, P187, P186, P185, P184, P183, P182, P181, P180, CEP, RSTP); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter ASIGNED_OPERAND_EN = "DISABLED"; parameter BYPASS_MULT9 = "USED"; @@ -8269,7 +8439,8 @@ module MULT9_CORE (...); input RSTP; endmodule -module OSC_CORE (...); +module OSC_CORE(HFCLKOUT, HFOUTEN, HFSDSCEN, HFTRMFAB8, HFTRMFAB7, HFTRMFAB6, HFTRMFAB5, HFTRMFAB4, HFTRMFAB3, HFTRMFAB2, HFTRMFAB1, HFTRMFAB0, LFCLKOUT, LFTRMFAB8, LFTRMFAB7, LFTRMFAB6, LFTRMFAB5, LFTRMFAB4, LFTRMFAB3, LFTRMFAB2, LFTRMFAB1 +, LFTRMFAB0, HFCLKCFG, HFSDCOUT); parameter DTR_EN = "ENABLED"; parameter HF_CLK_DIV = "1"; parameter HF_SED_SEC_DIV = "1"; @@ -8305,7 +8476,28 @@ module OSC_CORE (...); output HFSDCOUT; endmodule -module PCIE_CORE (...); +module PCIE_CORE(ACTACMD, ACTDR11, ACTEN, ACTHIGHZ, ACTMD, ACJNOUT, ACJPOUT, AUXCK, CKUSRI, CKUSRO, ECKIN, ECKIND2, ECKINDO, ERSTN, ERSTND2, ERXCKD2, ERXCKDO, ERXRSND2, ETXCKD2, ETXCKDO, ETXRSND2 +, FLR3, FLR2, FLR1, FLR0, FLRACK3, FLRACK2, FLRACK1, FLRACK0, MINTLEG3, MINTLEG2, MINTLEG1, MINTLEG0, MINTO, PERSTN, PMCTRL4, PMCTRL3, PMCTRL2, PMCTRL1, PMCTRL0, PMCTRLEN, PMDPAST4 +, PMDPAST3, PMDPAST2, PMDPAST1, PMDPAST0, PRMSGSD, PRNOSNP12, PRNOSNP11, PRNOSNP10, PRNOSNP9, PRNOSNP8, PRNOSNP7, PRNOSNP6, PRNOSNP5, PRNOSNP4, PRNOSNP3, PRNOSNP2, PRNOSNP1, PRNOSNP0, PRNSNPRE, PRSNOOP12, PRSNOOP11 +, PRSNOOP10, PRSNOOP9, PRSNOOP8, PRSNOOP7, PRSNOOP6, PRSNOOP5, PRSNOOP4, PRSNOOP3, PRSNOOP2, PRSNOOP1, PRSNOOP0, PRSNPRE, PPBDREG31, PPBDREG30, PPBDREG29, PPBDREG28, PPBDREG27, PPBDREG26, PPBDREG25, PPBDREG24, PPBDREG23 +, PPBDREG22, PPBDREG21, PPBDREG20, PPBDREG19, PPBDREG18, PPBDREG17, PPBDREG16, PPBDREG15, PPBDREG14, PPBDREG13, PPBDREG12, PPBDREG11, PPBDREG10, PPBDREG9, PPBDREG8, PPBDREG7, PPBDREG6, PPBDREG5, PPBDREG4, PPBDREG3, PPBDREG2 +, PPBDREG1, PPBDREG0, PPBDSEL7, PPBDSEL6, PPBDSEL5, PPBDSEL4, PPBDSEL3, PPBDSEL2, PPBDSEL1, PPBDSEL0, REXTCK, REXTRST, RSTUSRN, UDLLKUP, ULTSDIS, UPLLKUP, UTLLKUP, UCFGADDR11, UCFGADDR10, UCFGADDR9, UCFGADDR8 +, UCFGADDR7, UCFGADDR6, UCFGADDR5, UCFGADDR4, UCFGADDR3, UCFGADDR2, UCFGF2, UCFGF1, UCFGF0, UCFGRDD31, UCFGRDD30, UCFGRDD29, UCFGRDD28, UCFGRDD27, UCFGRDD26, UCFGRDD25, UCFGRDD24, UCFGRDD23, UCFGRDD22, UCFGRDD21, UCFGRDD20 +, UCFGRDD19, UCFGRDD18, UCFGRDD17, UCFGRDD16, UCFGRDD15, UCFGRDD14, UCFGRDD13, UCFGRDD12, UCFGRDD11, UCFGRDD10, UCFGRDD9, UCFGRDD8, UCFGRDD7, UCFGRDD6, UCFGRDD5, UCFGRDD4, UCFGRDD3, UCFGRDD2, UCFGRDD1, UCFGRDD0, UCFGRDE +, UCFGRDY, UCFGSERD, UCFGVD, UCFGWRBE3, UCFGWRBE2, UCFGWRBE1, UCFGWRBE0, UCFGWRD31, UCFGWRD30, UCFGWRD29, UCFGWRD28, UCFGWRD27, UCFGWRD26, UCFGWRD25, UCFGWRD24, UCFGWRD23, UCFGWRD22, UCFGWRD21, UCFGWRD20, UCFGWRD19, UCFGWRD18 +, UCFGWRD17, UCFGWRD16, UCFGWRD15, UCFGWRD14, UCFGWRD13, UCFGWRD12, UCFGWRD11, UCFGWRD10, UCFGWRD9, UCFGWRD8, UCFGWRD7, UCFGWRD6, UCFGWRD5, UCFGWRD4, UCFGWRD3, UCFGWRD2, UCFGWRD1, UCFGWRD0, UCFGWRDN, USERAUPD, USERTRS3 +, USERTRS2, USERTRS1, USERTRS0, LMMICLK, LMMIOFFSET16, LMMIOFFSET15, LMMIOFFSET14, LMMIOFFSET13, LMMIOFFSET12, LMMIOFFSET11, LMMIOFFSET10, LMMIOFFSET9, LMMIOFFSET8, LMMIOFFSET7, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIRDATA31, LMMIRDATA30 +, LMMIRDATA29, LMMIRDATA28, LMMIRDATA27, LMMIRDATA26, LMMIRDATA25, LMMIRDATA24, LMMIRDATA23, LMMIRDATA22, LMMIRDATA21, LMMIRDATA20, LMMIRDATA19, LMMIRDATA18, LMMIRDATA17, LMMIRDATA16, LMMIRDATA15, LMMIRDATA14, LMMIRDATA13, LMMIRDATA12, LMMIRDATA11, LMMIRDATA10, LMMIRDATA9 +, LMMIRDATA8, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA31, LMMIWDATA30, LMMIWDATA29, LMMIWDATA28, LMMIWDATA27, LMMIWDATA26, LMMIWDATA25, LMMIWDATA24 +, LMMIWDATA23, LMMIWDATA22, LMMIWDATA21, LMMIWDATA20, LMMIWDATA19, LMMIWDATA18, LMMIWDATA17, LMMIWDATA16, LMMIWDATA15, LMMIWDATA14, LMMIWDATA13, LMMIWDATA12, LMMIWDATA11, LMMIWDATA10, LMMIWDATA9, LMMIWDATA8, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3 +, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, VRXCMDD12, VRXCMDD11, VRXCMDD10, VRXCMDD9, VRXCMDD8, VRXCMDD7, VRXCMDD6, VRXCMDD5, VRXCMDD4, VRXCMDD3, VRXCMDD2, VRXCMDD1, VRXCMDD0, VRXCINIT, VRXCNH11, VRXCNH10, VRXCNH9 +, VRXCNH8, VRXCNH7, VRXCNH6, VRXCNH5, VRXCNH4, VRXCNH3, VRXCNH2, VRXCNH1, VRXCNH0, VRXCNINF, VRXCRRE, VRXD31, VRXD30, VRXD29, VRXD28, VRXD27, VRXD26, VRXD25, VRXD24, VRXD23, VRXD22 +, VRXD21, VRXD20, VRXD19, VRXD18, VRXD17, VRXD16, VRXD15, VRXD14, VRXD13, VRXD12, VRXD11, VRXD10, VRXD9, VRXD8, VRXD7, VRXD6, VRXD5, VRXD4, VRXD3, VRXD2, VRXD1 +, VRXD0, VRXDP3, VRXDP2, VRXDP1, VRXDP0, VRXEOP, VRXERR, VRXF1, VRXF0, VRXRDY, VRXSEL1, VRXSEL0, VRXSOP, VRXVD, VXCDINIT, VXCDNH11, VXCDNH10, VXCDNH9, VXCDNH8, VXCDNH7, VXCDNH6 +, VXCDNH5, VXCDNH4, VXCDNH3, VXCDNH2, VXCDNH1, VXCDNH0, VTXCRRE, VXD31, VXD30, VXD29, VXD28, VXD27, VXD26, VXD25, VXD24, VXD23, VXD22, VXD21, VXD20, VXD19, VXD18 +, VXD17, VXD16, VXD15, VXD14, VXD13, VXD12, VXD11, VXD10, VXD9, VXD8, VXD7, VXD6, VXD5, VXD4, VXD3, VXD2, VXD1, VXD0, VXDP3, VXDP2, VXDP1 +, VXDP0, VXEOP, VXEOPN, VXRDY, VXSOP, VXVD, TESTOUT7, TESTOUT6, TESTOUT5, TESTOUT4, TESTOUT3, TESTOUT2, TESTOUT1, TESTOUT0, REFCLKNA, S0REFCKN, S0REFCKP, S0REFRET, S0REXT, S0RXN, S0RXP +, S0TXN, S0TXP, CLKREQI, CLKREQO, CLKREQOE, SCANCLK, SCANRST, OPCGLDCK, ALTCLKIN); parameter ENABLE_USER_CFG = "DISABLED"; parameter PWDN_N = "DISABLED"; parameter GSR = "ENABLED"; @@ -9820,7 +10012,11 @@ module PCIE_CORE (...); input ALTCLKIN; endmodule -module PLL_CORE (...); +module PLL_CORE(CIBDIR, CIBDSEL2, CIBDSEL1, CIBDSEL0, CIBLDREG, CIBROT, CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, CLKOS5, ENEXT, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, ENCLKOS4, ENCLKOS5, FBKCK, INTFBK5 +, INTFBK4, INTFBK3, INTFBK2, INTFBK1, INTFBK0, INTLOCK, LEGACY, LEGRDYN, LMMICLK, LMMIOFFSET6, LMMIOFFSET5, LMMIOFFSET4, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1, LMMIOFFSET0, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3 +, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIREQUEST, LMMIRESETN, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIWRRDN, LOCK, PFDDN, PFDUP, PLLRESET, REFCK +, STDBY, ZRSEL3, REFMUXCK, PLLPDN, REGQA, REGQB, REGQB1, CLKOUTDL, ROTDEL, DIRDEL, ROTDELP1, GRAYTEST4, GRAYTEST3, GRAYTEST2, GRAYTEST1, GRAYTEST0, BINTEST1, BINTEST0, DIRDELP1, GRAYACT4, GRAYACT3 +, GRAYACT2, GRAYACT1, GRAYACT0, BINACT1, BINACT0, OPCGLDCK, SCANRST, SCANCLK); parameter BW_CTL_BIAS = "0b0101"; parameter CLKOP_TRIM = "0b0000"; parameter CLKOS_TRIM = "0b0000"; @@ -10032,7 +10228,11 @@ module PLL_CORE (...); input SCANCLK; endmodule -module PREADD9_CORE (...); +module PREADD9_CORE(B8, B7, B6, B5, B4, B3, B2, B1, B0, BSIGNED, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, BRS18 +, BRS17, BRS16, BRS15, BRS14, BRS13, BRS12, BRS11, BRS10, BRS28, BRS27, BRS26, BRS25, BRS24, BRS23, BRS22, BRS21, BRS20, BLS18, BLS17, BLS16, BLS15 +, BLS14, BLS13, BLS12, BLS11, BLS10, BLS28, BLS27, BLS26, BLS25, BLS24, BLS23, BLS22, BLS21, BLS20, BRSS1, BRSS2, BLSS1, BLSS2, PRCASIN, CLK, RSTB +, CEB, RSTCL, CECL, BRSO8, BRSO7, BRSO6, BRSO5, BRSO4, BRSO3, BRSO2, BRSO1, BRSO0, BLSO8, BLSO7, BLSO6, BLSO5, BLSO4, BLSO3, BLSO2, BLSO1, BLSO0 +, BRSOSGND, BLSOSGND, PRCASOUT, BR8, BR7, BR6, BR5, BR4, BR3, BR2, BR1, BR0, BRSIGNED); parameter SIGNEDSTATIC_EN = "DISABLED"; parameter SUBSTRACT_EN = "SUBTRACTION"; parameter CSIGNED = "DISABLED"; @@ -10147,7 +10347,7 @@ module PREADD9_CORE (...); output BRSIGNED; endmodule -module REFMUX_CORE (...); +module REFMUX_CORE(REFCK, ZRSEL3, REFSEL, REFCLK17, REFCLK16, REFCLK15, REFCLK14, REFCLK13, REFCLK12, REFCLK11, REFCLK10, REFCLK27, REFCLK26, REFCLK25, REFCLK24, REFCLK23, REFCLK22, REFCLK21, REFCLK20); parameter REFSEL_ATT = "MC1"; parameter SEL1 = "SELECT_REFCLK1"; parameter SEL_REF2 = "REFCLK2_0"; @@ -10173,7 +10373,8 @@ module REFMUX_CORE (...); input REFCLK20; endmodule -module REG18_CORE (...); +module REG18_CORE(PM17, PM16, PM15, PM14, PM13, PM12, PM11, PM10, PM9, PM8, PM7, PM6, PM5, PM4, PM3, PM2, PM1, PM0, PP17, PP16, PP15 +, PP14, PP13, PP12, PP11, PP10, PP9, PP8, PP7, PP6, PP5, PP4, PP3, PP2, PP1, PP0, CEP, RSTP, CLK); parameter REGBYPS = "REGISTER"; parameter GSR = "ENABLED"; parameter RESET = "SYNC"; @@ -10218,7 +10419,7 @@ module REG18_CORE (...); input CLK; endmodule -module SEIO18_CORE (...); +module SEIO18_CORE(I, DOLP, B, O, INLP, T, INADC); parameter MIPI_ID = "0"; parameter PULLMODE = "DOWN"; parameter MIPI = "DISABLED"; @@ -10233,7 +10434,7 @@ module SEIO18_CORE (...); output INADC; endmodule -module SEIO33_CORE (...); +module SEIO33_CORE(B, O, I, T, I3CRESEN, I3CWKPU); parameter PULLMODE = "DOWN"; (* iopad_external_pin *) inout B; @@ -10244,7 +10445,9 @@ module SEIO33_CORE (...); input I3CWKPU; endmodule -module SGMIICDR_CORE (...); +module SGMIICDR_CORE(DCALIRST, DFACQRST, RRST, SPCLK, SRCLK, SRXD9, SRXD8, SRXD7, SRXD6, SRXD5, SRXD4, SRXD3, SRXD2, SRXD1, SRXD0, LMMICLK, LMMIREQUEST, LMMIWRRDN, LMMIOFFSET3, LMMIOFFSET2, LMMIOFFSET1 +, LMMIOFFSET0, LMMIWDATA7, LMMIWDATA6, LMMIWDATA5, LMMIWDATA4, LMMIWDATA3, LMMIWDATA2, LMMIWDATA1, LMMIWDATA0, LMMIRDATA7, LMMIRDATA6, LMMIRDATA5, LMMIRDATA4, LMMIRDATA3, LMMIRDATA2, LMMIRDATA1, LMMIRDATA0, LMMIRDATAVALID, LMMIREADY, LMMIRESETN, RSTBFBW +, RSTBRXF, SGMIIIN, SREFCLK, CDRLOL, OPCGLOADCLK, SCANCLK, SCANRST); parameter GSR = "ENABLED"; parameter DCOITUNE4LSB = "0_PERCENT"; parameter DCOCTLGI = "0_PERCENT"; @@ -10330,20 +10533,20 @@ module SGMIICDR_CORE (...); input SCANRST; endmodule -module GSR (...); +module GSR(GSR_N, CLK); parameter SYNCMODE = "ASYNC"; input GSR_N; input CLK; endmodule -module DCC (...); +module DCC(CE, CLKI, CLKO); parameter DCCEN = "0"; input CE; input CLKI; output CLKO; endmodule -module DCS (...); +module DCS(CLK0, CLK1, DCSOUT, SEL, SELFORCE); parameter DCSMODE = "GND"; input CLK0; input CLK1; @@ -10352,7 +10555,7 @@ module DCS (...); input SELFORCE; endmodule -module GSR_CORE (...); +module GSR_CORE(GSROUT, CLK, GSR_N); parameter GSR = "ENABLED"; parameter GSR_SYNC = "ASYNC"; output GSROUT; @@ -10360,7 +10563,7 @@ module GSR_CORE (...); input GSR_N; endmodule -module PCLKDIV (...); +module PCLKDIV(CLKIN, CLKOUT, LSRPDIV, PCLKDIVTESTINP2, PCLKDIVTESTINP1, PCLKDIVTESTINP0); parameter DIV_PCLKDIV = "X1"; parameter GSR = "ENABLED"; parameter TESTEN_PCLKDIV = "0"; @@ -10374,12 +10577,12 @@ module PCLKDIV (...); endmodule (* keep *) -module PUR (...); +module PUR(PUR); parameter RST_PULSE = "1"; input PUR; endmodule -module PCLKDIVSP (...); +module PCLKDIVSP(CLKIN, CLKOUT, LSRPDIV); parameter DIV_PCLKDIV = "X1"; parameter GSR = "ENABLED"; input CLKIN; diff --git a/techlibs/lattice/cells_bb_xo2.v b/techlibs/lattice/cells_bb_xo2.v index fdf8331b7..ad0b3da14 100644 --- a/techlibs/lattice/cells_bb_xo2.v +++ b/techlibs/lattice/cells_bb_xo2.v @@ -1,18 +1,21 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module DP8KC (...); +module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1 +, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10 +, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6 +, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0); parameter DATA_WIDTH_A = 9; parameter DATA_WIDTH_B = 9; parameter REGMODE_A = "NOREG"; @@ -138,7 +141,10 @@ module DP8KC (...); endmodule (* blackbox *) -module PDPW8KC (...); +module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6 +, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9 +, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; parameter REGMODE = "NOREG"; @@ -255,7 +261,8 @@ module PDPW8KC (...); endmodule (* blackbox *) -module SP8KC (...); +module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1 +, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH = 9; parameter REGMODE = "NOREG"; parameter CSDECODE = "0b000"; @@ -338,7 +345,9 @@ module SP8KC (...); endmodule (* blackbox *) -module FIFO8KB (...); +module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0 +, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10 +, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; parameter REGMODE = "NOREG"; @@ -409,7 +418,7 @@ module FIFO8KB (...); endmodule (* blackbox *) -module CLKDIVC (...); +module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input RST; @@ -420,7 +429,7 @@ module CLKDIVC (...); endmodule (* blackbox *) -module DCMA (...); +module DCMA(CLK0, CLK1, SEL, DCMOUT); input CLK0; input CLK1; input SEL; @@ -428,14 +437,14 @@ module DCMA (...); endmodule (* blackbox *) -module ECLKSYNCA (...); +module ECLKSYNCA(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -443,19 +452,21 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) (* keep *) -module START (...); +module START(STARTCLK); input STARTCLK; endmodule (* blackbox *) -module EHXPLLJ (...); +module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE +, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7 +, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -557,7 +568,7 @@ module EHXPLLJ (...); endmodule (* blackbox *) -module OSCH (...); +module OSCH(STDBY, OSC, SEDSTDBY); parameter NOM_FREQ = "2.08"; input STDBY; output OSC; @@ -565,7 +576,7 @@ module OSCH (...); endmodule (* blackbox *) (* keep *) -module TSALL (...); +module TSALL(TSALL); input TSALL; endmodule diff --git a/techlibs/lattice/cells_bb_xo3.v b/techlibs/lattice/cells_bb_xo3.v index fdf8331b7..ad0b3da14 100644 --- a/techlibs/lattice/cells_bb_xo3.v +++ b/techlibs/lattice/cells_bb_xo3.v @@ -1,18 +1,21 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module DP8KC (...); +module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1 +, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10 +, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6 +, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0); parameter DATA_WIDTH_A = 9; parameter DATA_WIDTH_B = 9; parameter REGMODE_A = "NOREG"; @@ -138,7 +141,10 @@ module DP8KC (...); endmodule (* blackbox *) -module PDPW8KC (...); +module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6 +, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9 +, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; parameter REGMODE = "NOREG"; @@ -255,7 +261,8 @@ module PDPW8KC (...); endmodule (* blackbox *) -module SP8KC (...); +module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1 +, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH = 9; parameter REGMODE = "NOREG"; parameter CSDECODE = "0b000"; @@ -338,7 +345,9 @@ module SP8KC (...); endmodule (* blackbox *) -module FIFO8KB (...); +module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0 +, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10 +, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; parameter REGMODE = "NOREG"; @@ -409,7 +418,7 @@ module FIFO8KB (...); endmodule (* blackbox *) -module CLKDIVC (...); +module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input RST; @@ -420,7 +429,7 @@ module CLKDIVC (...); endmodule (* blackbox *) -module DCMA (...); +module DCMA(CLK0, CLK1, SEL, DCMOUT); input CLK0; input CLK1; input SEL; @@ -428,14 +437,14 @@ module DCMA (...); endmodule (* blackbox *) -module ECLKSYNCA (...); +module ECLKSYNCA(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -443,19 +452,21 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) (* keep *) -module START (...); +module START(STARTCLK); input STARTCLK; endmodule (* blackbox *) -module EHXPLLJ (...); +module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE +, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7 +, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -557,7 +568,7 @@ module EHXPLLJ (...); endmodule (* blackbox *) -module OSCH (...); +module OSCH(STDBY, OSC, SEDSTDBY); parameter NOM_FREQ = "2.08"; input STDBY; output OSC; @@ -565,7 +576,7 @@ module OSCH (...); endmodule (* blackbox *) (* keep *) -module TSALL (...); +module TSALL(TSALL); input TSALL; endmodule diff --git a/techlibs/lattice/cells_bb_xo3d.v b/techlibs/lattice/cells_bb_xo3d.v index 84d7d9601..e6208e6b4 100644 --- a/techlibs/lattice/cells_bb_xo3d.v +++ b/techlibs/lattice/cells_bb_xo3d.v @@ -1,18 +1,21 @@ // Created by cells_xtra.py from Lattice models (* blackbox *) (* keep *) -module GSR (...); +module GSR(GSR); input GSR; endmodule (* blackbox *) (* keep *) -module SGSR (...); +module SGSR(GSR, CLK); input GSR; input CLK; endmodule (* blackbox *) -module DP8KC (...); +module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1 +, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10 +, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6 +, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0); parameter DATA_WIDTH_A = 9; parameter DATA_WIDTH_B = 9; parameter REGMODE_A = "NOREG"; @@ -138,7 +141,10 @@ module DP8KC (...); endmodule (* blackbox *) -module PDPW8KC (...); +module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6 +, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5 +, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9 +, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; parameter REGMODE = "NOREG"; @@ -255,7 +261,8 @@ module PDPW8KC (...); endmodule (* blackbox *) -module SP8KC (...); +module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1 +, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0); parameter DATA_WIDTH = 9; parameter REGMODE = "NOREG"; parameter CSDECODE = "0b000"; @@ -338,7 +345,9 @@ module SP8KC (...); endmodule (* blackbox *) -module FIFO8KB (...); +module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0 +, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10 +, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; parameter REGMODE = "NOREG"; @@ -409,7 +418,7 @@ module FIFO8KB (...); endmodule (* blackbox *) -module CLKDIVC (...); +module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX); parameter GSR = "DISABLED"; parameter DIV = "2.0"; input RST; @@ -420,7 +429,7 @@ module CLKDIVC (...); endmodule (* blackbox *) -module DCMA (...); +module DCMA(CLK0, CLK1, SEL, DCMOUT); input CLK0; input CLK1; input SEL; @@ -428,14 +437,14 @@ module DCMA (...); endmodule (* blackbox *) -module ECLKSYNCA (...); +module ECLKSYNCA(ECLKI, STOP, ECLKO); input ECLKI; input STOP; output ECLKO; endmodule (* blackbox *) -module ECLKBRIDGECS (...); +module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT); input CLK0; input CLK1; input SEL; @@ -443,19 +452,21 @@ module ECLKBRIDGECS (...); endmodule (* blackbox *) -module DCCA (...); +module DCCA(CLKI, CE, CLKO); input CLKI; input CE; output CLKO; endmodule (* blackbox *) (* keep *) -module START (...); +module START(STARTCLK); input STARTCLK; endmodule (* blackbox *) -module EHXPLLJ (...); +module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE +, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7 +, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB); parameter CLKI_DIV = 1; parameter CLKFB_DIV = 1; parameter CLKOP_DIV = 8; @@ -557,7 +568,7 @@ module EHXPLLJ (...); endmodule (* blackbox *) -module OSCJ (...); +module OSCJ(STDBY, OSC, SEDSTDBY, OSCESB); parameter NOM_FREQ = "2.08"; input STDBY; output OSC; @@ -566,7 +577,7 @@ module OSCJ (...); endmodule (* blackbox *) (* keep *) -module TSALL (...); +module TSALL(TSALL); input TSALL; endmodule diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8dc74b16e..e1736b14e 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -1,6 +1,6 @@ // Created by cells_xtra.py from Xilinx models -module RAMB4_S1 (...); +module RAMB4_S1(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -27,7 +27,7 @@ module RAMB4_S1 (...); input RST; endmodule -module RAMB4_S2 (...); +module RAMB4_S2(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -54,7 +54,7 @@ module RAMB4_S2 (...); input RST; endmodule -module RAMB4_S4 (...); +module RAMB4_S4(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -81,7 +81,7 @@ module RAMB4_S4 (...); input RST; endmodule -module RAMB4_S8 (...); +module RAMB4_S8(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -108,7 +108,7 @@ module RAMB4_S8 (...); input RST; endmodule -module RAMB4_S16 (...); +module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST); parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -135,7 +135,7 @@ module RAMB4_S16 (...); input RST; endmodule -module RAMB4_S1_S1 (...); +module RAMB4_S1_S1(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -171,7 +171,7 @@ module RAMB4_S1_S1 (...); input RSTB; endmodule -module RAMB4_S1_S2 (...); +module RAMB4_S1_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -207,7 +207,7 @@ module RAMB4_S1_S2 (...); input RSTB; endmodule -module RAMB4_S1_S4 (...); +module RAMB4_S1_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -243,7 +243,7 @@ module RAMB4_S1_S4 (...); input RSTB; endmodule -module RAMB4_S1_S8 (...); +module RAMB4_S1_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -279,7 +279,7 @@ module RAMB4_S1_S8 (...); input RSTB; endmodule -module RAMB4_S1_S16 (...); +module RAMB4_S1_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -315,7 +315,7 @@ module RAMB4_S1_S16 (...); input RSTB; endmodule -module RAMB4_S2_S2 (...); +module RAMB4_S2_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -351,7 +351,7 @@ module RAMB4_S2_S2 (...); input RSTB; endmodule -module RAMB4_S2_S4 (...); +module RAMB4_S2_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -387,7 +387,7 @@ module RAMB4_S2_S4 (...); input RSTB; endmodule -module RAMB4_S2_S8 (...); +module RAMB4_S2_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -423,7 +423,7 @@ module RAMB4_S2_S8 (...); input RSTB; endmodule -module RAMB4_S2_S16 (...); +module RAMB4_S2_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -459,7 +459,7 @@ module RAMB4_S2_S16 (...); input RSTB; endmodule -module RAMB4_S4_S4 (...); +module RAMB4_S4_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -495,7 +495,7 @@ module RAMB4_S4_S4 (...); input RSTB; endmodule -module RAMB4_S4_S8 (...); +module RAMB4_S4_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -531,7 +531,7 @@ module RAMB4_S4_S8 (...); input RSTB; endmodule -module RAMB4_S4_S16 (...); +module RAMB4_S4_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -567,7 +567,7 @@ module RAMB4_S4_S16 (...); input RSTB; endmodule -module RAMB4_S8_S8 (...); +module RAMB4_S8_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -603,7 +603,7 @@ module RAMB4_S8_S8 (...); input RSTB; endmodule -module RAMB4_S8_S16 (...); +module RAMB4_S8_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -639,7 +639,7 @@ module RAMB4_S8_S16 (...); input RSTB; endmodule -module RAMB4_S16_S16 (...); +module RAMB4_S16_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB); parameter SIM_COLLISION_CHECK = "ALL"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -675,7 +675,7 @@ module RAMB4_S16_S16 (...); input RSTB; endmodule -module RAMB16_S1 (...); +module RAMB16_S1(DO, ADDR, DI, EN, CLK, WE, SSR); parameter [0:0] INIT = 1'h0; parameter [0:0] SRVAL = 1'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -753,7 +753,7 @@ module RAMB16_S1 (...); input SSR; endmodule -module RAMB16_S2 (...); +module RAMB16_S2(DO, ADDR, DI, EN, CLK, WE, SSR); parameter [1:0] INIT = 2'h0; parameter [1:0] SRVAL = 2'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -831,7 +831,7 @@ module RAMB16_S2 (...); input SSR; endmodule -module RAMB16_S4 (...); +module RAMB16_S4(DO, ADDR, DI, EN, CLK, WE, SSR); parameter [3:0] INIT = 4'h0; parameter [3:0] SRVAL = 4'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -909,7 +909,7 @@ module RAMB16_S4 (...); input SSR; endmodule -module RAMB16_S9 (...); +module RAMB16_S9(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); parameter [8:0] INIT = 9'h0; parameter [8:0] SRVAL = 9'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -997,7 +997,7 @@ module RAMB16_S9 (...); input SSR; endmodule -module RAMB16_S18 (...); +module RAMB16_S18(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); parameter [17:0] INIT = 18'h0; parameter [17:0] SRVAL = 18'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -1085,7 +1085,7 @@ module RAMB16_S18 (...); input SSR; endmodule -module RAMB16_S36 (...); +module RAMB16_S36(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); parameter [35:0] INIT = 36'h0; parameter [35:0] SRVAL = 36'h0; parameter WRITE_MODE = "WRITE_FIRST"; @@ -1173,7 +1173,7 @@ module RAMB16_S36 (...); input SSR; endmodule -module RAMB16_S1_S1 (...); +module RAMB16_S1_S1(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [0:0] INIT_B = 1'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1263,7 +1263,7 @@ module RAMB16_S1_S1 (...); input SSRB; endmodule -module RAMB16_S1_S2 (...); +module RAMB16_S1_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [1:0] INIT_B = 2'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1353,7 +1353,7 @@ module RAMB16_S1_S2 (...); input SSRB; endmodule -module RAMB16_S1_S4 (...); +module RAMB16_S1_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [3:0] INIT_B = 4'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1443,7 +1443,7 @@ module RAMB16_S1_S4 (...); input SSRB; endmodule -module RAMB16_S1_S9 (...); +module RAMB16_S1_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [8:0] INIT_B = 9'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1543,7 +1543,7 @@ module RAMB16_S1_S9 (...); input SSRB; endmodule -module RAMB16_S1_S18 (...); +module RAMB16_S1_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [17:0] INIT_B = 18'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1643,7 +1643,7 @@ module RAMB16_S1_S18 (...); input SSRB; endmodule -module RAMB16_S1_S36 (...); +module RAMB16_S1_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [0:0] INIT_A = 1'h0; parameter [35:0] INIT_B = 36'h0; parameter [0:0] SRVAL_A = 1'h0; @@ -1743,7 +1743,7 @@ module RAMB16_S1_S36 (...); input SSRB; endmodule -module RAMB16_S2_S2 (...); +module RAMB16_S2_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [1:0] INIT_B = 2'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -1833,7 +1833,7 @@ module RAMB16_S2_S2 (...); input SSRB; endmodule -module RAMB16_S2_S4 (...); +module RAMB16_S2_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [3:0] INIT_B = 4'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -1923,7 +1923,7 @@ module RAMB16_S2_S4 (...); input SSRB; endmodule -module RAMB16_S2_S9 (...); +module RAMB16_S2_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [8:0] INIT_B = 9'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -2023,7 +2023,7 @@ module RAMB16_S2_S9 (...); input SSRB; endmodule -module RAMB16_S2_S18 (...); +module RAMB16_S2_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [17:0] INIT_B = 18'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -2123,7 +2123,7 @@ module RAMB16_S2_S18 (...); input SSRB; endmodule -module RAMB16_S2_S36 (...); +module RAMB16_S2_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [1:0] INIT_A = 2'h0; parameter [35:0] INIT_B = 36'h0; parameter [1:0] SRVAL_A = 2'h0; @@ -2223,7 +2223,7 @@ module RAMB16_S2_S36 (...); input SSRB; endmodule -module RAMB16_S4_S4 (...); +module RAMB16_S4_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [3:0] INIT_B = 4'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2313,7 +2313,7 @@ module RAMB16_S4_S4 (...); input SSRB; endmodule -module RAMB16_S4_S9 (...); +module RAMB16_S4_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [8:0] INIT_B = 9'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2413,7 +2413,7 @@ module RAMB16_S4_S9 (...); input SSRB; endmodule -module RAMB16_S4_S18 (...); +module RAMB16_S4_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [17:0] INIT_B = 18'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2513,7 +2513,7 @@ module RAMB16_S4_S18 (...); input SSRB; endmodule -module RAMB16_S4_S36 (...); +module RAMB16_S4_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [3:0] INIT_A = 4'h0; parameter [35:0] INIT_B = 36'h0; parameter [3:0] SRVAL_A = 4'h0; @@ -2613,7 +2613,7 @@ module RAMB16_S4_S36 (...); input SSRB; endmodule -module RAMB16_S9_S9 (...); +module RAMB16_S9_S9(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [8:0] INIT_A = 9'h0; parameter [8:0] INIT_B = 9'h0; parameter [8:0] SRVAL_A = 9'h0; @@ -2715,7 +2715,7 @@ module RAMB16_S9_S9 (...); input SSRB; endmodule -module RAMB16_S9_S18 (...); +module RAMB16_S9_S18(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [8:0] INIT_A = 9'h0; parameter [17:0] INIT_B = 18'h0; parameter [8:0] SRVAL_A = 9'h0; @@ -2817,7 +2817,7 @@ module RAMB16_S9_S18 (...); input SSRB; endmodule -module RAMB16_S9_S36 (...); +module RAMB16_S9_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [8:0] INIT_A = 9'h0; parameter [35:0] INIT_B = 36'h0; parameter [8:0] SRVAL_A = 9'h0; @@ -2919,7 +2919,7 @@ module RAMB16_S9_S36 (...); input SSRB; endmodule -module RAMB16_S18_S18 (...); +module RAMB16_S18_S18(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [17:0] INIT_A = 18'h0; parameter [17:0] INIT_B = 18'h0; parameter [17:0] SRVAL_A = 18'h0; @@ -3021,7 +3021,7 @@ module RAMB16_S18_S18 (...); input SSRB; endmodule -module RAMB16_S18_S36 (...); +module RAMB16_S18_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [17:0] INIT_A = 18'h0; parameter [35:0] INIT_B = 36'h0; parameter [17:0] SRVAL_A = 18'h0; @@ -3123,7 +3123,7 @@ module RAMB16_S18_S36 (...); input SSRB; endmodule -module RAMB16_S36_S36 (...); +module RAMB16_S36_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB); parameter [35:0] INIT_A = 36'h0; parameter [35:0] INIT_B = 36'h0; parameter [35:0] SRVAL_A = 36'h0; @@ -3225,7 +3225,7 @@ module RAMB16_S36_S36 (...); input SSRB; endmodule -module RAMB16BWE_S18 (...); +module RAMB16BWE_S18(DO, DOP, CLK, EN, SSR, WE, DI, DIP, ADDR); parameter [17:0] INIT = 18'h0; parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; @@ -3313,7 +3313,7 @@ module RAMB16BWE_S18 (...); input [9:0] ADDR; endmodule -module RAMB16BWE_S36 (...); +module RAMB16BWE_S36(DO, DOP, CLK, EN, SSR, WE, DI, DIP, ADDR); parameter [35:0] INIT = 36'h0; parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; @@ -3401,7 +3401,7 @@ module RAMB16BWE_S36 (...); input [8:0] ADDR; endmodule -module RAMB16BWE_S18_S9 (...); +module RAMB16BWE_S18_S9(DOA, DOB, DOPA, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEB, WEA, DIA, DIB, DIPA, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3503,7 +3503,7 @@ module RAMB16BWE_S18_S9 (...); input [10:0] ADDRB; endmodule -module RAMB16BWE_S18_S18 (...); +module RAMB16BWE_S18_S18(DOA, DOB, DOPA, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEB, WEA, DIA, DIB, DIPA, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3605,7 +3605,7 @@ module RAMB16BWE_S18_S18 (...); input [9:0] ADDRB; endmodule -module RAMB16BWE_S36_S9 (...); +module RAMB16BWE_S36_S9(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3707,7 +3707,7 @@ module RAMB16BWE_S36_S9 (...); input [10:0] ADDRB; endmodule -module RAMB16BWE_S36_S18 (...); +module RAMB16BWE_S36_S18(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3809,7 +3809,7 @@ module RAMB16BWE_S36_S18 (...); input [9:0] ADDRB; endmodule -module RAMB16BWE_S36_S36 (...); +module RAMB16BWE_S36_S36(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB); parameter [255:0] INITP_00 = 256'h0; parameter [255:0] INITP_01 = 256'h0; parameter [255:0] INITP_02 = 256'h0; @@ -3911,7 +3911,7 @@ module RAMB16BWE_S36_S36 (...); input [8:0] ADDRB; endmodule -module RAMB16BWER (...); +module RAMB16BWER(DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB); parameter integer DATA_WIDTH_A = 0; parameter integer DATA_WIDTH_B = 0; parameter integer DOA_REG = 0; @@ -4028,7 +4028,7 @@ module RAMB16BWER (...); input [3:0] WEB; endmodule -module RAMB8BWER (...); +module RAMB8BWER(DOADO, DOBDO, DOPADOP, DOPBDOP, ADDRAWRADDR, ADDRBRDADDR, CLKAWRCLK, CLKBRDCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENAWREN, ENBRDEN, REGCEA, REGCEBREGCE, RSTA, RSTBRST, WEAWEL, WEBWEU); parameter integer DATA_WIDTH_A = 0; parameter integer DATA_WIDTH_B = 0; parameter integer DOA_REG = 0; @@ -4109,7 +4109,7 @@ module RAMB8BWER (...); input [1:0] WEBWEU; endmodule -module FIFO16 (...); +module FIFO16(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; parameter integer DATA_WIDTH = 36; @@ -4135,7 +4135,8 @@ module FIFO16 (...); input WREN; endmodule -module RAMB16 (...); +module RAMB16(CASCADEOUTA, CASCADEOUTB, DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, CASCADEINA, REGCEA, ENB, CLKB, SSRB, CASCADEINB, REGCEB, ADDRA, ADDRB, DIA, DIB, DIPA +, DIPB, WEA, WEB); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4254,7 +4255,7 @@ module RAMB16 (...); input [3:0] WEB; endmodule -module RAMB32_S64_ECC (...); +module RAMB32_S64_ECC(STATUS, DO, RDCLK, RDEN, SSR, WRCLK, WREN, DI, RDADDR, WRADDR); parameter DO_REG = 0; parameter SIM_COLLISION_CHECK = "ALL"; output [1:0] STATUS; @@ -4271,7 +4272,7 @@ module RAMB32_S64_ECC (...); input [8:0] WRADDR; endmodule -module FIFO18 (...); +module FIFO18(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; parameter integer DATA_WIDTH = 4; @@ -4300,7 +4301,7 @@ module FIFO18 (...); input WREN; endmodule -module FIFO18_36 (...); +module FIFO18_36(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; parameter integer DO_REG = 1; @@ -4328,7 +4329,7 @@ module FIFO18_36 (...); input WREN; endmodule -module FIFO36 (...); +module FIFO36(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [12:0] ALMOST_EMPTY_OFFSET = 13'h080; parameter [12:0] ALMOST_FULL_OFFSET = 13'h080; parameter integer DATA_WIDTH = 4; @@ -4357,7 +4358,7 @@ module FIFO36 (...); input WREN; endmodule -module FIFO36_72 (...); +module FIFO36_72(ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; parameter integer DO_REG = 1; @@ -4390,7 +4391,7 @@ module FIFO36_72 (...); input WREN; endmodule -module RAMB18 (...); +module RAMB18(DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, REGCEA, ENB, CLKB, SSRB, REGCEB, ADDRA, ADDRB, DIA, DIB, DIPA, DIPB, WEA, WEB); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4502,7 +4503,8 @@ module RAMB18 (...); input [1:0] WEB; endmodule -module RAMB36 (...); +module RAMB36(CASCADEOUTLATA, CASCADEOUTREGA, CASCADEOUTLATB, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA, ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB, ADDRA +, ADDRB, DIA, DIB, DIPA, DIPB, WEA, WEB); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4696,7 +4698,7 @@ module RAMB36 (...); input [3:0] WEB; endmodule -module RAMB18SDP (...); +module RAMB18SDP(DO, DOP, RDCLK, RDEN, REGCE, SSR, WRCLK, WREN, WRADDR, RDADDR, DI, DIP, WE); parameter integer DO_REG = 0; parameter [35:0] INIT = 36'h0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -4792,7 +4794,7 @@ module RAMB18SDP (...); input [3:0] WE; endmodule -module RAMB36SDP (...); +module RAMB36SDP(DBITERR, SBITERR, DO, DOP, ECCPARITY, RDCLK, RDEN, REGCE, SSR, WRCLK, WREN, WRADDR, RDADDR, DI, DIP, WE); parameter integer DO_REG = 0; parameter EN_ECC_READ = "FALSE"; parameter EN_ECC_SCRUB = "FALSE"; @@ -4966,7 +4968,7 @@ module RAMB36SDP (...); input [7:0] WE; endmodule -module FIFO18E1 (...); +module FIFO18E1(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; parameter integer DATA_WIDTH = 4; @@ -5012,7 +5014,8 @@ module FIFO18E1 (...); input WREN; endmodule -module FIFO36E1 (...); +module FIFO36E1(ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST +, RSTREG, WRCLK, WREN); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; parameter integer DATA_WIDTH = 4; @@ -5065,7 +5068,8 @@ module FIFO36E1 (...); input WREN; endmodule -module FIFO18E2 (...); +module FIFO18E2(CASDOUT, CASDOUTP, CASNXTEMPTY, CASPRVRDEN, DOUT, DOUTP, EMPTY, FULL, PROGEMPTY, PROGFULL, RDCOUNT, RDERR, RDRSTBUSY, WRCOUNT, WRERR, WRRSTBUSY, CASDIN, CASDINP, CASDOMUX, CASDOMUXEN, CASNXTRDEN +, CASOREGIMUX, CASOREGIMUXEN, CASPRVEMPTY, DIN, DINP, RDCLK, RDEN, REGCE, RST, RSTREG, SLEEP, WRCLK, WREN); parameter CASCADE_ORDER = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; parameter FIRST_WORD_FALL_THROUGH = "FALSE"; @@ -5130,7 +5134,8 @@ module FIFO18E2 (...); input WREN; endmodule -module FIFO36E2 (...); +module FIFO36E2(CASDOUT, CASDOUTP, CASNXTEMPTY, CASPRVRDEN, DBITERR, DOUT, DOUTP, ECCPARITY, EMPTY, FULL, PROGEMPTY, PROGFULL, RDCOUNT, RDERR, RDRSTBUSY, SBITERR, WRCOUNT, WRERR, WRRSTBUSY, CASDIN, CASDINP +, CASDOMUX, CASDOMUXEN, CASNXTRDEN, CASOREGIMUX, CASOREGIMUXEN, CASPRVEMPTY, DIN, DINP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, SLEEP, WRCLK, WREN); parameter CASCADE_ORDER = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; parameter EN_ECC_PIPE = "FALSE"; @@ -5203,7 +5208,9 @@ module FIFO36E2 (...); input WREN; endmodule -module RAMB18E2 (...); +module RAMB18E2(CASDOUTA, CASDOUTB, CASDOUTPA, CASDOUTPB, DOUTADOUT, DOUTBDOUT, DOUTPADOUTP, DOUTPBDOUTP, ADDRARDADDR, ADDRBWRADDR, ADDRENA, ADDRENB, CASDIMUXA, CASDIMUXB, CASDINA, CASDINB, CASDINPA, CASDINPB, CASDOMUXA, CASDOMUXB, CASDOMUXEN_A +, CASDOMUXEN_B, CASOREGIMUXA, CASOREGIMUXB, CASOREGIMUXEN_A, CASOREGIMUXEN_B, CLKARDCLK, CLKBWRCLK, DINADIN, DINBDIN, DINPADINP, DINPBDINP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, SLEEP, WEA +, WEBWE); parameter CASCADE_ORDER_A = "NONE"; parameter CASCADE_ORDER_B = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; @@ -5363,7 +5370,9 @@ module RAMB18E2 (...); input [3:0] WEBWE; endmodule -module RAMB36E2 (...); +module RAMB36E2(CASDOUTA, CASDOUTB, CASDOUTPA, CASDOUTPB, CASOUTDBITERR, CASOUTSBITERR, DBITERR, DOUTADOUT, DOUTBDOUT, DOUTPADOUTP, DOUTPBDOUTP, ECCPARITY, RDADDRECC, SBITERR, ADDRARDADDR, ADDRBWRADDR, ADDRENA, ADDRENB, CASDIMUXA, CASDIMUXB, CASDINA +, CASDINB, CASDINPA, CASDINPB, CASDOMUXA, CASDOMUXB, CASDOMUXEN_A, CASDOMUXEN_B, CASINDBITERR, CASINSBITERR, CASOREGIMUXA, CASOREGIMUXB, CASOREGIMUXEN_A, CASOREGIMUXEN_B, CLKARDCLK, CLKBWRCLK, DINADIN, DINBDIN, DINPADINP, DINPBDINP, ECCPIPECE, ENARDEN +, ENBWREN, INJECTDBITERR, INJECTSBITERR, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, SLEEP, WEA, WEBWE); parameter CASCADE_ORDER_A = "NONE"; parameter CASCADE_ORDER_B = "NONE"; parameter CLOCK_DOMAINS = "INDEPENDENT"; @@ -5609,7 +5618,10 @@ module RAMB36E2 (...); input [7:0] WEBWE; endmodule -module URAM288 (...); +module URAM288(CAS_OUT_ADDR_A, CAS_OUT_ADDR_B, CAS_OUT_BWE_A, CAS_OUT_BWE_B, CAS_OUT_DBITERR_A, CAS_OUT_DBITERR_B, CAS_OUT_DIN_A, CAS_OUT_DIN_B, CAS_OUT_DOUT_A, CAS_OUT_DOUT_B, CAS_OUT_EN_A, CAS_OUT_EN_B, CAS_OUT_RDACCESS_A, CAS_OUT_RDACCESS_B, CAS_OUT_RDB_WR_A, CAS_OUT_RDB_WR_B, CAS_OUT_SBITERR_A, CAS_OUT_SBITERR_B, DBITERR_A, DBITERR_B, DOUT_A +, DOUT_B, RDACCESS_A, RDACCESS_B, SBITERR_A, SBITERR_B, ADDR_A, ADDR_B, BWE_A, BWE_B, CAS_IN_ADDR_A, CAS_IN_ADDR_B, CAS_IN_BWE_A, CAS_IN_BWE_B, CAS_IN_DBITERR_A, CAS_IN_DBITERR_B, CAS_IN_DIN_A, CAS_IN_DIN_B, CAS_IN_DOUT_A, CAS_IN_DOUT_B, CAS_IN_EN_A, CAS_IN_EN_B +, CAS_IN_RDACCESS_A, CAS_IN_RDACCESS_B, CAS_IN_RDB_WR_A, CAS_IN_RDB_WR_B, CAS_IN_SBITERR_A, CAS_IN_SBITERR_B, CLK, DIN_A, DIN_B, EN_A, EN_B, INJECT_DBITERR_A, INJECT_DBITERR_B, INJECT_SBITERR_A, INJECT_SBITERR_B, OREG_CE_A, OREG_CE_B, OREG_ECC_CE_A, OREG_ECC_CE_B, RDB_WR_A, RDB_WR_B +, RST_A, RST_B, SLEEP); parameter integer AUTO_SLEEP_LATENCY = 8; parameter integer AVG_CONS_INACTIVE_CYCLES = 10; parameter BWE_MODE_A = "PARITY_INTERLEAVED"; @@ -5724,7 +5736,8 @@ module URAM288 (...); input SLEEP; endmodule -module URAM288_BASE (...); +module URAM288_BASE(DBITERR_A, DBITERR_B, DOUT_A, DOUT_B, SBITERR_A, SBITERR_B, ADDR_A, ADDR_B, BWE_A, BWE_B, CLK, DIN_A, DIN_B, EN_A, EN_B, INJECT_DBITERR_A, INJECT_DBITERR_B, INJECT_SBITERR_A, INJECT_SBITERR_B, OREG_CE_A, OREG_CE_B +, OREG_ECC_CE_A, OREG_ECC_CE_B, RDB_WR_A, RDB_WR_B, RST_A, RST_B, SLEEP); parameter integer AUTO_SLEEP_LATENCY = 8; parameter integer AVG_CONS_INACTIVE_CYCLES = 10; parameter BWE_MODE_A = "PARITY_INTERLEAVED"; @@ -5789,7 +5802,9 @@ module URAM288_BASE (...); input SLEEP; endmodule -module DSP48E (...); +module DSP48E(ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1 +, CEA2, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CEM, CEMULTCARRYIN, CEP, CLK, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTM +, RSTP); parameter SIM_MODE = "SAFE"; parameter integer ACASCREG = 1; parameter integer ALUMODEREG = 1; @@ -5861,7 +5876,9 @@ module DSP48E (...); input RSTP; endmodule -module DSP48E2 (...); +module DSP48E2(ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, XOROUT, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL +, CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CED, CEINMODE, CEM, CEP, CLK, D, INMODE, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN +, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP); parameter integer ACASCREG = 1; parameter integer ADREG = 1; parameter integer ALUMODEREG = 1; @@ -5976,7 +5993,7 @@ module DSP48E2 (...); input RSTP; endmodule -module FDDRCPE (...); +module FDDRCPE(C0, C1, CE, D0, D1, CLR, PRE, Q); parameter INIT = 1'b0; (* clkbuf_sink *) input C0; @@ -5990,7 +6007,7 @@ module FDDRCPE (...); output Q; endmodule -module FDDRRSE (...); +module FDDRRSE(Q, C0, C1, CE, D0, D1, R, S); parameter INIT = 1'b0; output Q; (* clkbuf_sink *) @@ -6004,7 +6021,7 @@ module FDDRRSE (...); input S; endmodule -module IFDDRCPE (...); +module IFDDRCPE(Q0, Q1, C0, C1, CE, CLR, D, PRE); output Q0; output Q1; (* clkbuf_sink *) @@ -6018,7 +6035,7 @@ module IFDDRCPE (...); input PRE; endmodule -module IFDDRRSE (...); +module IFDDRRSE(Q0, Q1, C0, C1, CE, D, R, S); output Q0; output Q1; (* clkbuf_sink *) @@ -6032,7 +6049,7 @@ module IFDDRRSE (...); input S; endmodule -module OFDDRCPE (...); +module OFDDRCPE(Q, C0, C1, CE, CLR, D0, D1, PRE); (* iopad_external_pin *) output Q; (* clkbuf_sink *) @@ -6046,7 +6063,7 @@ module OFDDRCPE (...); input PRE; endmodule -module OFDDRRSE (...); +module OFDDRRSE(Q, C0, C1, CE, D0, D1, R, S); (* iopad_external_pin *) output Q; (* clkbuf_sink *) @@ -6060,7 +6077,7 @@ module OFDDRRSE (...); input S; endmodule -module OFDDRTCPE (...); +module OFDDRTCPE(O, C0, C1, CE, CLR, D0, D1, PRE, T); (* iopad_external_pin *) output O; (* clkbuf_sink *) @@ -6075,7 +6092,7 @@ module OFDDRTCPE (...); input T; endmodule -module OFDDRTRSE (...); +module OFDDRTRSE(O, C0, C1, CE, D0, D1, R, S, T); (* iopad_external_pin *) output O; (* clkbuf_sink *) @@ -6090,7 +6107,7 @@ module OFDDRTRSE (...); input T; endmodule -module IDDR2 (...); +module IDDR2(Q0, Q1, C0, C1, CE, D, R, S); parameter DDR_ALIGNMENT = "NONE"; parameter [0:0] INIT_Q0 = 1'b0; parameter [0:0] INIT_Q1 = 1'b0; @@ -6107,7 +6124,7 @@ module IDDR2 (...); input S; endmodule -module ODDR2 (...); +module ODDR2(Q, C0, C1, CE, D0, D1, R, S); parameter DDR_ALIGNMENT = "NONE"; parameter [0:0] INIT = 1'b0; parameter SRTYPE = "SYNC"; @@ -6123,7 +6140,7 @@ module ODDR2 (...); input S; endmodule -module IDDR (...); +module IDDR(Q1, Q2, C, CE, D, R, S); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; parameter INIT_Q2 = 1'b0; @@ -6144,7 +6161,7 @@ module IDDR (...); input S; endmodule -module IDDR_2CLK (...); +module IDDR_2CLK(Q1, Q2, C, CB, CE, D, R, S); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; parameter INIT_Q2 = 1'b0; @@ -6167,7 +6184,7 @@ module IDDR_2CLK (...); input S; endmodule -module ODDR (...); +module ODDR(Q, C, CE, D1, D2, R, S); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -6190,7 +6207,7 @@ module ODDR (...); endmodule (* keep *) -module IDELAYCTRL (...); +module IDELAYCTRL(RDY, REFCLK, RST); parameter SIM_DEVICE = "7SERIES"; output RDY; (* clkbuf_sink *) @@ -6198,7 +6215,7 @@ module IDELAYCTRL (...); input RST; endmodule -module IDELAY (...); +module IDELAY(O, C, CE, I, INC, RST); parameter IOBDELAY_TYPE = "DEFAULT"; parameter integer IOBDELAY_VALUE = 0; output O; @@ -6210,7 +6227,8 @@ module IDELAY (...); input RST; endmodule -module ISERDES (...); +module ISERDES(O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1 +, SHIFTIN2, SR); parameter BITSLIP_ENABLE = "FALSE"; parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6259,7 +6277,8 @@ module ISERDES (...); input SR; endmodule -module OSERDES (...); +module OSERDES(OQ, SHIFTOUT1, SHIFTOUT2, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4 +, TCE); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6295,7 +6314,7 @@ module OSERDES (...); input TCE; endmodule -module IODELAY (...); +module IODELAY(DATAOUT, C, CE, DATAIN, IDATAIN, INC, ODATAIN, RST, T); parameter DELAY_SRC = "I"; parameter HIGH_PERFORMANCE_MODE = "TRUE"; parameter IDELAY_TYPE = "DEFAULT"; @@ -6315,7 +6334,7 @@ module IODELAY (...); input T; endmodule -module ISERDES_NODELAY (...); +module ISERDES_NODELAY(Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2); parameter BITSLIP_ENABLE = "FALSE"; parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6351,7 +6370,7 @@ module ISERDES_NODELAY (...); input SHIFTIN2; endmodule -module IODELAYE1 (...); +module IODELAYE1(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, DATAIN, IDATAIN, INC, ODATAIN, RST, T); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "I"; parameter HIGH_PERFORMANCE_MODE = "FALSE"; @@ -6377,7 +6396,8 @@ module IODELAYE1 (...); input T; endmodule -module ISERDESE1 (...); +module ISERDESE1(O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, DDLY, DYNCLKDIVSEL, DYNCLKSEL, OCLK, OFB +, RST, SHIFTIN1, SHIFTIN2); parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; parameter DYN_CLKDIV_INV_EN = "FALSE"; @@ -6425,7 +6445,8 @@ module ISERDESE1 (...); input SHIFTIN2; endmodule -module OSERDESE1 (...); +module OSERDESE1(OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ, CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1 +, SHIFTIN2, T1, T2, T3, T4, TCE, WC); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6470,7 +6491,7 @@ module OSERDESE1 (...); input WC; endmodule -module IDELAYE2 (...); +module IDELAYE2(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN, REGRST); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "IDATAIN"; parameter HIGH_PERFORMANCE_MODE = "FALSE"; @@ -6501,7 +6522,7 @@ module IDELAYE2 (...); input REGRST; endmodule -module ODELAYE2 (...); +module ODELAYE2(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN, REGRST); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "ODATAIN"; parameter HIGH_PERFORMANCE_MODE = "FALSE"; @@ -6530,7 +6551,8 @@ module ODELAYE2 (...); input REGRST; endmodule -module ISERDESE2 (...); +module ISERDESE2(O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY, DYNCLKDIVSEL +, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2); parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; parameter DYN_CLKDIV_INV_EN = "FALSE"; @@ -6598,7 +6620,8 @@ module ISERDESE2 (...); input SHIFTIN2; endmodule -module OSERDESE2 (...); +module OSERDESE2(OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1, SHIFTIN2 +, T1, T2, T3, T4, TBYTEIN, TCE); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; parameter integer DATA_WIDTH = 4; @@ -6670,7 +6693,7 @@ module OSERDESE2 (...); endmodule (* keep *) -module PHASER_IN (...); +module PHASER_IN(FINEOVERFLOW, ICLK, ICLKDIV, ISERDESRST, RCLK, COUNTERREADVAL, COUNTERLOADEN, COUNTERREADEN, DIVIDERST, EDGEADV, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, SYNCIN, SYSCLK, RANKSEL, COUNTERLOADVAL); parameter integer CLKOUT_DIV = 4; parameter DQS_BIAS_MODE = "FALSE"; parameter EN_ISERDES_RST = "FALSE"; @@ -6707,7 +6730,8 @@ module PHASER_IN (...); endmodule (* keep *) -module PHASER_IN_PHY (...); +module PHASER_IN_PHY(DQSFOUND, DQSOUTOFRANGE, FINEOVERFLOW, ICLK, ICLKDIV, ISERDESRST, PHASELOCKED, RCLK, WRENABLE, COUNTERREADVAL, BURSTPENDINGPHY, COUNTERLOADEN, COUNTERREADEN, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, RSTDQSFIND, SYNCIN +, SYSCLK, ENCALIBPHY, RANKSELPHY, COUNTERLOADVAL); parameter BURST_MODE = "FALSE"; parameter integer CLKOUT_DIV = 4; parameter [0:0] DQS_AUTO_RECAL = 1'b1; @@ -6752,7 +6776,8 @@ module PHASER_IN_PHY (...); endmodule (* keep *) -module PHASER_OUT (...); +module PHASER_OUT(COARSEOVERFLOW, FINEOVERFLOW, OCLK, OCLKDELAYED, OCLKDIV, OSERDESRST, COUNTERREADVAL, COARSEENABLE, COARSEINC, COUNTERLOADEN, COUNTERREADEN, DIVIDERST, EDGEADV, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, SELFINEOCLKDELAY, SYNCIN +, SYSCLK, COUNTERLOADVAL); parameter integer CLKOUT_DIV = 4; parameter COARSE_BYPASS = "FALSE"; parameter integer COARSE_DELAY = 0; @@ -6794,7 +6819,8 @@ module PHASER_OUT (...); endmodule (* keep *) -module PHASER_OUT_PHY (...); +module PHASER_OUT_PHY(COARSEOVERFLOW, FINEOVERFLOW, OCLK, OCLKDELAYED, OCLKDIV, OSERDESRST, RDENABLE, CTSBUS, DQSBUS, DTSBUS, COUNTERREADVAL, BURSTPENDINGPHY, COARSEENABLE, COARSEINC, COUNTERLOADEN, COUNTERREADEN, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK +, RST, SELFINEOCLKDELAY, SYNCIN, SYSCLK, ENCALIBPHY, COUNTERLOADVAL); parameter integer CLKOUT_DIV = 4; parameter COARSE_BYPASS = "FALSE"; parameter integer COARSE_DELAY = 0; @@ -6841,7 +6867,7 @@ module PHASER_OUT_PHY (...); endmodule (* keep *) -module PHASER_REF (...); +module PHASER_REF(LOCKED, CLKIN, PWRDWN, RST); parameter [0:0] IS_RST_INVERTED = 1'b0; parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; output LOCKED; @@ -6853,7 +6879,8 @@ module PHASER_REF (...); endmodule (* keep *) -module PHY_CONTROL (...); +module PHY_CONTROL(PHYCTLALMOSTFULL, PHYCTLEMPTY, PHYCTLFULL, PHYCTLREADY, INRANKA, INRANKB, INRANKC, INRANKD, PCENABLECALIB, AUXOUTPUT, INBURSTPENDING, OUTBURSTPENDING, MEMREFCLK, PHYCLK, PHYCTLMSTREMPTY, PHYCTLWRENABLE, PLLLOCK, READCALIBENABLE, REFDLLLOCK, RESET, SYNCIN +, WRITECALIBENABLE, PHYCTLWD); parameter integer AO_TOGGLE = 0; parameter [3:0] AO_WRLVL_EN = 4'b0000; parameter BURST_MODE = "FALSE"; @@ -6913,7 +6940,7 @@ module PHY_CONTROL (...); input [31:0] PHYCTLWD; endmodule -module IDDRE1 (...); +module IDDRE1(Q1, Q2, C, CB, D, R); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter [0:0] IS_CB_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -6929,7 +6956,7 @@ module IDDRE1 (...); input R; endmodule -module ODDRE1 (...); +module ODDRE1(Q, C, D1, D2, SR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D1_INVERTED = 1'b0; parameter [0:0] IS_D2_INVERTED = 1'b0; @@ -6946,7 +6973,7 @@ module ODDRE1 (...); input SR; endmodule -module IDELAYE3 (...); +module IDELAYE3(CASC_OUT, CNTVALUEOUT, DATAOUT, CASC_IN, CASC_RETURN, CE, CLK, CNTVALUEIN, DATAIN, EN_VTC, IDATAIN, INC, LOAD, RST); parameter CASCADE = "NONE"; parameter DELAY_FORMAT = "TIME"; parameter DELAY_SRC = "IDATAIN"; @@ -6978,7 +7005,7 @@ module IDELAYE3 (...); input RST; endmodule -module ODELAYE3 (...); +module ODELAYE3(CASC_OUT, CNTVALUEOUT, DATAOUT, CASC_IN, CASC_RETURN, CE, CLK, CNTVALUEIN, EN_VTC, INC, LOAD, ODATAIN, RST); parameter CASCADE = "NONE"; parameter DELAY_FORMAT = "TIME"; parameter DELAY_TYPE = "FIXED"; @@ -7007,7 +7034,7 @@ module ODELAYE3 (...); input RST; endmodule -module ISERDESE3 (...); +module ISERDESE3(FIFO_EMPTY, INTERNAL_DIVCLK, Q, CLK, CLKDIV, CLK_B, D, FIFO_RD_CLK, FIFO_RD_EN, RST); parameter integer DATA_WIDTH = 8; parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter FIFO_ENABLE = "FALSE"; @@ -7037,7 +7064,7 @@ module ISERDESE3 (...); input RST; endmodule -module OSERDESE3 (...); +module OSERDESE3(OQ, T_OUT, CLK, CLKDIV, D, RST, T); parameter integer DATA_WIDTH = 8; parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; @@ -7063,7 +7090,9 @@ module OSERDESE3 (...); endmodule (* keep *) -module BITSLICE_CONTROL (...); +module BITSLICE_CONTROL(CLK_TO_EXT_NORTH, CLK_TO_EXT_SOUTH, DLY_RDY, DYN_DCI, NCLK_NIBBLE_OUT, PCLK_NIBBLE_OUT, RIU_RD_DATA, RIU_VALID, RX_BIT_CTRL_OUT0, RX_BIT_CTRL_OUT1, RX_BIT_CTRL_OUT2, RX_BIT_CTRL_OUT3, RX_BIT_CTRL_OUT4, RX_BIT_CTRL_OUT5, RX_BIT_CTRL_OUT6, TX_BIT_CTRL_OUT0, TX_BIT_CTRL_OUT1, TX_BIT_CTRL_OUT2, TX_BIT_CTRL_OUT3, TX_BIT_CTRL_OUT4, TX_BIT_CTRL_OUT5 +, TX_BIT_CTRL_OUT6, TX_BIT_CTRL_OUT_TRI, VTC_RDY, CLK_FROM_EXT, EN_VTC, NCLK_NIBBLE_IN, PCLK_NIBBLE_IN, PHY_RDCS0, PHY_RDCS1, PHY_RDEN, PHY_WRCS0, PHY_WRCS1, PLL_CLK, REFCLK, RIU_ADDR, RIU_CLK, RIU_NIBBLE_SEL, RIU_WR_DATA, RIU_WR_EN, RST, RX_BIT_CTRL_IN0 +, RX_BIT_CTRL_IN1, RX_BIT_CTRL_IN2, RX_BIT_CTRL_IN3, RX_BIT_CTRL_IN4, RX_BIT_CTRL_IN5, RX_BIT_CTRL_IN6, TBYTE_IN, TX_BIT_CTRL_IN0, TX_BIT_CTRL_IN1, TX_BIT_CTRL_IN2, TX_BIT_CTRL_IN3, TX_BIT_CTRL_IN4, TX_BIT_CTRL_IN5, TX_BIT_CTRL_IN6, TX_BIT_CTRL_IN_TRI); parameter CTRL_CLK = "EXTERNAL"; parameter DIV_MODE = "DIV2"; parameter EN_CLK_TO_EXT_NORTH = "DISABLE"; @@ -7148,7 +7177,7 @@ module BITSLICE_CONTROL (...); endmodule (* keep *) -module RIU_OR (...); +module RIU_OR(RIU_RD_DATA, RIU_RD_VALID, RIU_RD_DATA_LOW, RIU_RD_DATA_UPP, RIU_RD_VALID_LOW, RIU_RD_VALID_UPP); parameter SIM_DEVICE = "ULTRASCALE"; parameter real SIM_VERSION = 2.0; output [15:0] RIU_RD_DATA; @@ -7159,7 +7188,8 @@ module RIU_OR (...); input RIU_RD_VALID_UPP; endmodule -module RX_BITSLICE (...); +module RX_BITSLICE(CNTVALUEOUT, CNTVALUEOUT_EXT, FIFO_EMPTY, FIFO_WRCLK_OUT, Q, RX_BIT_CTRL_OUT, TX_BIT_CTRL_OUT, CE, CE_EXT, CLK, CLK_EXT, CNTVALUEIN, CNTVALUEIN_EXT, DATAIN, EN_VTC, EN_VTC_EXT, FIFO_RD_CLK, FIFO_RD_EN, INC, INC_EXT, LOAD +, LOAD_EXT, RST, RST_DLY, RST_DLY_EXT, RX_BIT_CTRL_IN, TX_BIT_CTRL_IN); parameter CASCADE = "TRUE"; parameter DATA_TYPE = "NONE"; parameter integer DATA_WIDTH = 8; @@ -7212,7 +7242,8 @@ module RX_BITSLICE (...); input [39:0] TX_BIT_CTRL_IN; endmodule -module RXTX_BITSLICE (...); +module RXTX_BITSLICE(FIFO_EMPTY, FIFO_WRCLK_OUT, O, Q, RX_BIT_CTRL_OUT, RX_CNTVALUEOUT, TX_BIT_CTRL_OUT, TX_CNTVALUEOUT, T_OUT, D, DATAIN, FIFO_RD_CLK, FIFO_RD_EN, RX_BIT_CTRL_IN, RX_CE, RX_CLK, RX_CNTVALUEIN, RX_EN_VTC, RX_INC, RX_LOAD, RX_RST +, RX_RST_DLY, T, TBYTE_IN, TX_BIT_CTRL_IN, TX_CE, TX_CLK, TX_CNTVALUEIN, TX_EN_VTC, TX_INC, TX_LOAD, TX_RST, TX_RST_DLY); parameter FIFO_SYNC_MODE = "FALSE"; parameter [0:0] INIT = 1'b1; parameter [0:0] IS_RX_CLK_INVERTED = 1'b0; @@ -7282,7 +7313,7 @@ module RXTX_BITSLICE (...); input TX_RST_DLY; endmodule -module TX_BITSLICE (...); +module TX_BITSLICE(CNTVALUEOUT, O, RX_BIT_CTRL_OUT, TX_BIT_CTRL_OUT, T_OUT, CE, CLK, CNTVALUEIN, D, EN_VTC, INC, LOAD, RST, RST_DLY, RX_BIT_CTRL_IN, T, TBYTE_IN, TX_BIT_CTRL_IN); parameter integer DATA_WIDTH = 8; parameter DELAY_FORMAT = "TIME"; parameter DELAY_TYPE = "FIXED"; @@ -7322,7 +7353,7 @@ module TX_BITSLICE (...); input [39:0] TX_BIT_CTRL_IN; endmodule -module TX_BITSLICE_TRI (...); +module TX_BITSLICE_TRI(BIT_CTRL_OUT, CNTVALUEOUT, TRI_OUT, BIT_CTRL_IN, CE, CLK, CNTVALUEIN, EN_VTC, INC, LOAD, RST, RST_DLY); parameter integer DATA_WIDTH = 8; parameter DELAY_FORMAT = "TIME"; parameter DELAY_TYPE = "FIXED"; @@ -7354,7 +7385,7 @@ module TX_BITSLICE_TRI (...); input RST_DLY; endmodule -module IODELAY2 (...); +module IODELAY2(BUSY, DATAOUT2, DATAOUT, DOUT, TOUT, CAL, CE, CLK, IDATAIN, INC, IOCLK0, IOCLK1, ODATAIN, RST, T); parameter COUNTER_WRAPAROUND = "WRAPAROUND"; parameter DATA_RATE = "SDR"; parameter DELAY_SRC = "IO"; @@ -7385,7 +7416,7 @@ module IODELAY2 (...); input T; endmodule -module IODRP2 (...); +module IODRP2(DATAOUT2, DATAOUT, DOUT, SDO, TOUT, ADD, BKST, CLK, CS, IDATAIN, IOCLK0, IOCLK1, ODATAIN, SDI, T); parameter DATA_RATE = "SDR"; parameter integer SIM_TAPDELAY_VALUE = 75; output DATAOUT2; @@ -7408,7 +7439,8 @@ module IODRP2 (...); input T; endmodule -module IODRP2_MCB (...); +module IODRP2_MCB(AUXSDO, DATAOUT2, DATAOUT, DOUT, DQSOUTN, DQSOUTP, SDO, TOUT, ADD, AUXSDOIN, BKST, CLK, CS, IDATAIN, IOCLK0, IOCLK1, MEMUPDATE, ODATAIN, SDI, T, AUXADDR +); parameter DATA_RATE = "SDR"; parameter integer IDELAY_VALUE = 0; parameter integer MCB_ADDRESS = 0; @@ -7441,7 +7473,7 @@ module IODRP2_MCB (...); input [4:0] AUXADDR; endmodule -module ISERDES2 (...); +module ISERDES2(CFB0, CFB1, DFB, FABRICOUT, INCDEC, Q1, Q2, Q3, Q4, SHIFTOUT, VALID, BITSLIP, CE0, CLK0, CLK1, CLKDIV, D, IOCE, RST, SHIFTIN); parameter BITSLIP_ENABLE = "FALSE"; parameter DATA_RATE = "SDR"; parameter integer DATA_WIDTH = 1; @@ -7472,7 +7504,8 @@ module ISERDES2 (...); input SHIFTIN; endmodule -module OSERDES2 (...); +module OSERDES2(OQ, SHIFTOUT1, SHIFTOUT2, SHIFTOUT3, SHIFTOUT4, TQ, CLK0, CLK1, CLKDIV, D1, D2, D3, D4, IOCE, OCE, RST, SHIFTIN1, SHIFTIN2, SHIFTIN3, SHIFTIN4, T1 +, T2, T3, T4, TCE, TRAIN); parameter BYPASS_GCLK_FF = "FALSE"; parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_OT = "DDR"; @@ -7511,7 +7544,7 @@ module OSERDES2 (...); input TRAIN; endmodule -module IBUF_DLY_ADJ (...); +module IBUF_DLY_ADJ(O, I, S); parameter DELAY_OFFSET = "OFF"; parameter IOSTANDARD = "DEFAULT"; output O; @@ -7520,7 +7553,7 @@ module IBUF_DLY_ADJ (...); input [2:0] S; endmodule -module IBUF_IBUFDISABLE (...); +module IBUF_IBUFDISABLE(O, I, IBUFDISABLE); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SIM_DEVICE = "7SERIES"; @@ -7531,7 +7564,7 @@ module IBUF_IBUFDISABLE (...); input IBUFDISABLE; endmodule -module IBUF_INTERMDISABLE (...); +module IBUF_INTERMDISABLE(O, I, IBUFDISABLE, INTERMDISABLE); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SIM_DEVICE = "7SERIES"; @@ -7543,13 +7576,13 @@ module IBUF_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUF_ANALOG (...); +module IBUF_ANALOG(O, I); output O; (* iopad_external_pin *) input I; endmodule -module IBUFE3 (...); +module IBUFE3(O, I, IBUFDISABLE, OSC, OSC_EN, VREF); parameter CCIO_EN = "TRUE"; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7565,7 +7598,7 @@ module IBUFE3 (...); input VREF; endmodule -module IBUFDS (...); +module IBUFDS(O, I, IB); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -7580,7 +7613,7 @@ module IBUFDS (...); input IB; endmodule -module IBUFDS_DLY_ADJ (...); +module IBUFDS_DLY_ADJ(O, I, IB, S); parameter DELAY_OFFSET = "OFF"; parameter DIFF_TERM = "FALSE"; parameter IOSTANDARD = "DEFAULT"; @@ -7592,7 +7625,7 @@ module IBUFDS_DLY_ADJ (...); input [2:0] S; endmodule -module IBUFDS_IBUFDISABLE (...); +module IBUFDS_IBUFDISABLE(O, I, IB, IBUFDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7607,7 +7640,7 @@ module IBUFDS_IBUFDISABLE (...); input IBUFDISABLE; endmodule -module IBUFDS_INTERMDISABLE (...); +module IBUFDS_INTERMDISABLE(O, I, IB, IBUFDISABLE, INTERMDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7623,7 +7656,7 @@ module IBUFDS_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUFDS_DIFF_OUT (...); +module IBUFDS_DIFF_OUT(O, OB, I, IB); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7636,7 +7669,7 @@ module IBUFDS_DIFF_OUT (...); input IB; endmodule -module IBUFDS_DIFF_OUT_IBUFDISABLE (...); +module IBUFDS_DIFF_OUT_IBUFDISABLE(O, OB, I, IB, IBUFDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7652,7 +7685,7 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...); input IBUFDISABLE; endmodule -module IBUFDS_DIFF_OUT_INTERMDISABLE (...); +module IBUFDS_DIFF_OUT_INTERMDISABLE(O, OB, I, IB, IBUFDISABLE, INTERMDISABLE); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7669,7 +7702,7 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUFDSE3 (...); +module IBUFDSE3(O, I, IB, IBUFDISABLE, OSC, OSC_EN); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7686,7 +7719,7 @@ module IBUFDSE3 (...); input [1:0] OSC_EN; endmodule -module IBUFDS_DPHY (...); +module IBUFDS_DPHY(HSRX_O, LPRX_O_N, LPRX_O_P, HSRX_DISABLE, I, IB, LPRX_DISABLE); parameter DIFF_TERM = "TRUE"; parameter IOSTANDARD = "DEFAULT"; output HSRX_O; @@ -7700,7 +7733,7 @@ module IBUFDS_DPHY (...); input LPRX_DISABLE; endmodule -module IBUFGDS (...); +module IBUFGDS(O, I, IB); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; parameter IBUF_DELAY_VALUE = "0"; @@ -7713,7 +7746,7 @@ module IBUFGDS (...); input IB; endmodule -module IBUFGDS_DIFF_OUT (...); +module IBUFGDS_DIFF_OUT(O, OB, I, IB); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7726,7 +7759,7 @@ module IBUFGDS_DIFF_OUT (...); input IB; endmodule -module IOBUF_DCIEN (...); +module IOBUF_DCIEN(O, IO, DCITERMDISABLE, I, IBUFDISABLE, T); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7742,7 +7775,7 @@ module IOBUF_DCIEN (...); input T; endmodule -module IOBUF_INTERMDISABLE (...); +module IOBUF_INTERMDISABLE(O, IO, I, IBUFDISABLE, INTERMDISABLE, T); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7758,7 +7791,7 @@ module IOBUF_INTERMDISABLE (...); input T; endmodule -module IOBUFE3 (...); +module IOBUFE3(O, IO, DCITERMDISABLE, I, IBUFDISABLE, OSC, OSC_EN, T, VREF); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -7777,7 +7810,7 @@ module IOBUFE3 (...); input VREF; endmodule -module IOBUFDS (...); +module IOBUFDS(O, IO, IOB, I, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7792,7 +7825,7 @@ module IOBUFDS (...); input T; endmodule -module IOBUFDS_DCIEN (...); +module IOBUFDS_DCIEN(O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7811,7 +7844,7 @@ module IOBUFDS_DCIEN (...); input T; endmodule -module IOBUFDS_INTERMDISABLE (...); +module IOBUFDS_INTERMDISABLE(O, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7830,7 +7863,7 @@ module IOBUFDS_INTERMDISABLE (...); input T; endmodule -module IOBUFDS_DIFF_OUT (...); +module IOBUFDS_DIFF_OUT(O, OB, IO, IOB, I, TM, TS); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7846,7 +7879,7 @@ module IOBUFDS_DIFF_OUT (...); input TS; endmodule -module IOBUFDS_DIFF_OUT_DCIEN (...); +module IOBUFDS_DIFF_OUT_DCIEN(O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7866,7 +7899,7 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); input TS; endmodule -module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); +module IOBUFDS_DIFF_OUT_INTERMDISABLE(O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7886,7 +7919,7 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); input TS; endmodule -module IOBUFDSE3 (...); +module IOBUFDSE3(O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, OSC, OSC_EN, T); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; @@ -7906,7 +7939,7 @@ module IOBUFDSE3 (...); input T; endmodule -module OBUFDS (...); +module OBUFDS(O, OB, I); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; @@ -7917,7 +7950,7 @@ module OBUFDS (...); input I; endmodule -module OBUFDS_DPHY (...); +module OBUFDS_DPHY(O, OB, HSTX_I, HSTX_T, LPTX_I_N, LPTX_I_P, LPTX_T); parameter IOSTANDARD = "DEFAULT"; (* iopad_external_pin *) output O; @@ -7930,7 +7963,7 @@ module OBUFDS_DPHY (...); input LPTX_T; endmodule -module OBUFTDS (...); +module OBUFTDS(O, OB, I, T); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; @@ -7942,32 +7975,32 @@ module OBUFTDS (...); input T; endmodule -module KEEPER (...); +module KEEPER(O); inout O; endmodule -module PULLDOWN (...); +module PULLDOWN(O); output O; endmodule -module PULLUP (...); +module PULLUP(O); output O; endmodule (* keep *) -module DCIRESET (...); +module DCIRESET(LOCKED, RST); output LOCKED; input RST; endmodule (* keep *) -module HPIO_VREF (...); +module HPIO_VREF(VREF, FABRIC_VREF_TUNE); parameter VREF_CNTR = "OFF"; output VREF; input [6:0] FABRIC_VREF_TUNE; endmodule -module BUFGCE (...); +module BUFGCE(O, CE, I); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; parameter [0:0] IS_I_INVERTED = 1'b0; @@ -7981,14 +8014,14 @@ module BUFGCE (...); input I; endmodule -module BUFGCE_1 (...); +module BUFGCE_1(O, CE, I); (* clkbuf_driver *) output O; input CE; input I; endmodule -module BUFGMUX (...); +module BUFGMUX(O, I0, I1, S); parameter CLK_SEL_TYPE = "SYNC"; (* clkbuf_driver *) output O; @@ -7997,7 +8030,7 @@ module BUFGMUX (...); input S; endmodule -module BUFGMUX_1 (...); +module BUFGMUX_1(O, I0, I1, S); parameter CLK_SEL_TYPE = "SYNC"; (* clkbuf_driver *) output O; @@ -8006,7 +8039,7 @@ module BUFGMUX_1 (...); input S; endmodule -module BUFGMUX_CTRL (...); +module BUFGMUX_CTRL(O, I0, I1, S); (* clkbuf_driver *) output O; input I0; @@ -8014,7 +8047,7 @@ module BUFGMUX_CTRL (...); input S; endmodule -module BUFGMUX_VIRTEX4 (...); +module BUFGMUX_VIRTEX4(O, I0, I1, S); (* clkbuf_driver *) output O; input I0; @@ -8022,7 +8055,7 @@ module BUFGMUX_VIRTEX4 (...); input S; endmodule -module BUFG_GT (...); +module BUFG_GT(O, CE, CEMASK, CLR, CLRMASK, DIV, I); parameter SIM_DEVICE = "ULTRASCALE"; parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) @@ -8035,7 +8068,7 @@ module BUFG_GT (...); input I; endmodule -module BUFG_GT_SYNC (...); +module BUFG_GT_SYNC(CESYNC, CLRSYNC, CE, CLK, CLR); output CESYNC; output CLRSYNC; input CE; @@ -8043,7 +8076,7 @@ module BUFG_GT_SYNC (...); input CLR; endmodule -module BUFG_PS (...); +module BUFG_PS(O, I); parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) @@ -8051,7 +8084,7 @@ module BUFG_PS (...); input I; endmodule -module BUFGCE_DIV (...); +module BUFGCE_DIV(O, CE, CLR, I); parameter integer BUFGCE_DIVIDE = 1; parameter CE_TYPE = "SYNC"; parameter HARDSYNC_CLR = "FALSE"; @@ -8070,13 +8103,13 @@ module BUFGCE_DIV (...); input I; endmodule -module BUFH (...); +module BUFH(O, I); (* clkbuf_driver *) output O; input I; endmodule -module BUFIO2 (...); +module BUFIO2(DIVCLK, IOCLK, SERDESSTROBE, I); parameter DIVIDE_BYPASS = "TRUE"; parameter integer DIVIDE = 1; parameter I_INVERT = "FALSE"; @@ -8089,7 +8122,7 @@ module BUFIO2 (...); input I; endmodule -module BUFIO2_2CLK (...); +module BUFIO2_2CLK(DIVCLK, IOCLK, SERDESSTROBE, I, IB); parameter integer DIVIDE = 2; (* clkbuf_driver *) output DIVCLK; @@ -8100,14 +8133,14 @@ module BUFIO2_2CLK (...); input IB; endmodule -module BUFIO2FB (...); +module BUFIO2FB(O, I); parameter DIVIDE_BYPASS = "TRUE"; (* clkbuf_driver *) output O; input I; endmodule -module BUFPLL (...); +module BUFPLL(IOCLK, LOCK, SERDESSTROBE, GCLK, LOCKED, PLLIN); parameter integer DIVIDE = 1; parameter ENABLE_SYNC = "TRUE"; (* clkbuf_driver *) @@ -8119,7 +8152,7 @@ module BUFPLL (...); input PLLIN; endmodule -module BUFPLL_MCB (...); +module BUFPLL_MCB(IOCLK0, IOCLK1, LOCK, SERDESSTROBE0, SERDESSTROBE1, GCLK, LOCKED, PLLIN0, PLLIN1); parameter integer DIVIDE = 2; parameter LOCK_SRC = "LOCK_TO_0"; (* clkbuf_driver *) @@ -8135,13 +8168,13 @@ module BUFPLL_MCB (...); input PLLIN1; endmodule -module BUFIO (...); +module BUFIO(O, I); (* clkbuf_driver *) output O; input I; endmodule -module BUFIODQS (...); +module BUFIODQS(O, DQSMASK, I); parameter DQSMASK_ENABLE = "FALSE"; (* clkbuf_driver *) output O; @@ -8149,7 +8182,7 @@ module BUFIODQS (...); input I; endmodule -module BUFR (...); +module BUFR(O, CE, CLR, I); parameter BUFR_DIVIDE = "BYPASS"; parameter SIM_DEVICE = "7SERIES"; (* clkbuf_driver *) @@ -8159,13 +8192,13 @@ module BUFR (...); input I; endmodule -module BUFMR (...); +module BUFMR(O, I); (* clkbuf_driver *) output O; input I; endmodule -module BUFMRCE (...); +module BUFMRCE(O, CE, I); parameter CE_TYPE = "SYNC"; parameter integer INIT_OUT = 0; parameter [0:0] IS_CE_INVERTED = 1'b0; @@ -8176,7 +8209,7 @@ module BUFMRCE (...); input I; endmodule -module DCM (...); +module DCM(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST, CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8214,7 +8247,7 @@ module DCM (...); output [7:0] STATUS; endmodule -module DCM_SP (...); +module DCM_SP(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST, CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8251,7 +8284,7 @@ module DCM_SP (...); output [7:0] STATUS; endmodule -module DCM_CLKGEN (...); +module DCM_CLKGEN(CLKFX180, CLKFX, CLKFXDV, LOCKED, PROGDONE, STATUS, CLKIN, FREEZEDCM, PROGCLK, PROGDATA, PROGEN, RST); parameter SPREAD_SPECTRUM = "NONE"; parameter STARTUP_WAIT = "FALSE"; parameter integer CLKFXDV_DIVIDE = 2; @@ -8273,7 +8306,8 @@ module DCM_CLKGEN (...); input RST; endmodule -module DCM_ADV (...); +module DCM_ADV(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, DRDY, LOCKED, PSDONE, DO, CLKFB, CLKIN, DCLK, DEN, DWE, PSCLK, PSEN, PSINCDEC +, RST, DI, DADDR); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8317,7 +8351,7 @@ module DCM_ADV (...); input [6:0] DADDR; endmodule -module DCM_BASE (...); +module DCM_BASE(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, LOCKED, CLKFB, CLKIN, RST); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8349,7 +8383,7 @@ module DCM_BASE (...); input RST; endmodule -module DCM_PS (...); +module DCM_PS(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, LOCKED, PSDONE, DO, CLKFB, CLKIN, PSCLK, PSEN, PSINCDEC, RST); parameter real CLKDV_DIVIDE = 2.0; parameter integer CLKFX_DIVIDE = 1; parameter integer CLKFX_MULTIPLY = 4; @@ -8386,7 +8420,7 @@ module DCM_PS (...); input RST; endmodule -module PMCD (...); +module PMCD(CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, CLKC, CLKD, REL, RST); parameter EN_REL = "FALSE"; parameter RST_DEASSERT_CLK = "CLKA"; output CLKA1; @@ -8404,7 +8438,8 @@ module PMCD (...); input RST; endmodule -module PLL_ADV (...); +module PLL_ADV(CLKFBDCM, CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUTDCM0, CLKOUTDCM1, CLKOUTDCM2, CLKOUTDCM3, CLKOUTDCM4, CLKOUTDCM5, DRDY, LOCKED, DO, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL +, DCLK, DEN, DWE, REL, RST, DI, DADDR); parameter BANDWIDTH = "OPTIMIZED"; parameter CLK_FEEDBACK = "CLKFBOUT"; parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; @@ -8480,7 +8515,7 @@ module PLL_ADV (...); input [4:0] DADDR; endmodule -module PLL_BASE (...); +module PLL_BASE(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter integer CLKFBOUT_MULT = 1; parameter real CLKFBOUT_PHASE = 0.0; @@ -8521,7 +8556,8 @@ module PLL_BASE (...); input RST; endmodule -module MMCM_ADV (...); +module MMCM_ADV(CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DRDY, LOCKED, PSDONE, DO, CLKFBIN, CLKIN1 +, CLKIN2, CLKINSEL, DCLK, DEN, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST, DI, DADDR); parameter BANDWIDTH = "OPTIMIZED"; parameter CLKFBOUT_USE_FINE_PS = "FALSE"; parameter CLKOUT0_USE_FINE_PS = "FALSE"; @@ -8604,7 +8640,7 @@ module MMCM_ADV (...); input [6:0] DADDR; endmodule -module MMCM_BASE (...); +module MMCM_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -8655,7 +8691,8 @@ module MMCM_BASE (...); input RST; endmodule -module MMCME2_ADV (...); +module MMCME2_ADV(CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CLKFBIN, CLKIN1 +, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKPFD_FREQ_MAX = 550.000; @@ -8750,7 +8787,7 @@ module MMCME2_ADV (...); input RST; endmodule -module MMCME2_BASE (...); +module MMCME2_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -8800,7 +8837,8 @@ module MMCME2_BASE (...); input RST; endmodule -module PLLE2_ADV (...); +module PLLE2_ADV(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, DRDY, LOCKED, DO, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DCLK, DEN, DWE, PWRDWN, RST, DI, DADDR +); parameter BANDWIDTH = "OPTIMIZED"; parameter COMPENSATION = "ZHOLD"; parameter STARTUP_WAIT = "FALSE"; @@ -8864,7 +8902,7 @@ module PLLE2_ADV (...); input [6:0] DADDR; endmodule -module PLLE2_BASE (...); +module PLLE2_BASE(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter integer CLKFBOUT_MULT = 5; parameter real CLKFBOUT_PHASE = 0.000; @@ -8904,7 +8942,8 @@ module PLLE2_BASE (...); input RST; endmodule -module MMCME3_ADV (...); +module MMCME3_ADV(CDDCDONE, CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CDDCREQ +, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKPFD_FREQ_MAX = 550.000; @@ -9007,7 +9046,7 @@ module MMCME3_ADV (...); input RST; endmodule -module MMCME3_BASE (...); +module MMCME3_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -9065,7 +9104,7 @@ module MMCME3_BASE (...); input RST; endmodule -module PLLE3_ADV (...); +module PLLE3_ADV(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, DO, DRDY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, DADDR, DCLK, DEN, DI, DWE, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 70.000; parameter real CLKPFD_FREQ_MAX = 667.500; @@ -9115,7 +9154,7 @@ module PLLE3_ADV (...); input RST; endmodule -module PLLE3_BASE (...); +module PLLE3_BASE(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, PWRDWN, RST); parameter integer CLKFBOUT_MULT = 5; parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_PERIOD = 0.000; @@ -9151,7 +9190,8 @@ module PLLE3_BASE (...); input RST; endmodule -module MMCME4_ADV (...); +module MMCME4_ADV(CDDCDONE, CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CDDCREQ +, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKPFD_FREQ_MAX = 550.000; @@ -9254,7 +9294,7 @@ module MMCME4_ADV (...); input RST; endmodule -module MMCME4_BASE (...); +module MMCME4_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST); parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; @@ -9312,7 +9352,7 @@ module MMCME4_BASE (...); input RST; endmodule -module PLLE4_ADV (...); +module PLLE4_ADV(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, DO, DRDY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, DADDR, DCLK, DEN, DI, DWE, PWRDWN, RST); parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 70.000; parameter real CLKPFD_FREQ_MAX = 667.500; @@ -9362,7 +9402,7 @@ module PLLE4_ADV (...); input RST; endmodule -module PLLE4_BASE (...); +module PLLE4_BASE(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, PWRDWN, RST); parameter integer CLKFBOUT_MULT = 5; parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_PERIOD = 0.000; @@ -9398,13 +9438,14 @@ module PLLE4_BASE (...); input RST; endmodule -module BUFT (...); +module BUFT(O, I, T); output O; input I; input T; endmodule -module IN_FIFO (...); +module IN_FIFO(ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, RDCLK, RDEN, RESET, WRCLK, WREN, D0, D1 +, D2, D3, D4, D7, D8, D9, D5, D6); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; @@ -9442,7 +9483,8 @@ module IN_FIFO (...); input [7:0] D6; endmodule -module OUT_FIFO (...); +module OUT_FIFO(ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL, Q0, Q1, Q2, Q3, Q4, Q7, Q8, Q9, Q5, Q6, RDCLK, RDEN, RESET, WRCLK, WREN, D0, D1 +, D2, D3, D4, D5, D6, D7, D8, D9); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; @@ -9481,7 +9523,7 @@ module OUT_FIFO (...); input [7:0] D9; endmodule -module HARD_SYNC (...); +module HARD_SYNC(DOUT, CLK, DIN); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLK_INVERTED = 1'b0; parameter integer LATENCY = 2; @@ -9493,14 +9535,14 @@ module HARD_SYNC (...); endmodule (* keep *) -module STARTUP_SPARTAN3 (...); +module STARTUP_SPARTAN3(CLK, GSR, GTS); input CLK; input GSR; input GTS; endmodule (* keep *) -module STARTUP_SPARTAN3E (...); +module STARTUP_SPARTAN3E(CLK, GSR, GTS, MBT); input CLK; input GSR; input GTS; @@ -9508,14 +9550,14 @@ module STARTUP_SPARTAN3E (...); endmodule (* keep *) -module STARTUP_SPARTAN3A (...); +module STARTUP_SPARTAN3A(CLK, GSR, GTS); input CLK; input GSR; input GTS; endmodule (* keep *) -module STARTUP_SPARTAN6 (...); +module STARTUP_SPARTAN6(CFGCLK, CFGMCLK, EOS, CLK, GSR, GTS, KEYCLEARB); output CFGCLK; output CFGMCLK; output EOS; @@ -9526,7 +9568,7 @@ module STARTUP_SPARTAN6 (...); endmodule (* keep *) -module STARTUP_VIRTEX4 (...); +module STARTUP_VIRTEX4(EOS, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); output EOS; input CLK; input GSR; @@ -9538,7 +9580,7 @@ module STARTUP_VIRTEX4 (...); endmodule (* keep *) -module STARTUP_VIRTEX5 (...); +module STARTUP_VIRTEX5(CFGCLK, CFGMCLK, DINSPI, EOS, TCKSPI, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); output CFGCLK; output CFGMCLK; output DINSPI; @@ -9554,7 +9596,7 @@ module STARTUP_VIRTEX5 (...); endmodule (* keep *) -module STARTUP_VIRTEX6 (...); +module STARTUP_VIRTEX6(CFGCLK, CFGMCLK, DINSPI, EOS, PREQ, TCKSPI, CLK, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); parameter PROG_USR = "FALSE"; output CFGCLK; output CFGMCLK; @@ -9574,7 +9616,7 @@ module STARTUP_VIRTEX6 (...); endmodule (* keep *) -module STARTUPE2 (...); +module STARTUPE2(CFGCLK, CFGMCLK, EOS, PREQ, CLK, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); parameter PROG_USR = "FALSE"; parameter real SIM_CCLK_FREQ = 0.0; output CFGCLK; @@ -9593,7 +9635,7 @@ module STARTUPE2 (...); endmodule (* keep *) -module STARTUPE3 (...); +module STARTUPE3(CFGCLK, CFGMCLK, DI, EOS, PREQ, DO, DTS, FCSBO, FCSBTS, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); parameter PROG_USR = "FALSE"; parameter real SIM_CCLK_FREQ = 0.0; output CFGCLK; @@ -9616,49 +9658,49 @@ module STARTUPE3 (...); endmodule (* keep *) -module CAPTURE_SPARTAN3 (...); +module CAPTURE_SPARTAN3(CAP, CLK); parameter ONESHOT = "FALSE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_SPARTAN3A (...); +module CAPTURE_SPARTAN3A(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_VIRTEX4 (...); +module CAPTURE_VIRTEX4(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_VIRTEX5 (...); +module CAPTURE_VIRTEX5(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTURE_VIRTEX6 (...); +module CAPTURE_VIRTEX6(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module CAPTUREE2 (...); +module CAPTUREE2(CAP, CLK); parameter ONESHOT = "TRUE"; input CAP; input CLK; endmodule (* keep *) -module ICAP_SPARTAN3A (...); +module ICAP_SPARTAN3A(BUSY, O, CE, CLK, WRITE, I); output BUSY; output [7:0] O; input CE; @@ -9668,7 +9710,7 @@ module ICAP_SPARTAN3A (...); endmodule (* keep *) -module ICAP_SPARTAN6 (...); +module ICAP_SPARTAN6(BUSY, O, CLK, CE, WRITE, I); parameter DEVICE_ID = 32'h04000093; parameter SIM_CFG_FILE_NAME = "NONE"; output BUSY; @@ -9680,7 +9722,7 @@ module ICAP_SPARTAN6 (...); endmodule (* keep *) -module ICAP_VIRTEX4 (...); +module ICAP_VIRTEX4(BUSY, O, CE, CLK, WRITE, I); parameter ICAP_WIDTH = "X8"; output BUSY; output [31:0] O; @@ -9691,7 +9733,7 @@ module ICAP_VIRTEX4 (...); endmodule (* keep *) -module ICAP_VIRTEX5 (...); +module ICAP_VIRTEX5(BUSY, O, CE, CLK, WRITE, I); parameter ICAP_WIDTH = "X8"; output BUSY; output [31:0] O; @@ -9702,7 +9744,7 @@ module ICAP_VIRTEX5 (...); endmodule (* keep *) -module ICAP_VIRTEX6 (...); +module ICAP_VIRTEX6(BUSY, O, CLK, CSB, RDWRB, I); parameter [31:0] DEVICE_ID = 32'h04244093; parameter ICAP_WIDTH = "X8"; parameter SIM_CFG_FILE_NAME = "NONE"; @@ -9715,7 +9757,7 @@ module ICAP_VIRTEX6 (...); endmodule (* keep *) -module ICAPE2 (...); +module ICAPE2(O, CLK, CSIB, RDWRB, I); parameter [31:0] DEVICE_ID = 32'h04244093; parameter ICAP_WIDTH = "X32"; parameter SIM_CFG_FILE_NAME = "NONE"; @@ -9727,7 +9769,7 @@ module ICAPE2 (...); endmodule (* keep *) -module ICAPE3 (...); +module ICAPE3(AVAIL, O, PRDONE, PRERROR, CLK, CSIB, RDWRB, I); parameter [31:0] DEVICE_ID = 32'h03628093; parameter ICAP_AUTO_SWITCH = "DISABLE"; parameter SIM_CFG_FILE_NAME = "NONE"; @@ -9742,7 +9784,7 @@ module ICAPE3 (...); endmodule (* keep *) -module BSCAN_SPARTAN3 (...); +module BSCAN_SPARTAN3(CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2); output CAPTURE; output DRCK1; output DRCK2; @@ -9757,7 +9799,7 @@ module BSCAN_SPARTAN3 (...); endmodule (* keep *) -module BSCAN_SPARTAN3A (...); +module BSCAN_SPARTAN3A(CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE, TDO1, TDO2); output CAPTURE; output DRCK1; output DRCK2; @@ -9774,7 +9816,7 @@ module BSCAN_SPARTAN3A (...); endmodule (* keep *) -module BSCAN_SPARTAN6 (...); +module BSCAN_SPARTAN6(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); parameter integer JTAG_CHAIN = 1; output CAPTURE; output DRCK; @@ -9790,7 +9832,7 @@ module BSCAN_SPARTAN6 (...); endmodule (* keep *) -module BSCAN_VIRTEX4 (...); +module BSCAN_VIRTEX4(CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO); parameter integer JTAG_CHAIN = 1; output CAPTURE; output DRCK; @@ -9803,7 +9845,7 @@ module BSCAN_VIRTEX4 (...); endmodule (* keep *) -module BSCAN_VIRTEX5 (...); +module BSCAN_VIRTEX5(CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO); parameter integer JTAG_CHAIN = 1; output CAPTURE; output DRCK; @@ -9816,7 +9858,7 @@ module BSCAN_VIRTEX5 (...); endmodule (* keep *) -module BSCAN_VIRTEX6 (...); +module BSCAN_VIRTEX6(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); parameter DISABLE_JTAG = "FALSE"; parameter integer JTAG_CHAIN = 1; output CAPTURE; @@ -9833,7 +9875,7 @@ module BSCAN_VIRTEX6 (...); endmodule (* keep *) -module BSCANE2 (...); +module BSCANE2(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); parameter DISABLE_JTAG = "FALSE"; parameter integer JTAG_CHAIN = 1; output CAPTURE; @@ -9849,7 +9891,7 @@ module BSCANE2 (...); input TDO; endmodule -module DNA_PORT (...); +module DNA_PORT(DOUT, CLK, DIN, READ, SHIFT); parameter [56:0] SIM_DNA_VALUE = 57'h0; output DOUT; input CLK; @@ -9858,7 +9900,7 @@ module DNA_PORT (...); input SHIFT; endmodule -module DNA_PORTE2 (...); +module DNA_PORTE2(DOUT, CLK, DIN, READ, SHIFT); parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000; output DOUT; input CLK; @@ -9867,20 +9909,20 @@ module DNA_PORTE2 (...); input SHIFT; endmodule -module FRAME_ECC_VIRTEX4 (...); +module FRAME_ECC_VIRTEX4(ERROR, SYNDROME, SYNDROMEVALID); output ERROR; output [11:0] SYNDROME; output SYNDROMEVALID; endmodule -module FRAME_ECC_VIRTEX5 (...); +module FRAME_ECC_VIRTEX5(CRCERROR, ECCERROR, SYNDROMEVALID, SYNDROME); output CRCERROR; output ECCERROR; output SYNDROMEVALID; output [11:0] SYNDROME; endmodule -module FRAME_ECC_VIRTEX6 (...); +module FRAME_ECC_VIRTEX6(CRCERROR, ECCERROR, ECCERRORSINGLE, SYNDROMEVALID, SYNDROME, FAR, SYNBIT, SYNWORD); parameter FARSRC = "EFAR"; parameter FRAME_RBT_IN_FILENAME = "NONE"; output CRCERROR; @@ -9893,7 +9935,7 @@ module FRAME_ECC_VIRTEX6 (...); output [6:0] SYNWORD; endmodule -module FRAME_ECCE2 (...); +module FRAME_ECCE2(CRCERROR, ECCERROR, ECCERRORSINGLE, SYNDROMEVALID, SYNDROME, FAR, SYNBIT, SYNWORD); parameter FARSRC = "EFAR"; parameter FRAME_RBT_IN_FILENAME = "NONE"; output CRCERROR; @@ -9906,7 +9948,7 @@ module FRAME_ECCE2 (...); output [6:0] SYNWORD; endmodule -module FRAME_ECCE3 (...); +module FRAME_ECCE3(CRCERROR, ECCERRORNOTSINGLE, ECCERRORSINGLE, ENDOFFRAME, ENDOFSCAN, FAR, FARSEL, ICAPBOTCLK, ICAPTOPCLK); output CRCERROR; output ECCERRORNOTSINGLE; output ECCERRORSINGLE; @@ -9918,7 +9960,7 @@ module FRAME_ECCE3 (...); input ICAPTOPCLK; endmodule -module FRAME_ECCE4 (...); +module FRAME_ECCE4(CRCERROR, ECCERRORNOTSINGLE, ECCERRORSINGLE, ENDOFFRAME, ENDOFSCAN, FAR, FARSEL, ICAPBOTCLK, ICAPTOPCLK); output CRCERROR; output ECCERRORNOTSINGLE; output ECCERRORSINGLE; @@ -9930,47 +9972,47 @@ module FRAME_ECCE4 (...); input ICAPTOPCLK; endmodule -module USR_ACCESS_VIRTEX4 (...); +module USR_ACCESS_VIRTEX4(DATA, DATAVALID); output [31:0] DATA; output DATAVALID; endmodule -module USR_ACCESS_VIRTEX5 (...); +module USR_ACCESS_VIRTEX5(CFGCLK, DATA, DATAVALID); output CFGCLK; output [31:0] DATA; output DATAVALID; endmodule -module USR_ACCESS_VIRTEX6 (...); +module USR_ACCESS_VIRTEX6(CFGCLK, DATA, DATAVALID); output CFGCLK; output [31:0] DATA; output DATAVALID; endmodule -module USR_ACCESSE2 (...); +module USR_ACCESSE2(CFGCLK, DATAVALID, DATA); output CFGCLK; output DATAVALID; output [31:0] DATA; endmodule -module POST_CRC_INTERNAL (...); +module POST_CRC_INTERNAL(CRCERROR); output CRCERROR; endmodule (* keep *) -module SUSPEND_SYNC (...); +module SUSPEND_SYNC(SREQ, CLK, SACK); output SREQ; input CLK; input SACK; endmodule (* keep *) -module KEY_CLEAR (...); +module KEY_CLEAR(KEYCLEARB); input KEYCLEARB; endmodule (* keep *) -module MASTER_JTAG (...); +module MASTER_JTAG(TDO, TCK, TDI, TMS); output TDO; input TCK; input TDI; @@ -9978,7 +10020,7 @@ module MASTER_JTAG (...); endmodule (* keep *) -module SPI_ACCESS (...); +module SPI_ACCESS(MISO, CLK, CSB, MOSI); parameter SIM_DELAY_TYPE = "SCALED"; parameter SIM_DEVICE = "3S1400AN"; parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -9990,13 +10032,14 @@ module SPI_ACCESS (...); input MOSI; endmodule -module EFUSE_USR (...); +module EFUSE_USR(EFUSEUSR); parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; output [31:0] EFUSEUSR; endmodule (* keep *) -module SYSMON (...); +module SYSMON(BUSY, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, DO, ALM, CHANNEL, CONVST, CONVSTCLK, DCLK, DEN, DWE, RESET, VN, VP, DI, VAUXN +, VAUXP, DADDR); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; parameter [15:0] INIT_42 = 16'h0800; @@ -10049,7 +10092,8 @@ module SYSMON (...); endmodule (* keep *) -module XADC (...); +module XADC(BUSY, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, DO, ALM, CHANNEL, MUXADDR, CONVST, CONVSTCLK, DCLK, DEN, DWE, RESET, VN, VP, DI +, VAUXN, VAUXP, DADDR); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; parameter [15:0] INIT_42 = 16'h0800; @@ -10115,7 +10159,8 @@ module XADC (...); endmodule (* keep *) -module SYSMONE1 (...); +module SYSMONE1(ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, I2C_SCLK_TS, I2C_SDA_TS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, MUXADDR, OT, CONVST, CONVSTCLK, DADDR, DCLK, DEN, DI, DWE +, I2C_SCLK, I2C_SDA, RESET, VAUXN, VAUXP, VN, VP); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; parameter [15:0] INIT_42 = 16'h0; @@ -10224,7 +10269,8 @@ module SYSMONE1 (...); endmodule (* keep *) -module SYSMONE4 (...); +module SYSMONE4(ADC_DATA, ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, I2C_SCLK_TS, I2C_SDA_TS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, MUXADDR, OT, SMBALERT_TS, CONVST, CONVSTCLK, DADDR, DCLK, DEN +, DI, DWE, I2C_SCLK, I2C_SDA, RESET, VAUXN, VAUXP, VN, VP); parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; parameter [15:0] INIT_40 = 16'h0000; parameter [15:0] INIT_41 = 16'h0000; @@ -10336,7 +10382,17 @@ module SYSMONE4 (...); input VP; endmodule -module GTPA1_DUAL (...); +module GTPA1_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET0, PLLLKDET1, REFCLKOUT0, REFCLKOUT1, REFCLKPLL0, REFCLKPLL1, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1 +, RXCOMMADET0, RXCOMMADET1, RXELECIDLE0, RXELECIDLE1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXVALID0, RXVALID1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, DRPDO, GTPCLKFBEAST, GTPCLKFBWEST, GTPCLKOUT0, GTPCLKOUT1 +, RXLOSSOFSYNC0, RXLOSSOFSYNC1, TXBUFSTATUS0, TXBUFSTATUS1, RXBUFSTATUS0, RXBUFSTATUS1, RXCHBONDO, RXCLKCORCNT0, RXCLKCORCNT1, RXSTATUS0, RXSTATUS1, RXDATA0, RXDATA1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXDISPERR0, RXDISPERR1, RXNOTINTABLE0, RXNOTINTABLE1 +, RXRUNDISP0, RXRUNDISP1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, RCALOUTEAST, RCALOUTWEST, TSTOUT0, TSTOUT1, CLK00, CLK01, CLK10, CLK11, CLKINEAST0, CLKINEAST1, CLKINWEST0, CLKINWEST1, DCLK, DEN, DWE +, GATERXELECIDLE0, GATERXELECIDLE1, GCLK00, GCLK01, GCLK10, GCLK11, GTPRESET0, GTPRESET1, IGNORESIGDET0, IGNORESIGDET1, INTDATAWIDTH0, INTDATAWIDTH1, PLLCLK00, PLLCLK01, PLLCLK10, PLLCLK11, PLLLKDETEN0, PLLLKDETEN1, PLLPOWERDOWN0, PLLPOWERDOWN1, PRBSCNTRESET0 +, PRBSCNTRESET1, REFCLKPWRDNB0, REFCLKPWRDNB1, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDMASTER0, RXCHBONDMASTER1, RXCHBONDSLAVE0, RXCHBONDSLAVE1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1 +, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TSTCLK0, TSTCLK1, TXCOMSTART0 +, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXINHIBIT0, TXINHIBIT1, TXPDOWNASYNCH0, TXPDOWNASYNCH1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXPRBSFORCEERR0, TXPRBSFORCEERR1 +, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, USRCODEERR0, USRCODEERR1, TSTIN0, TSTIN1, DI, GTPCLKFBSEL0EAST, GTPCLKFBSEL0WEST, GTPCLKFBSEL1EAST, GTPCLKFBSEL1WEST, RXDATAWIDTH0, RXDATAWIDTH1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1 +, TXDATAWIDTH0, TXDATAWIDTH1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, REFSELDYPLL0, REFSELDYPLL1, RXCHBONDI, RXENPRBSTST0, RXENPRBSTST1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXENPRBSTST0, TXENPRBSTST1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXDATA0, TXDATA1, TXBYPASS8B10B0, TXBYPASS8B10B1 +, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXDIFFCTRL0, TXDIFFCTRL1, RCALINEAST, RCALINWEST, DADDR, GTPTEST0, GTPTEST1); parameter AC_CAP_DIS_0 = "TRUE"; parameter AC_CAP_DIS_1 = "TRUE"; parameter integer ALIGN_COMMA_WORD_0 = 1; @@ -10788,7 +10844,11 @@ module GTPA1_DUAL (...); input [7:0] GTPTEST1; endmodule -module GT11_CUSTOM (...); +module GT11_CUSTOM(DRDY, RXBUFERR, RXCALFAIL, RXCOMMADET, RXCYCLELIMIT, RXLOCK, RXMCLK, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXSIGDET, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCYCLELIMIT, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT +, DO, RXLOSSOFSYNC, RXCRCOUT, TXCRCOUT, CHBONDO, RXSTATUS, RXDATA, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE, RXRUNDISP, TXKERR, TXRUNDISP, DCLK, DEN, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK +, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXPMARESET, RXPOLARITY, RXRESET +, RXSLIDE, RXSYNC, RXUSRCLK2, RXUSRCLK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC +, TXUSRCLK2, TXUSRCLK, DI, LOOPBACK, RXDATAWIDTH, RXINTDATAWIDTH, TXDATAWIDTH, TXINTDATAWIDTH, RXCRCDATAWIDTH, TXCRCDATAWIDTH, CHBONDI, RXCRCIN, TXCRCIN, TXDATA, DADDR, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK); parameter ALIGN_COMMA_WORD = 1; parameter BANDGAPSEL = "FALSE"; parameter BIASRESSEL = "TRUE"; @@ -11060,7 +11120,16 @@ module GT11_CUSTOM (...); input [7:0] TXCHARISK; endmodule -module GT11_DUAL (...); +module GT11_DUAL(DRDYA, DRDYB, RXBUFERRA, RXBUFERRB, RXCALFAILA, RXCALFAILB, RXCOMMADETA, RXCOMMADETB, RXCYCLELIMITA, RXCYCLELIMITB, RXLOCKA, RXLOCKB, RXMCLKA, RXMCLKB, RXPCSHCLKOUTA, RXPCSHCLKOUTB, RXREALIGNA, RXREALIGNB, RXRECCLK1A, RXRECCLK1B, RXRECCLK2A +, RXRECCLK2B, RXSIGDETA, RXSIGDETB, TX1NA, TX1NB, TX1PA, TX1PB, TXBUFERRA, TXBUFERRB, TXCALFAILA, TXCALFAILB, TXCYCLELIMITA, TXCYCLELIMITB, TXLOCKA, TXLOCKB, TXOUTCLK1A, TXOUTCLK1B, TXOUTCLK2A, TXOUTCLK2B, TXPCSHCLKOUTA, TXPCSHCLKOUTB +, DOA, DOB, RXLOSSOFSYNCA, RXLOSSOFSYNCB, RXCRCOUTA, RXCRCOUTB, TXCRCOUTA, TXCRCOUTB, CHBONDOA, CHBONDOB, RXSTATUSA, RXSTATUSB, RXDATAA, RXDATAB, RXCHARISCOMMAA, RXCHARISCOMMAB, RXCHARISKA, RXCHARISKB, RXDISPERRA, RXDISPERRB, RXNOTINTABLEA +, RXNOTINTABLEB, RXRUNDISPA, RXRUNDISPB, TXKERRA, TXKERRB, TXRUNDISPA, TXRUNDISPB, DCLKA, DCLKB, DENA, DENB, DWEA, DWEB, ENCHANSYNCA, ENCHANSYNCB, ENMCOMMAALIGNA, ENMCOMMAALIGNB, ENPCOMMAALIGNA, ENPCOMMAALIGNB, GREFCLKA, GREFCLKB +, POWERDOWNA, POWERDOWNB, REFCLK1A, REFCLK1B, REFCLK2A, REFCLK2B, RX1NA, RX1NB, RX1PA, RX1PB, RXBLOCKSYNC64B66BUSEA, RXBLOCKSYNC64B66BUSEB, RXCLKSTABLEA, RXCLKSTABLEB, RXCOMMADETUSEA, RXCOMMADETUSEB, RXCRCCLKA, RXCRCCLKB, RXCRCDATAVALIDA, RXCRCDATAVALIDB, RXCRCINITA +, RXCRCINITB, RXCRCINTCLKA, RXCRCINTCLKB, RXCRCPDA, RXCRCPDB, RXCRCRESETA, RXCRCRESETB, RXDEC64B66BUSEA, RXDEC64B66BUSEB, RXDEC8B10BUSEA, RXDEC8B10BUSEB, RXDESCRAM64B66BUSEA, RXDESCRAM64B66BUSEB, RXIGNOREBTFA, RXIGNOREBTFB, RXPMARESETA, RXPMARESETB, RXPOLARITYA, RXPOLARITYB, RXRESETA, RXRESETB +, RXSLIDEA, RXSLIDEB, RXSYNCA, RXSYNCB, RXUSRCLK2A, RXUSRCLK2B, RXUSRCLKA, RXUSRCLKB, TXCLKSTABLEA, TXCLKSTABLEB, TXCRCCLKA, TXCRCCLKB, TXCRCDATAVALIDA, TXCRCDATAVALIDB, TXCRCINITA, TXCRCINITB, TXCRCINTCLKA, TXCRCINTCLKB, TXCRCPDA, TXCRCPDB, TXCRCRESETA +, TXCRCRESETB, TXENC64B66BUSEA, TXENC64B66BUSEB, TXENC8B10BUSEA, TXENC8B10BUSEB, TXENOOBA, TXENOOBB, TXGEARBOX64B66BUSEA, TXGEARBOX64B66BUSEB, TXINHIBITA, TXINHIBITB, TXPMARESETA, TXPMARESETB, TXPOLARITYA, TXPOLARITYB, TXRESETA, TXRESETB, TXSCRAM64B66BUSEA, TXSCRAM64B66BUSEB, TXSYNCA, TXSYNCB +, TXUSRCLK2A, TXUSRCLK2B, TXUSRCLKA, TXUSRCLKB, DIA, DIB, LOOPBACKA, LOOPBACKB, RXDATAWIDTHA, RXDATAWIDTHB, RXINTDATAWIDTHA, RXINTDATAWIDTHB, TXDATAWIDTHA, TXDATAWIDTHB, TXINTDATAWIDTHA, TXINTDATAWIDTHB, RXCRCDATAWIDTHA, RXCRCDATAWIDTHB, TXCRCDATAWIDTHA, TXCRCDATAWIDTHB, CHBONDIA +, CHBONDIB, RXCRCINA, RXCRCINB, TXCRCINA, TXCRCINB, TXDATAA, TXDATAB, DADDRA, DADDRB, TXBYPASS8B10BA, TXBYPASS8B10BB, TXCHARDISPMODEA, TXCHARDISPMODEB, TXCHARDISPVALA, TXCHARDISPVALB, TXCHARISKA, TXCHARISKB); parameter ALIGN_COMMA_WORD_A = 1; parameter ALIGN_COMMA_WORD_B = 1; parameter BANDGAPSEL_A = "FALSE"; @@ -11601,7 +11670,7 @@ module GT11_DUAL (...); input [7:0] TXCHARISKB; endmodule -module GT11CLK (...); +module GT11CLK(SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP, REFCLK, RXBCLK, SYNCLK1IN, SYNCLK2IN); parameter REFCLKSEL = "MGTCLK"; parameter SYNCLK1OUTEN = "ENABLE"; parameter SYNCLK2OUTEN = "DISABLE"; @@ -11615,7 +11684,7 @@ module GT11CLK (...); input SYNCLK2IN; endmodule -module GT11CLK_MGT (...); +module GT11CLK_MGT(SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP); parameter SYNCLK1OUTEN = "ENABLE"; parameter SYNCLK2OUTEN = "DISABLE"; output SYNCLK1OUT; @@ -11624,7 +11693,15 @@ module GT11CLK_MGT (...); input MGTCLKP; endmodule -module GTP_DUAL (...); +module GTP_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCOMMADET0, RXCOMMADET1, RXELECIDLE0, RXELECIDLE1 +, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXVALID0, RXVALID1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, DO, RXDATA0, RXDATA1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1 +, RXDISPERR0, RXDISPERR1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXRUNDISP0, RXRUNDISP1, TXBUFSTATUS0, TXBUFSTATUS1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, RXBUFSTATUS0, RXBUFSTATUS1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXSTATUS0 +, RXSTATUS1, CLKIN, DCLK, DEN, DWE, GTPRESET, INTDATAWIDTH, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0 +, RXDEC8B10BUSE1, RXELECIDLERESET0, RXELECIDLERESET1, RXENCHANSYNC0, RXENCHANSYNC1, RXENELECIDLERESETB, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0 +, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1 +, TXENPMAPHASEALIGN, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE, TXPOLARITY0, TXPOLARITY1, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, DI, TXDATA0, TXDATA1, RXENPRBSTST0, RXENPRBSTST1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1 +, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXENPRBSTST0, TXENPRBSTST1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, RXCHBONDI0, RXCHBONDI1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXDIFFCTRL0, TXDIFFCTRL1, TXPREEMPHASIS0 +, TXPREEMPHASIS1, GTPTEST, RXEQPOLE0, RXEQPOLE1, DADDR); parameter AC_CAP_DIS_0 = "TRUE"; parameter AC_CAP_DIS_1 = "TRUE"; parameter CHAN_BOND_MODE_0 = "OFF"; @@ -11981,7 +12058,17 @@ module GTP_DUAL (...); input [6:0] DADDR; endmodule -module GTX_DUAL (...); +module GTX_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCOMMADET0, RXCOMMADET1, RXDATAVALID0, RXDATAVALID1 +, RXELECIDLE0, RXELECIDLE1, RXHEADERVALID0, RXHEADERVALID1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXSTARTOFSEQ0, RXSTARTOFSEQ1, RXVALID0, RXVALID1, TXGEARBOXREADY0, TXGEARBOXREADY1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0 +, TXP1, DO, RXLOSSOFSYNC0, RXLOSSOFSYNC1, TXBUFSTATUS0, TXBUFSTATUS1, DFESENSCAL0, DFESENSCAL1, RXBUFSTATUS0, RXBUFSTATUS1, RXCLKCORCNT0, RXCLKCORCNT1, RXHEADER0, RXHEADER1, RXSTATUS0, RXSTATUS1, RXDATA0, RXDATA1, DFETAP3MONITOR0, DFETAP3MONITOR1, DFETAP4MONITOR0 +, DFETAP4MONITOR1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXDISPERR0, RXDISPERR1, RXNOTINTABLE0, RXNOTINTABLE1, RXRUNDISP0, RXRUNDISP1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, DFEEYEDACMONITOR0, DFEEYEDACMONITOR1, DFETAP1MONITOR0, DFETAP1MONITOR1 +, DFETAP2MONITOR0, DFETAP2MONITOR1, DFECLKDLYADJMONITOR0, DFECLKDLYADJMONITOR1, CLKIN, DCLK, DEN, DWE, GTXRESET, INTDATAWIDTH, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCOMMADETUSE0, RXCOMMADETUSE1 +, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXGEARBOXSLIP0, RXGEARBOXSLIP1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0 +, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1 +, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXRESET0, TXRESET1, TXSTARTSEQ0, TXSTARTSEQ1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, GTXTEST, DI, RXDATAWIDTH0, RXDATAWIDTH1, RXENPRBSTST0 +, RXENPRBSTST1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1, TXDATAWIDTH0, TXDATAWIDTH1, TXENPRBSTST0, TXENPRBSTST1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXDIFFCTRL0, TXDIFFCTRL1, TXHEADER0, TXHEADER1, TXDATA0, TXDATA1 +, DFETAP30, DFETAP31, DFETAP40, DFETAP41, RXCHBONDI0, RXCHBONDI1, RXEQPOLE0, RXEQPOLE1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXPREEMPHASIS0, TXPREEMPHASIS1, DFETAP10, DFETAP11, DFETAP20 +, DFETAP21, DFECLKDLYADJ0, DFECLKDLYADJ1, DADDR, TXSEQUENCE0, TXSEQUENCE1); parameter STEPPING = "0"; parameter AC_CAP_DIS_0 = "TRUE"; parameter AC_CAP_DIS_1 = "TRUE"; @@ -12417,7 +12504,7 @@ module GTX_DUAL (...); input [6:0] TXSEQUENCE1; endmodule -module CRC32 (...); +module CRC32(CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET); parameter CRC_INIT = 32'hFFFFFFFF; output [31:0] CRCOUT; (* clkbuf_sink *) @@ -12428,7 +12515,7 @@ module CRC32 (...); input CRCRESET; endmodule -module CRC64 (...); +module CRC64(CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET); parameter CRC_INIT = 32'hFFFFFFFF; output [31:0] CRCOUT; (* clkbuf_sink *) @@ -12439,7 +12526,15 @@ module CRC64 (...); input CRCRESET; endmodule -module GTHE1_QUAD (...); +module GTHE1_QUAD(DRDY, GTHINITDONE, MGMTPCSRDACK, RXCTRLACK0, RXCTRLACK1, RXCTRLACK2, RXCTRLACK3, RXDATATAP0, RXDATATAP1, RXDATATAP2, RXDATATAP3, RXPCSCLKSMPL0, RXPCSCLKSMPL1, RXPCSCLKSMPL2, RXPCSCLKSMPL3, RXUSERCLKOUT0, RXUSERCLKOUT1, RXUSERCLKOUT2, RXUSERCLKOUT3, TSTPATH, TSTREFCLKFAB +, TSTREFCLKOUT, TXCTRLACK0, TXCTRLACK1, TXCTRLACK2, TXCTRLACK3, TXDATATAP10, TXDATATAP11, TXDATATAP12, TXDATATAP13, TXDATATAP20, TXDATATAP21, TXDATATAP22, TXDATATAP23, TXN0, TXN1, TXN2, TXN3, TXP0, TXP1, TXP2, TXP3 +, TXPCSCLKSMPL0, TXPCSCLKSMPL1, TXPCSCLKSMPL2, TXPCSCLKSMPL3, TXUSERCLKOUT0, TXUSERCLKOUT1, TXUSERCLKOUT2, TXUSERCLKOUT3, DRPDO, MGMTPCSRDDATA, RXDATA0, RXDATA1, RXDATA2, RXDATA3, RXCODEERR0, RXCODEERR1, RXCODEERR2, RXCODEERR3, RXCTRL0, RXCTRL1, RXCTRL2 +, RXCTRL3, RXDISPERR0, RXDISPERR1, RXDISPERR2, RXDISPERR3, RXVALID0, RXVALID1, RXVALID2, RXVALID3, DCLK, DEN, DFETRAINCTRL0, DFETRAINCTRL1, DFETRAINCTRL2, DFETRAINCTRL3, DISABLEDRP, DWE, GTHINIT, GTHRESET, GTHX2LANE01, GTHX2LANE23 +, GTHX4LANE, MGMTPCSREGRD, MGMTPCSREGWR, POWERDOWN0, POWERDOWN1, POWERDOWN2, POWERDOWN3, REFCLK, RXBUFRESET0, RXBUFRESET1, RXBUFRESET2, RXBUFRESET3, RXENCOMMADET0, RXENCOMMADET1, RXENCOMMADET2, RXENCOMMADET3, RXN0, RXN1, RXN2, RXN3, RXP0 +, RXP1, RXP2, RXP3, RXPOLARITY0, RXPOLARITY1, RXPOLARITY2, RXPOLARITY3, RXSLIP0, RXSLIP1, RXSLIP2, RXSLIP3, RXUSERCLKIN0, RXUSERCLKIN1, RXUSERCLKIN2, RXUSERCLKIN3, TXBUFRESET0, TXBUFRESET1, TXBUFRESET2, TXBUFRESET3, TXDEEMPH0, TXDEEMPH1 +, TXDEEMPH2, TXDEEMPH3, TXUSERCLKIN0, TXUSERCLKIN1, TXUSERCLKIN2, TXUSERCLKIN3, DADDR, DI, MGMTPCSREGADDR, MGMTPCSWRDATA, RXPOWERDOWN0, RXPOWERDOWN1, RXPOWERDOWN2, RXPOWERDOWN3, RXRATE0, RXRATE1, RXRATE2, RXRATE3, TXPOWERDOWN0, TXPOWERDOWN1, TXPOWERDOWN2 +, TXPOWERDOWN3, TXRATE0, TXRATE1, TXRATE2, TXRATE3, PLLREFCLKSEL, SAMPLERATE0, SAMPLERATE1, SAMPLERATE2, SAMPLERATE3, TXMARGIN0, TXMARGIN1, TXMARGIN2, TXMARGIN3, MGMTPCSLANESEL, MGMTPCSMMDADDR, PLLPCSCLKDIV, TXDATA0, TXDATA1, TXDATA2, TXDATA3 +, TXCTRL0, TXCTRL1, TXCTRL2, TXCTRL3, TXDATAMSB0, TXDATAMSB1, TXDATAMSB2, TXDATAMSB3); parameter [15:0] BER_CONST_PTRN0 = 16'h0000; parameter [15:0] BER_CONST_PTRN1 = 16'h0000; parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; @@ -12907,7 +13002,15 @@ module GTHE1_QUAD (...); input [7:0] TXDATAMSB3; endmodule -module GTXE1 (...); +module GTXE1(COMFINISH, COMINITDET, COMSASDET, COMWAKEDET, DRDY, PHYSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMMADET, RXDATAVALID, RXELECIDLE, RXHEADERVALID, RXOVERSAMPLEERR, RXPLLLKDET, RXPRBSERR, RXRATEDONE, RXRECCLK, RXRECCLKPCS +, RXRESETDONE, RXSTARTOFSEQ, RXVALID, TXGEARBOXREADY, TXN, TXOUTCLK, TXOUTCLKPCS, TXP, TXPLLLKDET, TXRATEDONE, TXRESETDONE, DRPDO, MGTREFCLKFAB, RXLOSSOFSYNC, TXBUFSTATUS, DFESENSCAL, RXBUFSTATUS, RXCLKCORCNT, RXHEADER, RXSTATUS, RXDATA +, DFETAP3MONITOR, DFETAP4MONITOR, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXDISPERR, RXNOTINTABLE, RXRUNDISP, TXKERR, TXRUNDISP, DFEEYEDACMON, DFETAP1MONITOR, DFETAP2MONITOR, DFECLKDLYADJMON, RXDLYALIGNMONITOR, TXDLYALIGNMONITOR, TSTOUT, DCLK, DEN, DFEDLYOVRD, DFETAPOVRD +, DWE, GATERXELECIDLE, GREFCLKRX, GREFCLKTX, GTXRXRESET, GTXTXRESET, IGNORESIGDET, PERFCLKRX, PERFCLKTX, PLLRXRESET, PLLTXRESET, PRBSCNTRESET, RXBUFRESET, RXCDRRESET, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETUSE, RXDEC8B10BUSE, RXDLYALIGNDISABLE, RXDLYALIGNMONENB, RXDLYALIGNOVERRIDE +, RXDLYALIGNRESET, RXDLYALIGNSWPPRECURB, RXDLYALIGNUPDSW, RXENCHANSYNC, RXENMCOMMAALIGN, RXENPCOMMAALIGN, RXENPMAPHASEALIGN, RXENSAMPLEALIGN, RXGEARBOXSLIP, RXN, RXP, RXPLLLKDETEN, RXPLLPOWERDOWN, RXPMASETPHASE, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK2, RXUSRCLK, TSTCLK0, TSTCLK1 +, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDLYALIGNDISABLE, TXDLYALIGNMONENB, TXDLYALIGNOVERRIDE, TXDLYALIGNRESET, TXDLYALIGNUPDSW, TXELECIDLE, TXENC8B10BUSE, TXENPMAPHASEALIGN, TXINHIBIT, TXPDOWNASYNCH, TXPLLLKDETEN, TXPLLPOWERDOWN, TXPMASETPHASE, TXPOLARITY, TXPRBSFORCEERR, TXRESET +, TXSTARTSEQ, TXSWING, TXUSRCLK2, TXUSRCLK, USRCODEERR, GTXTEST, DI, TSTIN, MGTREFCLKRX, MGTREFCLKTX, NORTHREFCLKRX, NORTHREFCLKTX, RXPOWERDOWN, RXRATE, SOUTHREFCLKRX, SOUTHREFCLKTX, TXPOWERDOWN, TXRATE, LOOPBACK, RXCHBONDLEVEL, RXENPRBSTST +, RXPLLREFSELDY, TXBUFDIFFCTRL, TXENPRBSTST, TXHEADER, TXMARGIN, TXPLLREFSELDY, TXDATA, DFETAP3, DFETAP4, RXCHBONDI, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDIFFCTRL, TXPREEMPHASIS, DFETAP1, DFETAP2, TXPOSTEMPHASIS, DFECLKDLYADJ, TXSEQUENCE +, DADDR, RXEQMIX); parameter AC_CAP_DIS = "TRUE"; parameter integer ALIGN_COMMA_WORD = 1; parameter [1:0] BGTEST_CFG = 2'b00; @@ -13259,7 +13362,7 @@ module GTXE1 (...); input [9:0] RXEQMIX; endmodule -module IBUFDS_GTXE1 (...); +module IBUFDS_GTXE1(O, ODIV2, CEB, I, IB); parameter CLKCM_CFG = "TRUE"; parameter CLKRCV_TRST = "TRUE"; parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; @@ -13272,7 +13375,7 @@ module IBUFDS_GTXE1 (...); input IB; endmodule -module IBUFDS_GTHE1 (...); +module IBUFDS_GTHE1(O, I, IB); output O; (* iopad_external_pin *) input I; @@ -13280,7 +13383,20 @@ module IBUFDS_GTHE1 (...); input IB; endmodule -module GTHE2_CHANNEL (...); +module GTHE2_CHANNEL(CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTREFCLKMONITOR, PHYSTATUS, RSOSINTDONE, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDFESLIDETAPSTARTED +, RXDFESLIDETAPSTROBEDONE, RXDFESLIDETAPSTROBESTARTED, RXDFESTADAPTDONE, RXDLYSRESETDONE, RXELECIDLE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPMARESETDONE, RXPRBSERR, RXQPISENN, RXQPISENP, RXRATEDONE, RXRESETDONE, RXSYNCDONE, RXSYNCOUT, RXVALID +, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, DMONITOROUT, DRPDO, PCSRSVDOUT, RXCLKCORCNT, RXDATAVALID, RXHEADERVALID +, RXSTARTOFSEQ, TXBUFSTATUS, RXBUFSTATUS, RXSTATUS, RXCHBONDO, RXPHMONITOR, RXPHSLIPMONITOR, RXHEADER, RXDATA, RXMONITOROUT, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLRESET +, DMONFIFORESET, DMONITORCLK, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, QPLLCLK +, QPLLREFCLK, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECM1EN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFESLIDETAPADAPTEN +, RXDFESLIDETAPHOLD, RXDFESLIDETAPINITOVRDEN, RXDFESLIDETAPONLYADAPTEN, RXDFESLIDETAPOVRDEN, RXDFESLIDETAPSTROBE, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN +, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTEN, RXOSINTHOLD, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTSTROBE +, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXQPIEN, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXUSERRDY, RXUSRCLK2, RXUSRCLK +, SETERRSTATUS, SIGVALIDCLK, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN +, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXRATEMODE, TXSTARTSEQ, TXSWING +, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXUSERRDY, TXUSRCLK2, TXUSRCLK, RXADAPTSELTEST, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXMONITORSEL, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, CPLLREFCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL +, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER, TXMARGIN, TXOUTCLKSEL, TXPRBSSEL, TXRATE, RXOSINTCFG, RXOSINTID0, TXDIFFCTRL, PCSRSVDIN2, PMARSVDIN, RXCHBONDI, RXDFEAGCTRL, RXDFESLIDETAP, TXPIPPMSTEPSIZE, TXPOSTCURSOR, TXPRECURSOR, RXDFESLIDETAPID, TXDATA +, TXMAINCURSOR, TXSEQUENCE, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, DRPADDR); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -13843,7 +13959,8 @@ module GTHE2_CHANNEL (...); input [8:0] DRPADDR; endmodule -module GTHE2_COMMON (...); +module GTHE2_COMMON(DRPRDY, QPLLFBCLKLOST, QPLLLOCK, QPLLOUTCLK, QPLLOUTREFCLK, QPLLREFCLKLOST, REFCLKOUTMONITOR, DRPDO, PMARSVDOUT, QPLLDMONITOR, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRDENB, DRPCLK, DRPEN, DRPWE, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0 +, GTREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1, QPLLLOCKDETCLK, QPLLLOCKEN, QPLLOUTRESET, QPLLPD, QPLLRESET, RCALENB, DRPDI, QPLLRSVD1, QPLLREFCLKSEL, BGRCALOVRD, QPLLRSVD2, DRPADDR, PMARSVD); parameter [63:0] BIAS_CFG = 64'h0000040000001000; parameter [31:0] COMMON_CFG = 32'h0000001C; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; @@ -13913,7 +14030,17 @@ module GTHE2_COMMON (...); input [7:0] PMARSVD; endmodule -module GTPE2_CHANNEL (...); +module GTPE2_CHANNEL(DRPRDY, EYESCANDATAERROR, GTPTXN, GTPTXP, PHYSTATUS, PMARSVDOUT0, PMARSVDOUT1, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDLYSRESETDONE, RXELECIDLE, RXHEADERVALID, RXOSINTDONE +, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPMARESETDONE, RXPRBSERR, RXRATEDONE, RXRESETDONE, RXSYNCDONE, RXSYNCOUT, RXVALID, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE +, TXPHINITDONE, TXPMARESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, DMONITOROUT, DRPDO, PCSRSVDOUT, RXCLKCORCNT, RXDATAVALID, RXSTARTOFSEQ, TXBUFSTATUS, RXBUFSTATUS, RXHEADER, RXSTATUS, RXDATA, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXDISPERR +, RXNOTINTABLE, RXPHMONITOR, RXPHSLIPMONITOR, CFGRESET, CLKRSVD0, CLKRSVD1, DMONFIFORESET, DMONITORCLK, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTPRXN, GTPRXP, GTRESETSEL, GTRXRESET, GTTXRESET, PLL0CLK, PLL0REFCLK +, PLL1CLK, PLL1REFCLK, PMARSVDIN0, PMARSVDIN1, PMARSVDIN2, PMARSVDIN3, PMARSVDIN4, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEXYDEN +, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFOVRDEN, RXLPMOSINTNTRLEN, RXLPMRESET, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTEN, RXOSINTHOLD, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTPD, RXOSINTSTROBE +, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXUSERRDY, RXUSRCLK2, RXUSRCLK, SETERRSTATUS +, SIGVALIDCLK, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD +, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXRATEMODE, TXSTARTSEQ, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXUSERRDY +, TXUSRCLK2, TXUSRCLK, RXADAPTSELTEST, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER, TXMARGIN, TXOUTCLKSEL +, TXPRBSSEL, TXRATE, TXDATA, RXCHBONDI, RXOSINTCFG, RXOSINTID0, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDIFFCTRL, TXPIPPMSTEPSIZE, TXPOSTCURSOR, TXPRECURSOR, TXMAINCURSOR, TXSEQUENCE, DRPADDR); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -14395,7 +14522,9 @@ module GTPE2_CHANNEL (...); input [8:0] DRPADDR; endmodule -module GTPE2_COMMON (...); +module GTPE2_COMMON(DRPRDY, PLL0FBCLKLOST, PLL0LOCK, PLL0OUTCLK, PLL0OUTREFCLK, PLL0REFCLKLOST, PLL1FBCLKLOST, PLL1LOCK, PLL1OUTCLK, PLL1OUTREFCLK, PLL1REFCLKLOST, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, DRPDO, PMARSVDOUT, DMONITOROUT, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRDENB, DRPCLK +, DRPEN, DRPWE, GTEASTREFCLK0, GTEASTREFCLK1, GTGREFCLK0, GTGREFCLK1, GTREFCLK0, GTREFCLK1, GTWESTREFCLK0, GTWESTREFCLK1, PLL0LOCKDETCLK, PLL0LOCKEN, PLL0PD, PLL0RESET, PLL1LOCKDETCLK, PLL1LOCKEN, PLL1PD, PLL1RESET, RCALENB, DRPDI, PLLRSVD1 +, PLL0REFCLKSEL, PLL1REFCLKSEL, BGRCALOVRD, PLLRSVD2, DRPADDR, PMARSVD); parameter [63:0] BIAS_CFG = 64'h0000000000000000; parameter [31:0] COMMON_CFG = 32'h00000000; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; @@ -14479,7 +14608,17 @@ module GTPE2_COMMON (...); input [7:0] PMARSVD; endmodule -module GTXE2_CHANNEL (...); +module GTXE2_CHANNEL(CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DRPRDY, EYESCANDATAERROR, GTREFCLKMONITOR, GTXTXN, GTXTXP, PHYSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDATAVALID, RXDLYSRESETDONE +, RXELECIDLE, RXHEADERVALID, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPRBSERR, RXQPISENN, RXQPISENP, RXRATEDONE, RXRESETDONE, RXSTARTOFSEQ, RXVALID, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE +, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, DRPDO, PCSRSVDOUT, RXCLKCORCNT, TXBUFSTATUS, RXBUFSTATUS, RXHEADER, RXSTATUS, RXCHBONDO, RXPHMONITOR, RXPHSLIPMONITOR, RXDATA, RXMONITOROUT, DMONITOROUT, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE +, TSTOUT, CFGRESET, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLRESET, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1 +, GTTXRESET, GTXRXN, GTXRXP, QPLLCLK, QPLLREFCLK, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECM1EN +, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDFEXYDHOLD, RXDFEXYDOVRDEN, RXDLYBYPASS, RXDLYEN +, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXMCOMMAALIGNEN, RXOOBRESET, RXOSHOLD, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY +, RXPRBSCNTRESET, RXQPIEN, RXSLIDE, RXUSERRDY, RXUSRCLK2, RXUSRCLK, SETERRSTATUS, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE +, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXSTARTSEQ, TXSWING +, TXUSERRDY, TXUSRCLK2, TXUSRCLK, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXMONITORSEL, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, CPLLREFCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER +, TXMARGIN, TXOUTCLKSEL, TXPRBSSEL, TXRATE, CLKRSVD, TXDIFFCTRL, PCSRSVDIN2, PMARSVDIN2, PMARSVDIN, RXCHBONDI, TXPOSTCURSOR, TXPRECURSOR, TXDATA, TXMAINCURSOR, TXSEQUENCE, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, DRPADDR); parameter ALIGN_COMMA_DOUBLE = "FALSE"; parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; parameter integer ALIGN_COMMA_WORD = 1; @@ -14927,7 +15066,8 @@ module GTXE2_CHANNEL (...); input [8:0] DRPADDR; endmodule -module GTXE2_COMMON (...); +module GTXE2_COMMON(DRPRDY, QPLLFBCLKLOST, QPLLLOCK, QPLLOUTCLK, QPLLOUTREFCLK, QPLLREFCLKLOST, REFCLKOUTMONITOR, DRPDO, QPLLDMONITOR, BGBYPASSB, BGMONITORENB, BGPDB, DRPCLK, DRPEN, DRPWE, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTSOUTHREFCLK0 +, GTSOUTHREFCLK1, QPLLLOCKDETCLK, QPLLLOCKEN, QPLLOUTRESET, QPLLPD, QPLLRESET, RCALENB, DRPDI, QPLLRSVD1, QPLLREFCLKSEL, BGRCALOVRD, QPLLRSVD2, DRPADDR, PMARSVD); parameter [63:0] BIAS_CFG = 64'h0000040000001000; parameter [31:0] COMMON_CFG = 32'h00000000; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; @@ -14990,7 +15130,7 @@ module GTXE2_COMMON (...); input [7:0] PMARSVD; endmodule -module IBUFDS_GTE2 (...); +module IBUFDS_GTE2(O, ODIV2, CEB, I, IB); parameter CLKCM_CFG = "TRUE"; parameter CLKRCV_TRST = "TRUE"; parameter CLKSWING_CFG = "TRUE"; @@ -15003,7 +15143,22 @@ module IBUFDS_GTE2 (...); input IB; endmodule -module GTHE3_CHANNEL (...); +module GTHE3_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTPOWERGOOD, GTREFCLKMONITOR, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET, PCIESYNCTXSYNCDONE +, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET +, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR +, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXQPISENN, RXQPISENP, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDLYSRESETDONE +, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET +, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, EVODDPHICALDONE, EVODDPHICALSTART, EVODDPHIDRDEN, EVODDPHIDWREN, EVODDPHIXRDEN, EVODDPHIXWREN, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1 +, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRSVD, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, LOOPBACK, LPBKRXTXSEREN, LPBKTXRXSEREN, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, PCSRSVDIN2, PMARSVDIN, QPLL0CLK, QPLL0REFCLK, QPLL1CLK +, QPLL1REFCLK, RESETOVRD, RSTCLKENTX, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDFEAGCCTRL, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN +, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN +, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLATCLK +, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN, RXOSINTHOLD, RXOSINTOVRDEN, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN +, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXQPIEN, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA +, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDEEMPH +, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXLATCLK, TXMAINCURSOR, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN +, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPRECURSORINV, TXPROGDIVRESET +, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -15723,7 +15878,10 @@ module GTHE3_CHANNEL (...); input TXUSRCLK2; endmodule -module GTHE3_COMMON (...); +module GTHE3_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0_SEL, RXRECCLK1_SEL, BGBYPASSB +, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01 +, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1CLKRSVD1, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3 +, QPLLRSVD4, RCALENB); parameter [15:0] BIAS_CFG0 = 16'h0000; parameter [15:0] BIAS_CFG1 = 16'h0000; parameter [15:0] BIAS_CFG2 = 16'h0000; @@ -15865,7 +16023,22 @@ module GTHE3_COMMON (...); input RCALENB; endmodule -module GTYE3_CHANNEL (...); +module GTYE3_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTPOWERGOOD, GTREFCLKMONITOR, GTYTXN, GTYTXP, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET, PCIESYNCTXSYNCDONE +, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET +, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE +, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE +, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL +, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, ELPCALDVORWREN, ELPCALPAORWREN, EVODDPHICALDONE, EVODDPHICALSTART, EVODDPHIDRDEN, EVODDPHIDWREN, EVODDPHIXRDEN, EVODDPHIXWREN, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTNORTHREFCLK0 +, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRSVD, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTYRXN, GTYRXP, LOOPBACK, LOOPRSVD, LPBKRXTXSEREN, LPBKTXRXSEREN, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, PCSRSVDIN2 +, PMARSVDIN, QPLL0CLK, QPLL0REFCLK, QPLL1CLK, QPLL1REFCLK, RESETOVRD, RSTCLKENTX, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET, RXCOMMADETEN +, RXDCCFORCESTART, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD +, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN +, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN +, RXOSINTHOLD, RXOSINTOVRDEN, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXRATE +, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1 +, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXELFORCESTART, TXHEADER, TXINHIBIT, TXLATCLK, TXMAINCURSOR +, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY +, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -16666,7 +16839,10 @@ module GTYE3_CHANNEL (...); input TXUSRCLK2; endmodule -module GTYE3_COMMON (...); +module GTYE3_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0_SEL, RXRECCLK1_SEL, SDM0FINALOUT +, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01 +, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1 +, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0WIDTH, SDM1DATA, SDM1RESET, SDM1WIDTH); parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; parameter [15:0] BIAS_CFG0 = 16'h0000; @@ -16814,7 +16990,7 @@ module GTYE3_COMMON (...); input [1:0] SDM1WIDTH; endmodule -module IBUFDS_GTE3 (...); +module IBUFDS_GTE3(O, ODIV2, CEB, I, IB); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; parameter [1:0] REFCLK_ICNTL_RX = 2'b00; @@ -16827,7 +17003,7 @@ module IBUFDS_GTE3 (...); input IB; endmodule -module OBUFDS_GTE3 (...); +module OBUFDS_GTE3(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -16838,7 +17014,7 @@ module OBUFDS_GTE3 (...); input I; endmodule -module OBUFDS_GTE3_ADV (...); +module OBUFDS_GTE3_ADV(O, OB, CEB, I, RXRECCLK_SEL); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -16850,7 +17026,23 @@ module OBUFDS_GTE3_ADV (...); input [1:0] RXRECCLK_SEL; endmodule -module GTHE4_CHANNEL (...); +module GTHE4_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DMONITOROUTCLK, DRPDO, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTPOWERGOOD, GTREFCLKMONITOR, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET +, PCIESYNCTXSYNCDONE, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, POWERPRESENT, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET +, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXLFPSTRESETDET, RXLFPSU2LPEXITDET, RXLFPSU3WAKEDET, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE +, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXQPISENN, RXQPISENP, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS +, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR +, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLFREQLOCK, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, EYESCANRESET, EYESCANTRIGGER +, FREQOS, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRSVD, GTRXRESET, GTRXRESETSEL, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTTXRESETSEL, INCPCTRL, LOOPBACK, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE +, PCSRSVDIN, QPLL0CLK, QPLL0FREQLOCK, QPLL0REFCLK, QPLL1CLK, QPLL1FREQLOCK, QPLL1REFCLK, RESETOVRD, RX8B10BEN, RXAFECFOKEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET +, RXCKCALSTART, RXCOMMADETEN, RXDFEAGCCTRL, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECFOKFCNUM, RXDFECFOKFEN, RXDFECFOKFPULSE, RXDFECFOKHOLD, RXDFECFOKOVREN, RXDFEKHHOLD, RXDFEKHOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN +, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD +, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXEQTRAINING, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN +, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET +, RXPRBSSEL, RXPROGDIVRESET, RXQPIEN, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXTERMINATION, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXCOMINIT +, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT +, TXLATCLK, TXLFPSTRESET, TXLFPSU2LPEXIT, TXLFPSU3WAKE, TXMAINCURSOR, TXMARGIN, TXMUXDCDEXHOLD, TXMUXDCDORWREN, TXONESZEROS, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN +, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXQPIBIASEN, TXQPIWEAKPUP, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN +, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -17698,7 +17890,11 @@ module GTHE4_CHANNEL (...); input TXUSRCLK2; endmodule -module GTHE4_COMMON (...); +module GTHE4_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0SEL, RXRECCLK1SEL, SDM0FINALOUT +, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, TCONGPO, TCONRSVDOUT0, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11 +, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PCIERATEQPLL0, PCIERATEQPLL1, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0FBDIV, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0 +, QPLL1CLKRSVD1, QPLL1FBDIV, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0TOGGLE, SDM0WIDTH, SDM1DATA, SDM1RESET, SDM1TOGGLE, SDM1WIDTH, TCONGPI +, TCONPOWERUP, TCONRESET, TCONRSVDIN1); parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; parameter [0:0] AEN_SDM0TOGGLE = 1'b0; @@ -17870,7 +18066,22 @@ module GTHE4_COMMON (...); input [1:0] TCONRSVDIN1; endmodule -module GTYE4_CHANNEL (...); +module GTYE4_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DMONITOROUTCLK, DRPDO, DRPRDY, EYESCANDATAERROR, GTPOWERGOOD, GTREFCLKMONITOR, GTYTXN, GTYTXP, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET +, PCIESYNCTXSYNCDONE, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, POWERPRESENT, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET +, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXLFPSTRESETDET, RXLFPSU2LPEXITDET, RXLFPSU3WAKEDET, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE +, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT +, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0 +, CLKRSVD1, CPLLFREQLOCK, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, EYESCANRESET, EYESCANTRIGGER, FREQOS, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1 +, GTREFCLK0, GTREFCLK1, GTRSVD, GTRXRESET, GTRXRESETSEL, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTTXRESETSEL, GTYRXN, GTYRXP, INCPCTRL, LOOPBACK, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, QPLL0CLK, QPLL0FREQLOCK, QPLL0REFCLK +, QPLL1CLK, QPLL1FREQLOCK, QPLL1REFCLK, RESETOVRD, RX8B10BEN, RXAFECFOKEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET, RXCKCALSTART, RXCOMMADETEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN +, RXDFECFOKFCNUM, RXDFECFOKFEN, RXDFECFOKFPULSE, RXDFECFOKHOLD, RXDFECFOKOVREN, RXDFEKHHOLD, RXDFEKHOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD +, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN +, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXEQTRAINING, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET +, RXOSCALRESET, RXOSHOLD, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK +, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXTERMINATION, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD +, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXLATCLK, TXLFPSTRESET, TXLFPSU2LPEXIT, TXLFPSU3WAKE, TXMAINCURSOR, TXMARGIN, TXMUXDCDEXHOLD +, TXMUXDCDORWREN, TXONESZEROS, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET +, TXPOLARITY, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; @@ -18696,7 +18907,11 @@ module GTYE4_CHANNEL (...); input TXUSRCLK2; endmodule -module GTYE4_COMMON (...); +module GTYE4_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0SEL, RXRECCLK1SEL, SDM0FINALOUT +, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, UBDADDR, UBDEN, UBDI, UBDWE, UBMDMTDO, UBRSVDOUT, UBTXUART, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0 +, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PCIERATEQPLL0, PCIERATEQPLL1, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0FBDIV, QPLL0LOCKDETCLK +, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1CLKRSVD1, QPLL1FBDIV, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0TOGGLE, SDM0WIDTH +, SDM1DATA, SDM1RESET, SDM1TOGGLE, SDM1WIDTH, UBCFGSTREAMEN, UBDO, UBDRDY, UBENABLE, UBGPI, UBINTR, UBIOLMBRST, UBMBRST, UBMDMCAPTURE, UBMDMDBGRST, UBMDMDBGUPDATE, UBMDMREGEN, UBMDMSHIFT, UBMDMSYSRST, UBMDMTCK, UBMDMTDI); parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; parameter [0:0] AEN_SDM0TOGGLE = 1'b0; @@ -18892,7 +19107,7 @@ module GTYE4_COMMON (...); input UBMDMTDI; endmodule -module IBUFDS_GTE4 (...); +module IBUFDS_GTE4(O, ODIV2, CEB, I, IB); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; parameter [1:0] REFCLK_ICNTL_RX = 2'b00; @@ -18905,7 +19120,7 @@ module IBUFDS_GTE4 (...); input IB; endmodule -module OBUFDS_GTE4 (...); +module OBUFDS_GTE4(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -18916,7 +19131,7 @@ module OBUFDS_GTE4 (...); input I; endmodule -module OBUFDS_GTE4_ADV (...); +module OBUFDS_GTE4_ADV(O, OB, CEB, I, RXRECCLK_SEL); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -18928,7 +19143,20 @@ module OBUFDS_GTE4_ADV (...); input [1:0] RXRECCLK_SEL; endmodule -module GTM_DUAL (...); +module GTM_DUAL(CH0_AXISTDATA, CH0_AXISTLAST, CH0_AXISTVALID, CH0_DMONITOROUT, CH0_DMONITOROUTCLK, CH0_GTMTXN, CH0_GTMTXP, CH0_PCSRSVDOUT, CH0_PMARSVDOUT, CH0_RESETEXCEPTION, CH0_RXBUFSTATUS, CH0_RXDATA, CH0_RXDATAFLAGS, CH0_RXDATAISAM, CH0_RXDATASTART, CH0_RXOUTCLK, CH0_RXPMARESETDONE, CH0_RXPRBSERR, CH0_RXPRBSLOCKED, CH0_RXPRGDIVRESETDONE, CH0_RXPROGDIVCLK +, CH0_RXRESETDONE, CH0_TXBUFSTATUS, CH0_TXOUTCLK, CH0_TXPMARESETDONE, CH0_TXPRGDIVRESETDONE, CH0_TXPROGDIVCLK, CH0_TXRESETDONE, CH1_AXISTDATA, CH1_AXISTLAST, CH1_AXISTVALID, CH1_DMONITOROUT, CH1_DMONITOROUTCLK, CH1_GTMTXN, CH1_GTMTXP, CH1_PCSRSVDOUT, CH1_PMARSVDOUT, CH1_RESETEXCEPTION, CH1_RXBUFSTATUS, CH1_RXDATA, CH1_RXDATAFLAGS, CH1_RXDATAISAM +, CH1_RXDATASTART, CH1_RXOUTCLK, CH1_RXPMARESETDONE, CH1_RXPRBSERR, CH1_RXPRBSLOCKED, CH1_RXPRGDIVRESETDONE, CH1_RXPROGDIVCLK, CH1_RXRESETDONE, CH1_TXBUFSTATUS, CH1_TXOUTCLK, CH1_TXPMARESETDONE, CH1_TXPRGDIVRESETDONE, CH1_TXPROGDIVCLK, CH1_TXRESETDONE, CLKTESTSIG2PAD, DMONITOROUTPLLCLK, DRPDO, DRPRDY, FECRX0ALIGNED, FECRX0CORRCWINC, FECRX0CWINC +, FECRX0UNCORRCWINC, FECRX1ALIGNED, FECRX1CORRCWINC, FECRX1CWINC, FECRX1UNCORRCWINC, FECRXLN0BITERR0TO1INC, FECRXLN0BITERR1TO0INC, FECRXLN0DLY, FECRXLN0ERRCNTINC, FECRXLN0MAPPING, FECRXLN1BITERR0TO1INC, FECRXLN1BITERR1TO0INC, FECRXLN1DLY, FECRXLN1ERRCNTINC, FECRXLN1MAPPING, FECRXLN2BITERR0TO1INC, FECRXLN2BITERR1TO0INC, FECRXLN2DLY, FECRXLN2ERRCNTINC, FECRXLN2MAPPING, FECRXLN3BITERR0TO1INC +, FECRXLN3BITERR1TO0INC, FECRXLN3DLY, FECRXLN3ERRCNTINC, FECRXLN3MAPPING, FECTRXLN0LOCK, FECTRXLN1LOCK, FECTRXLN2LOCK, FECTRXLN3LOCK, GTPOWERGOOD, PLLFBCLKLOST, PLLLOCK, PLLREFCLKLOST, PLLREFCLKMONITOR, PLLRESETDONE, PLLRSVDOUT, RCALCMP, RCALOUT, RXRECCLK0, RXRECCLK1, BGBYPASSB, BGMONITORENB +, BGPDB, BGRCALOVRD, BGRCALOVRDENB, CH0_AXISEN, CH0_AXISRST, CH0_AXISTRDY, CH0_CFGRESET, CH0_DMONFIFORESET, CH0_DMONITORCLK, CH0_GTMRXN, CH0_GTMRXP, CH0_GTRXRESET, CH0_GTTXRESET, CH0_LOOPBACK, CH0_PCSRSVDIN, CH0_PMARSVDIN, CH0_RESETOVRD, CH0_RXADAPTRESET, CH0_RXADCCALRESET, CH0_RXADCCLKGENRESET, CH0_RXBUFRESET +, CH0_RXCDRFREQOS, CH0_RXCDRFRRESET, CH0_RXCDRHOLD, CH0_RXCDRINCPCTRL, CH0_RXCDROVRDEN, CH0_RXCDRPHRESET, CH0_RXDFERESET, CH0_RXDSPRESET, CH0_RXEQTRAINING, CH0_RXEYESCANRESET, CH0_RXFECRESET, CH0_RXOUTCLKSEL, CH0_RXPCSRESET, CH0_RXPCSRESETMASK, CH0_RXPMARESET, CH0_RXPMARESETMASK, CH0_RXPOLARITY, CH0_RXPRBSCNTSTOP, CH0_RXPRBSCSCNTRST, CH0_RXPRBSPTN, CH0_RXPROGDIVRESET +, CH0_RXQPRBSEN, CH0_RXRESETMODE, CH0_RXSPCSEQADV, CH0_RXUSRCLK, CH0_RXUSRCLK2, CH0_RXUSRRDY, CH0_RXUSRSTART, CH0_RXUSRSTOP, CH0_TXCKALRESET, CH0_TXCTLFIRDAT, CH0_TXDATA, CH0_TXDATASTART, CH0_TXDRVAMP, CH0_TXEMPMAIN, CH0_TXEMPPOST, CH0_TXEMPPRE, CH0_TXEMPPRE2, CH0_TXFECRESET, CH0_TXINHIBIT, CH0_TXMUXDCDEXHOLD, CH0_TXMUXDCDORWREN +, CH0_TXOUTCLKSEL, CH0_TXPCSRESET, CH0_TXPCSRESETMASK, CH0_TXPMARESET, CH0_TXPMARESETMASK, CH0_TXPOLARITY, CH0_TXPRBSINERR, CH0_TXPRBSPTN, CH0_TXPROGDIVRESET, CH0_TXQPRBSEN, CH0_TXRESETMODE, CH0_TXSPCSEQADV, CH0_TXUSRCLK, CH0_TXUSRCLK2, CH0_TXUSRRDY, CH1_AXISEN, CH1_AXISRST, CH1_AXISTRDY, CH1_CFGRESET, CH1_DMONFIFORESET, CH1_DMONITORCLK +, CH1_GTMRXN, CH1_GTMRXP, CH1_GTRXRESET, CH1_GTTXRESET, CH1_LOOPBACK, CH1_PCSRSVDIN, CH1_PMARSVDIN, CH1_RESETOVRD, CH1_RXADAPTRESET, CH1_RXADCCALRESET, CH1_RXADCCLKGENRESET, CH1_RXBUFRESET, CH1_RXCDRFREQOS, CH1_RXCDRFRRESET, CH1_RXCDRHOLD, CH1_RXCDRINCPCTRL, CH1_RXCDROVRDEN, CH1_RXCDRPHRESET, CH1_RXDFERESET, CH1_RXDSPRESET, CH1_RXEQTRAINING +, CH1_RXEYESCANRESET, CH1_RXFECRESET, CH1_RXOUTCLKSEL, CH1_RXPCSRESET, CH1_RXPCSRESETMASK, CH1_RXPMARESET, CH1_RXPMARESETMASK, CH1_RXPOLARITY, CH1_RXPRBSCNTSTOP, CH1_RXPRBSCSCNTRST, CH1_RXPRBSPTN, CH1_RXPROGDIVRESET, CH1_RXQPRBSEN, CH1_RXRESETMODE, CH1_RXSPCSEQADV, CH1_RXUSRCLK, CH1_RXUSRCLK2, CH1_RXUSRRDY, CH1_RXUSRSTART, CH1_RXUSRSTOP, CH1_TXCKALRESET +, CH1_TXCTLFIRDAT, CH1_TXDATA, CH1_TXDATASTART, CH1_TXDRVAMP, CH1_TXEMPMAIN, CH1_TXEMPPOST, CH1_TXEMPPRE, CH1_TXEMPPRE2, CH1_TXFECRESET, CH1_TXINHIBIT, CH1_TXMUXDCDEXHOLD, CH1_TXMUXDCDORWREN, CH1_TXOUTCLKSEL, CH1_TXPCSRESET, CH1_TXPCSRESETMASK, CH1_TXPMARESET, CH1_TXPMARESETMASK, CH1_TXPOLARITY, CH1_TXPRBSINERR, CH1_TXPRBSPTN, CH1_TXPROGDIVRESET +, CH1_TXQPRBSEN, CH1_TXRESETMODE, CH1_TXSPCSEQADV, CH1_TXUSRCLK, CH1_TXUSRCLK2, CH1_TXUSRRDY, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, FECCTRLRX0BITSLIPFS, FECCTRLRX1BITSLIPFS, GTGREFCLK2PLL, GTNORTHREFCLK, GTREFCLK, GTSOUTHREFCLK, PLLFBDIV, PLLMONCLK, PLLPD +, PLLREFCLKSEL, PLLRESET, PLLRESETBYPASSMODE, PLLRESETMASK, PLLRSVDIN, RCALENB, SDMDATA, SDMTOGGLE); parameter [15:0] A_CFG = 16'b0000100001000000; parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000; parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000; @@ -19575,7 +19803,7 @@ module GTM_DUAL (...); input SDMTOGGLE; endmodule -module IBUFDS_GTM (...); +module IBUFDS_GTM(O, ODIV2, CEB, I, IB); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter integer REFCLK_HROW_CK_SEL = 0; parameter integer REFCLK_ICNTL_RX = 0; @@ -19588,7 +19816,7 @@ module IBUFDS_GTM (...); input IB; endmodule -module OBUFDS_GTM (...); +module OBUFDS_GTM(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter integer REFCLK_ICNTL_TX = 0; (* iopad_external_pin *) @@ -19599,7 +19827,7 @@ module OBUFDS_GTM (...); input I; endmodule -module OBUFDS_GTM_ADV (...); +module OBUFDS_GTM_ADV(O, OB, CEB, I); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter integer REFCLK_ICNTL_TX = 0; parameter [1:0] RXRECCLK_SEL = 2'b00; @@ -19611,7 +19839,9 @@ module OBUFDS_GTM_ADV (...); input [3:0] I; endmodule -module HSDAC (...); +module HSDAC(CLK_DAC, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_COMMON, STATUS_DAC0, STATUS_DAC1, STATUS_DAC2, STATUS_DAC3, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, VOUT0_N, VOUT0_P, VOUT1_N, VOUT1_P, VOUT2_N, VOUT2_P, VOUT3_N, VOUT3_P, CLK_FIFO_LM +, CONTROL_COMMON, CONTROL_DAC0, CONTROL_DAC1, CONTROL_DAC2, CONTROL_DAC3, DAC_CLK_N, DAC_CLK_P, DADDR, DATA_DAC0, DATA_DAC1, DATA_DAC2, DATA_DAC3, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH +, SYSREF_N, SYSREF_P); parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter integer XPA_CFG0 = 0; parameter integer XPA_CFG1 = 0; @@ -19665,7 +19895,9 @@ module HSDAC (...); input SYSREF_P; endmodule -module HSADC (...); +module HSADC(CLK_ADC, DATA_ADC0, DATA_ADC1, DATA_ADC2, DATA_ADC3, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_ADC0, STATUS_ADC1, STATUS_ADC2, STATUS_ADC3, STATUS_COMMON, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, ADC_CLK_N, ADC_CLK_P, CLK_FIFO_LM, CONTROL_ADC0, CONTROL_ADC1 +, CONTROL_ADC2, CONTROL_ADC3, CONTROL_COMMON, DADDR, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, VIN0_N, VIN0_P, VIN1_N, VIN1_P, VIN2_N, VIN2_P +, VIN3_N, VIN3_P, VIN_I01_N, VIN_I01_P, VIN_I23_N, VIN_I23_P); parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter integer XPA_CFG0 = 0; parameter integer XPA_CFG1 = 0; @@ -19723,7 +19955,9 @@ module HSADC (...); input VIN_I23_P; endmodule -module RFDAC (...); +module RFDAC(CLK_DAC, CLK_DIST_OUT_NORTH, CLK_DIST_OUT_SOUTH, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_COMMON, STATUS_DAC0, STATUS_DAC1, STATUS_DAC2, STATUS_DAC3, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, T1_ALLOWED_SOUTH, VOUT0_N, VOUT0_P, VOUT1_N, VOUT1_P, VOUT2_N, VOUT2_P +, VOUT3_N, VOUT3_P, CLK_DIST_IN_NORTH, CLK_DIST_IN_SOUTH, CLK_FIFO_LM, CONTROL_COMMON, CONTROL_DAC0, CONTROL_DAC1, CONTROL_DAC2, CONTROL_DAC3, DAC_CLK_N, DAC_CLK_P, DADDR, DATA_DAC0, DATA_DAC1, DATA_DAC2, DATA_DAC3, DCLK, DEN, DI, DWE +, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, T1_ALLOWED_NORTH); parameter integer LD_DEVICE = 0; parameter integer OPT_CLK_DIST = 0; parameter SIM_DEVICE = "ULTRASCALE_PLUS"; @@ -19787,7 +20021,9 @@ module RFDAC (...); input T1_ALLOWED_NORTH; endmodule -module RFADC (...); +module RFADC(CLK_ADC, CLK_DIST_OUT_NORTH, CLK_DIST_OUT_SOUTH, DATA_ADC0, DATA_ADC1, DATA_ADC2, DATA_ADC3, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_ADC0, STATUS_ADC1, STATUS_ADC2, STATUS_ADC3, STATUS_COMMON, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, T1_ALLOWED_SOUTH, ADC_CLK_N, ADC_CLK_P +, CLK_DIST_IN_NORTH, CLK_DIST_IN_SOUTH, CLK_FIFO_LM, CONTROL_ADC0, CONTROL_ADC1, CONTROL_ADC2, CONTROL_ADC3, CONTROL_COMMON, DADDR, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, T1_ALLOWED_NORTH +, VIN0_N, VIN0_P, VIN1_N, VIN1_P, VIN2_N, VIN2_P, VIN3_N, VIN3_P, VIN_I01_N, VIN_I01_P, VIN_I23_N, VIN_I23_P); parameter integer LD_DEVICE = 0; parameter integer OPT_ANALOG = 0; parameter integer OPT_CLK_DIST = 0; @@ -19856,7 +20092,14 @@ module RFADC (...); input VIN_I23_P; endmodule -module PCIE_A1 (...); +module PCIE_A1(CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTRDYN +, CFGLINKCONTOLRCB, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGRDWRDONEN, CFGTOTURNOFFN, DBGBADDLLPSTATUS, DBGBADTLPLCRC, DBGBADTLPSEQNUM, DBGBADTLPSTATUS, DBGDLPROTOCOLSTATUS, DBGFCPROTOCOLERRSTATUS, DBGMLFRMDLENGTH, DBGMLFRMDMPS, DBGMLFRMDTCVC, DBGMLFRMDTLPSTATUS, DBGMLFRMDUNRECTYPE, DBGPOISTLPSTATUS, DBGRCVROVERFLOWSTATUS, DBGREGDETECTEDCORRECTABLE, DBGREGDETECTEDFATAL, DBGREGDETECTEDNONFATAL +, DBGREGDETECTEDUNSUPPORTED, DBGRPLYROLLOVERSTATUS, DBGRPLYTIMEOUTSTATUS, DBGURNOBARHIT, DBGURPOISCFGWR, DBGURSTATUS, DBGURUNSUPMSG, MIMRXREN, MIMRXWEN, MIMTXREN, MIMTXWEN, PIPEGTTXELECIDLEA, PIPEGTTXELECIDLEB, PIPERXPOLARITYA, PIPERXPOLARITYB, PIPERXRESETA, PIPERXRESETB, PIPETXRCVRDETA, PIPETXRCVRDETB, RECEIVEDHOTRESET, TRNLNKUPN +, TRNREOFN, TRNRERRFWDN, TRNRSOFN, TRNRSRCDSCN, TRNRSRCRDYN, TRNTCFGREQN, TRNTDSTRDYN, TRNTERRDROPN, USERRSTN, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, TRNFCCPLD, TRNFCNPD, TRNFCPD, PIPETXDATAA, PIPETXDATAB, CFGLINKCONTROLASPMCONTROL, PIPEGTPOWERDOWNA, PIPEGTPOWERDOWNB +, PIPETXCHARDISPMODEA, PIPETXCHARDISPMODEB, PIPETXCHARDISPVALA, PIPETXCHARDISPVALB, PIPETXCHARISKA, PIPETXCHARISKB, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGFUNCTIONNUMBER, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATEN, CFGDO, TRNRD, MIMRXWDATA, MIMTXWDATA, CFGDEVICENUMBER, CFGLTSSMSTATE, TRNTBUFAV, TRNRBARHITN, CFGBUSNUMBER, CFGINTERRUPTDO +, TRNFCCPLH, TRNFCNPH, TRNFCPH, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRECRCN, CFGERRLOCKEDN, CFGERRPOSTEDN, CFGERRURN, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGPMWAKEN, CFGRDENN, CFGTRNPENDINGN, CFGTURNOFFOKN, CLOCKLOCKED, MGTCLK, PIPEGTRESETDONEA, PIPEGTRESETDONEB, PIPEPHYSTATUSA +, PIPEPHYSTATUSB, PIPERXENTERELECIDLEA, PIPERXENTERELECIDLEB, SYSRESETN, TRNRDSTRDYN, TRNRNPOKN, TRNTCFGGNTN, TRNTEOFN, TRNTERRFWDN, TRNTSOFN, TRNTSRCDSCN, TRNTSRCRDYN, TRNTSTRN, USERCLK, CFGDEVID, CFGSUBSYSID, CFGSUBSYSVENID, CFGVENID, PIPERXDATAA, PIPERXDATAB, PIPERXCHARISKA +, PIPERXCHARISKB, PIPERXSTATUSA, PIPERXSTATUSB, TRNFCSEL, TRNTD, MIMRXRDATA, MIMTXRDATA, CFGERRTLPCPLHEADER, CFGDSN, CFGINTERRUPTDI, CFGREVID, CFGDWADDR); parameter [31:0] BAR0 = 32'h00000000; parameter [31:0] BAR1 = 32'h00000000; parameter [31:0] BAR2 = 32'h00000000; @@ -20099,7 +20342,20 @@ module PCIE_A1 (...); input [9:0] CFGDWADDR; endmodule -module PCIE_EP (...); +module PCIE_EP(BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0CFGLOOPBACKACK, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0FIRSTCFGWRITEOCCURRED, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MSIENABLE0, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0PWRL1STATE +, L0PWRL23READYSTATE, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RXDLLPM, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0UNLOCKRECEIVED, LLKRXEOFN, LLKRXEOPN, LLKRXSOFN, LLKRXSOPN, LLKRXSRCLASTREQN, LLKRXSRCRDYN +, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MEMSPACEENABLE, MIMDLLBREN, MIMDLLBWEN, MIMRXBREN, MIMRXBWEN, MIMTXBREN, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPERESETL0, PIPERESETL1, PIPERESETL2 +, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7 +, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4 +, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBWADD, L0COMPLETERID, MIMRXBRADD, MIMRXBWADD, MIMTXBRADD, MIMTXBWADD, LLKRXPREFERREDTYPE, MGMTPSO, L0PWRSTATE0, L0RXMACLINKERROR, LLKRXVALIDN, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2 +, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, L0MULTIMSGEN0, L0RXDLLPMTYPE, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MGMTRDATA, L0LTSSMSTATE, L0MACNEGOTIATEDLINKWIDTH, LLKRXDATA, MIMDLLBWDATA, MIMRXBWDATA, MIMTXBWDATA, L0DLLERRORVECTOR, L0DLLVCSTATUS, L0DLUPDOWN, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHNONPOSTEDAVAILABLEN +, LLKRXCHPOSTEDAVAILABLEN, LLKTCSTATUS, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, LLKTXCHANSPACE, AUXPOWER, COMPLIANCEAVOID, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN +, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, L0CFGDISABLESCRAMBLE, L0CFGLOOPBACKMASTER, L0LEGACYINTFUNCT0, L0PMEREQIN, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR +, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TRANSACTIONSPENDING, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MGMTRDEN, MGMTWREN, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2 +, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7 +, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7, MGMTADDR, L0PACKETHEADERFROMUSER, LLKRXCHFIFO, LLKTXCHFIFO, LLKTXENABLEN +, LLKRXCHTC, LLKTXCHTC, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, MGMTWDATA, L0MSIREQUEST0, MGMTBWREN, LLKTXDATA, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, MGMTSTATSCREDITSEL, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2 +, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7); parameter BAR0EXIST = "TRUE"; parameter BAR0PREFETCHABLE = "TRUE"; parameter BAR1EXIST = "FALSE"; @@ -20540,7 +20796,23 @@ module PCIE_EP (...); input [7:0] PIPERXDATAL7; endmodule -module PCIE_2_0 (...); +module PCIE_2_0(CFGAERECRCCHECKEN, CFGAERECRCGENEN, CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROL2CPLTIMEOUTDIS, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED +, CFGERRAERHEADERLOGSETN, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFM, CFGINTERRUPTRDYN, CFGLINKCONTROLAUTOBANDWIDTHINTEN, CFGLINKCONTROLBANDWIDTHINTEN, CFGLINKCONTROLCLOCKPMEN, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGLINKCONTROLHWAUTOWIDTHDIS, CFGLINKCONTROLLINKDISABLE, CFGLINKCONTROLRCB, CFGLINKCONTROLRETRAINLINK, CFGLINKSTATUSAUTOBANDWIDTHSTATUS, CFGLINKSTATUSBANDWITHSTATUS, CFGLINKSTATUSDLLACTIVE, CFGLINKSTATUSLINKTRAINING, CFGMSGRECEIVED, CFGMSGRECEIVEDASSERTINTA +, CFGMSGRECEIVEDASSERTINTB, CFGMSGRECEIVEDASSERTINTC, CFGMSGRECEIVEDASSERTINTD, CFGMSGRECEIVEDDEASSERTINTA, CFGMSGRECEIVEDDEASSERTINTB, CFGMSGRECEIVEDDEASSERTINTC, CFGMSGRECEIVEDDEASSERTINTD, CFGMSGRECEIVEDERRCOR, CFGMSGRECEIVEDERRFATAL, CFGMSGRECEIVEDERRNONFATAL, CFGMSGRECEIVEDPMASNAK, CFGMSGRECEIVEDPMETO, CFGMSGRECEIVEDPMETOACK, CFGMSGRECEIVEDPMPME, CFGMSGRECEIVEDSETSLOTPOWERLIMIT, CFGMSGRECEIVEDUNLOCK, CFGPMCSRPMEEN, CFGPMCSRPMESTATUS, CFGPMRCVASREQL1N, CFGPMRCVENTERL1N, CFGPMRCVENTERL23N +, CFGPMRCVREQACKN, CFGRDWRDONEN, CFGSLOTCONTROLELECTROMECHILCTLPULSE, CFGTRANSACTION, CFGTRANSACTIONTYPE, DBGSCLRA, DBGSCLRB, DBGSCLRC, DBGSCLRD, DBGSCLRE, DBGSCLRF, DBGSCLRG, DBGSCLRH, DBGSCLRI, DBGSCLRJ, DBGSCLRK, DRPDRDY, LL2BADDLLPERRN, LL2BADTLPERRN, LL2PROTOCOLERRN, LL2REPLAYROERRN +, LL2REPLAYTOERRN, LL2SUSPENDOKN, LL2TFCINIT1SEQN, LL2TFCINIT2SEQN, LNKCLKEN, MIMRXRCE, MIMRXREN, MIMRXWEN, MIMTXRCE, MIMTXREN, MIMTXWEN, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0ELECIDLE +, PIPETX1COMPLIANCE, PIPETX1ELECIDLE, PIPETX2COMPLIANCE, PIPETX2ELECIDLE, PIPETX3COMPLIANCE, PIPETX3ELECIDLE, PIPETX4COMPLIANCE, PIPETX4ELECIDLE, PIPETX5COMPLIANCE, PIPETX5ELECIDLE, PIPETX6COMPLIANCE, PIPETX6ELECIDLE, PIPETX7COMPLIANCE, PIPETX7ELECIDLE, PIPETXDEEMPH, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PL2LINKUPN, PL2RECEIVERERRN, PL2RECOVERYN +, PL2RXELECIDLE, PL2SUSPENDOK, PLLINKGEN2CAP, PLLINKPARTNERGEN2SUPPORTED, PLLINKUPCFGCAP, PLPHYLNKUPN, PLRECEIVEDHOTRST, PLSELLNKRATE, RECEIVEDFUNCLVLRSTN, TL2ASPMSUSPENDCREDITCHECKOKN, TL2ASPMSUSPENDREQN, TL2PPMSUSPENDOKN, TRNLNKUPN, TRNRDLLPSRCRDYN, TRNRECRCERRN, TRNREOFN, TRNRERRFWDN, TRNRREMN, TRNRSOFN, TRNRSRCDSCN, TRNRSRCRDYN +, TRNTCFGREQN, TRNTDLLPDSTRDYN, TRNTDSTRDYN, TRNTERRDROPN, USERRSTN, DBGVECC, PLDBGVEC, TRNFCCPLD, TRNFCNPD, TRNFCPD, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, CFGMSGDATA, DRPDO, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA +, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGLINKCONTROLASPMCONTROL, CFGLINKSTATUSCURRENTSPEED, CFGPMCSRPOWERSTATE, PIPETX0CHARISK, PIPETX0POWERDOWN, PIPETX1CHARISK, PIPETX1POWERDOWN, PIPETX2CHARISK, PIPETX2POWERDOWN, PIPETX3CHARISK, PIPETX3POWERDOWN, PIPETX4CHARISK, PIPETX4POWERDOWN, PIPETX5CHARISK, PIPETX5POWERDOWN, PIPETX6CHARISK, PIPETX6POWERDOWN, PIPETX7CHARISK +, PIPETX7POWERDOWN, PLLANEREVERSALMODE, PLRXPMSTATE, PLSELLNKWIDTH, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATE, PIPETXMARGIN, PLINITIALLINKWIDTH, PLTXPMSTATE, CFGDO, TRNRDLLPDATA, CFGDEVCONTROL2CPLTIMEOUTVAL, CFGLINKSTATUSNEGOTIATEDWIDTH, PLLTSSMSTATE, TRNTBUFAV, DBGVECA, DBGVECB, TRNRD, MIMRXWDATA +, MIMTXWDATA, CFGTRANSACTIONADDR, CFGVCTCVCMAP, TRNRBARHITN, CFGINTERRUPTDO, TRNFCCPLH, TRNFCNPH, TRNFCPH, CFGERRACSN, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRCPLUNEXPECTN, CFGERRECRCN, CFGERRLOCKEDN, CFGERRPOSTEDN, CFGERRURN, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGPMDIRECTASPML1N, CFGPMSENDPMACKN +, CFGPMSENDPMETON, CFGPMSENDPMNAKN, CFGPMTURNOFFOKN, CFGPMWAKEN, CFGRDENN, CFGTRNPENDINGN, CFGWRENN, CFGWRREADONLYN, CFGWRRW1CASRWN, CMRSTN, CMSTICKYRSTN, DBGSUBMODE, DLRSTN, DRPCLK, DRPDEN, DRPDWE, FUNCLVLRSTN, LL2SENDASREQL1N, LL2SENDENTERL1N, LL2SENDENTERL23N, LL2SUSPENDNOWN +, LL2TLPRCVN, PIPECLK, PIPERX0CHANISALIGNED, PIPERX0ELECIDLE, PIPERX0PHYSTATUS, PIPERX0VALID, PIPERX1CHANISALIGNED, PIPERX1ELECIDLE, PIPERX1PHYSTATUS, PIPERX1VALID, PIPERX2CHANISALIGNED, PIPERX2ELECIDLE, PIPERX2PHYSTATUS, PIPERX2VALID, PIPERX3CHANISALIGNED, PIPERX3ELECIDLE, PIPERX3PHYSTATUS, PIPERX3VALID, PIPERX4CHANISALIGNED, PIPERX4ELECIDLE, PIPERX4PHYSTATUS +, PIPERX4VALID, PIPERX5CHANISALIGNED, PIPERX5ELECIDLE, PIPERX5PHYSTATUS, PIPERX5VALID, PIPERX6CHANISALIGNED, PIPERX6ELECIDLE, PIPERX6PHYSTATUS, PIPERX6VALID, PIPERX7CHANISALIGNED, PIPERX7ELECIDLE, PIPERX7PHYSTATUS, PIPERX7VALID, PLDIRECTEDLINKAUTON, PLDIRECTEDLINKSPEED, PLDOWNSTREAMDEEMPHSOURCE, PLRSTN, PLTRANSMITHOTRST, PLUPSTREAMPREFERDEEMPH, SYSRSTN, TL2ASPMSUSPENDCREDITCHECKN +, TL2PPMSUSPENDREQN, TLRSTN, TRNRDSTRDYN, TRNRNPOKN, TRNTCFGGNTN, TRNTDLLPSRCRDYN, TRNTECRCGENN, TRNTEOFN, TRNTERRFWDN, TRNTREMN, TRNTSOFN, TRNTSRCDSCN, TRNTSRCRDYN, TRNTSTRN, USERCLK, CFGERRAERHEADERLOG, DRPDI, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA +, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, DBGMODE, PIPERX0CHARISK, PIPERX1CHARISK, PIPERX2CHARISK, PIPERX3CHARISK, PIPERX4CHARISK, PIPERX5CHARISK, PIPERX6CHARISK, PIPERX7CHARISK, PLDIRECTEDLINKCHANGE, PLDIRECTEDLINKWIDTH, CFGDSFUNCTIONNUMBER, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS +, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, PLDBGMODE, TRNFCSEL, CFGDI, TRNTDLLPDATA, CFGBYTEENN, CFGERRTLPCPLHEADER, CFGDSDEVICENUMBER, PL2DIRECTEDLSTATE, CFGDSN, TRNTD, MIMRXRDATA, MIMTXRDATA, CFGDSBUSNUMBER, CFGINTERRUPTDI, CFGPORTNUMBER, DRPDADDR, CFGDWADDR); parameter [11:0] AER_BASE_PTR = 12'h128; parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; @@ -21135,7 +21407,26 @@ module PCIE_2_0 (...); input [9:0] CFGDWADDR; endmodule -module PCIE_2_1 (...); +module PCIE_2_1(CFGAERECRCCHECKEN, CFGAERECRCGENEN, CFGAERROOTERRCORRERRRECEIVED, CFGAERROOTERRCORRERRREPORTINGEN, CFGAERROOTERRFATALERRRECEIVED, CFGAERROOTERRFATALERRREPORTINGEN, CFGAERROOTERRNONFATALERRRECEIVED, CFGAERROOTERRNONFATALERRREPORTINGEN, CFGBRIDGESERREN, CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROL2ARIFORWARDEN, CFGDEVCONTROL2ATOMICEGRESSBLOCK, CFGDEVCONTROL2ATOMICREQUESTEREN, CFGDEVCONTROL2CPLTIMEOUTDIS, CFGDEVCONTROL2IDOCPLEN, CFGDEVCONTROL2IDOREQEN, CFGDEVCONTROL2LTREN +, CFGDEVCONTROL2TLPPREFIXBLOCK, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED, CFGERRAERHEADERLOGSETN, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFM, CFGINTERRUPTRDYN, CFGLINKCONTROLAUTOBANDWIDTHINTEN +, CFGLINKCONTROLBANDWIDTHINTEN, CFGLINKCONTROLCLOCKPMEN, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGLINKCONTROLHWAUTOWIDTHDIS, CFGLINKCONTROLLINKDISABLE, CFGLINKCONTROLRCB, CFGLINKCONTROLRETRAINLINK, CFGLINKSTATUSAUTOBANDWIDTHSTATUS, CFGLINKSTATUSBANDWIDTHSTATUS, CFGLINKSTATUSDLLACTIVE, CFGLINKSTATUSLINKTRAINING, CFGMGMTRDWRDONEN, CFGMSGRECEIVED, CFGMSGRECEIVEDASSERTINTA, CFGMSGRECEIVEDASSERTINTB, CFGMSGRECEIVEDASSERTINTC, CFGMSGRECEIVEDASSERTINTD, CFGMSGRECEIVEDDEASSERTINTA, CFGMSGRECEIVEDDEASSERTINTB, CFGMSGRECEIVEDDEASSERTINTC +, CFGMSGRECEIVEDDEASSERTINTD, CFGMSGRECEIVEDERRCOR, CFGMSGRECEIVEDERRFATAL, CFGMSGRECEIVEDERRNONFATAL, CFGMSGRECEIVEDPMASNAK, CFGMSGRECEIVEDPMETO, CFGMSGRECEIVEDPMETOACK, CFGMSGRECEIVEDPMPME, CFGMSGRECEIVEDSETSLOTPOWERLIMIT, CFGMSGRECEIVEDUNLOCK, CFGPMCSRPMEEN, CFGPMCSRPMESTATUS, CFGPMRCVASREQL1N, CFGPMRCVENTERL1N, CFGPMRCVENTERL23N, CFGPMRCVREQACKN, CFGROOTCONTROLPMEINTEN, CFGROOTCONTROLSYSERRCORRERREN, CFGROOTCONTROLSYSERRFATALERREN, CFGROOTCONTROLSYSERRNONFATALERREN, CFGSLOTCONTROLELECTROMECHILCTLPULSE +, CFGTRANSACTION, CFGTRANSACTIONTYPE, DBGSCLRA, DBGSCLRB, DBGSCLRC, DBGSCLRD, DBGSCLRE, DBGSCLRF, DBGSCLRG, DBGSCLRH, DBGSCLRI, DBGSCLRJ, DBGSCLRK, DRPRDY, LL2BADDLLPERR, LL2BADTLPERR, LL2PROTOCOLERR, LL2RECEIVERERR, LL2REPLAYROERR, LL2REPLAYTOERR, LL2SUSPENDOK +, LL2TFCINIT1SEQ, LL2TFCINIT2SEQ, LL2TXIDLE, LNKCLKEN, MIMRXREN, MIMRXWEN, MIMTXREN, MIMTXWEN, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0ELECIDLE, PIPETX1COMPLIANCE, PIPETX1ELECIDLE, PIPETX2COMPLIANCE +, PIPETX2ELECIDLE, PIPETX3COMPLIANCE, PIPETX3ELECIDLE, PIPETX4COMPLIANCE, PIPETX4ELECIDLE, PIPETX5COMPLIANCE, PIPETX5ELECIDLE, PIPETX6COMPLIANCE, PIPETX6ELECIDLE, PIPETX7COMPLIANCE, PIPETX7ELECIDLE, PIPETXDEEMPH, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PL2L0REQ, PL2LINKUP, PL2RECEIVERERR, PL2RECOVERY, PL2RXELECIDLE, PL2SUSPENDOK +, PLDIRECTEDCHANGEDONE, PLLINKGEN2CAP, PLLINKPARTNERGEN2SUPPORTED, PLLINKUPCFGCAP, PLPHYLNKUPN, PLRECEIVEDHOTRST, PLSELLNKRATE, RECEIVEDFUNCLVLRSTN, TL2ASPMSUSPENDCREDITCHECKOK, TL2ASPMSUSPENDREQ, TL2ERRFCPE, TL2ERRMALFORMED, TL2ERRRXOVERFLOW, TL2PPMSUSPENDOK, TRNLNKUP, TRNRECRCERR, TRNREOF, TRNRERRFWD, TRNRSOF, TRNRSRCDSC, TRNRSRCRDY +, TRNTCFGREQ, TRNTDLLPDSTRDY, TRNTERRDROP, USERRSTN, DBGVECC, PLDBGVEC, TRNFCCPLD, TRNFCNPD, TRNFCPD, TRNRD, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, CFGMSGDATA, DRPDO, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA +, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGLINKCONTROLASPMCONTROL, CFGLINKSTATUSCURRENTSPEED, CFGPMCSRPOWERSTATE, PIPETX0CHARISK, PIPETX0POWERDOWN, PIPETX1CHARISK, PIPETX1POWERDOWN, PIPETX2CHARISK, PIPETX2POWERDOWN, PIPETX3CHARISK, PIPETX3POWERDOWN, PIPETX4CHARISK, PIPETX4POWERDOWN, PIPETX5CHARISK, PIPETX5POWERDOWN, PIPETX6CHARISK, PIPETX6POWERDOWN, PIPETX7CHARISK +, PIPETX7POWERDOWN, PL2RXPMSTATE, PLLANEREVERSALMODE, PLRXPMSTATE, PLSELLNKWIDTH, TRNRDLLPSRCRDY, TRNRREM, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATE, PIPETXMARGIN, PLINITIALLINKWIDTH, PLTXPMSTATE, CFGMGMTDO, CFGDEVCONTROL2CPLTIMEOUTVAL, CFGLINKSTATUSNEGOTIATEDWIDTH, TRNTDSTRDY, LL2LINKSTATUS, PLLTSSMSTATE, TRNTBUFAV +, DBGVECA, DBGVECB, TL2ERRHDR, TRNRDLLPDATA, MIMRXWDATA, MIMTXWDATA, CFGTRANSACTIONADDR, CFGVCTCVCMAP, CFGINTERRUPTDO, TRNFCCPLH, TRNFCNPH, TRNFCPH, TRNRBARHIT, CFGERRACSN, CFGERRATOMICEGRESSBLOCKEDN, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRCPLUNEXPECTN, CFGERRECRCN, CFGERRINTERNALCORN +, CFGERRINTERNALUNCORN, CFGERRLOCKEDN, CFGERRMALFORMEDN, CFGERRMCBLOCKEDN, CFGERRNORECOVERYN, CFGERRPOISONEDN, CFGERRPOSTEDN, CFGERRURN, CFGFORCECOMMONCLOCKOFF, CFGFORCEEXTENDEDSYNCON, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGINTERRUPTSTATN, CFGMGMTRDENN, CFGMGMTWRENN, CFGMGMTWRREADONLYN, CFGMGMTWRRW1CASRWN, CFGPMFORCESTATEENN, CFGPMHALTASPML0SN, CFGPMHALTASPML1N, CFGPMSENDPMETON +, CFGPMTURNOFFOKN, CFGPMWAKEN, CFGTRNPENDINGN, CMRSTN, CMSTICKYRSTN, DBGSUBMODE, DLRSTN, DRPCLK, DRPEN, DRPWE, FUNCLVLRSTN, LL2SENDASREQL1, LL2SENDENTERL1, LL2SENDENTERL23, LL2SENDPMACK, LL2SUSPENDNOW, LL2TLPRCV, PIPECLK, PIPERX0CHANISALIGNED, PIPERX0ELECIDLE, PIPERX0PHYSTATUS +, PIPERX0VALID, PIPERX1CHANISALIGNED, PIPERX1ELECIDLE, PIPERX1PHYSTATUS, PIPERX1VALID, PIPERX2CHANISALIGNED, PIPERX2ELECIDLE, PIPERX2PHYSTATUS, PIPERX2VALID, PIPERX3CHANISALIGNED, PIPERX3ELECIDLE, PIPERX3PHYSTATUS, PIPERX3VALID, PIPERX4CHANISALIGNED, PIPERX4ELECIDLE, PIPERX4PHYSTATUS, PIPERX4VALID, PIPERX5CHANISALIGNED, PIPERX5ELECIDLE, PIPERX5PHYSTATUS, PIPERX5VALID +, PIPERX6CHANISALIGNED, PIPERX6ELECIDLE, PIPERX6PHYSTATUS, PIPERX6VALID, PIPERX7CHANISALIGNED, PIPERX7ELECIDLE, PIPERX7PHYSTATUS, PIPERX7VALID, PLDIRECTEDLINKAUTON, PLDIRECTEDLINKSPEED, PLDIRECTEDLTSSMNEWVLD, PLDIRECTEDLTSSMSTALL, PLDOWNSTREAMDEEMPHSOURCE, PLRSTN, PLTRANSMITHOTRST, PLUPSTREAMPREFERDEEMPH, SYSRSTN, TL2ASPMSUSPENDCREDITCHECK, TL2PPMSUSPENDREQ, TLRSTN, TRNRDSTRDY +, TRNRFCPRET, TRNRNPOK, TRNRNPREQ, TRNTCFGGNT, TRNTDLLPSRCRDY, TRNTECRCGEN, TRNTEOF, TRNTERRFWD, TRNTSOF, TRNTSRCDSC, TRNTSRCRDY, TRNTSTR, USERCLK2, USERCLK, CFGERRAERHEADERLOG, TRNTD, CFGDEVID, CFGSUBSYSID, CFGSUBSYSVENDID, CFGVENDID, DRPDI +, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, CFGPMFORCESTATE, DBGMODE, PIPERX0CHARISK, PIPERX1CHARISK, PIPERX2CHARISK, PIPERX3CHARISK, PIPERX4CHARISK, PIPERX5CHARISK, PIPERX6CHARISK, PIPERX7CHARISK, PLDIRECTEDLINKCHANGE, PLDIRECTEDLINKWIDTH, TRNTREM +, CFGDSFUNCTIONNUMBER, CFGFORCEMPS, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, PLDBGMODE, TRNFCSEL, CFGMGMTDI, TRNTDLLPDATA, CFGMGMTBYTEENN, CFGERRTLPCPLHEADER, CFGAERINTERRUPTMSGNUM, CFGDSDEVICENUMBER, CFGPCIECAPINTERRUPTMSGNUM, PL2DIRECTEDLSTATE, PLDIRECTEDLTSSMNEW +, CFGDSN, MIMRXRDATA, MIMTXRDATA, CFGDSBUSNUMBER, CFGINTERRUPTDI, CFGPORTNUMBER, CFGREVID, DRPADDR, CFGMGMTDWADDR); parameter [11:0] AER_BASE_PTR = 12'h140; parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; @@ -21830,7 +22121,29 @@ module PCIE_2_1 (...); input [9:0] CFGMGMTDWADDR; endmodule -module PCIE_3_0 (...); +module PCIE_3_0(CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTREADRECEIVED, CFGEXTWRITERECEIVED, CFGHOTRESETOUT, CFGINPUTUPDATEDONE, CFGINTERRUPTAOUTPUT, CFGINTERRUPTBOUTPUT, CFGINTERRUPTCOUTPUT, CFGINTERRUPTDOUTPUT, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXFAIL, CFGINTERRUPTMSIXSENT, CFGINTERRUPTSENT, CFGLOCALERROR, CFGLTRENABLE, CFGMCUPDATEDONE, CFGMGMTREADWRITEDONE +, CFGMSGRECEIVED, CFGMSGTRANSMITDONE, CFGPERFUNCTIONUPDATEDONE, CFGPHYLINKDOWN, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGTPHSTTREADENABLE, CFGTPHSTTWRITEENABLE, DRPRDY, MAXISCQTLAST, MAXISCQTVALID, MAXISRCTLAST, MAXISRCTVALID, PCIERQSEQNUMVLD, PCIERQTAGVLD, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY +, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0DATAVALID, PIPETX0ELECIDLE, PIPETX0STARTBLOCK, PIPETX1COMPLIANCE, PIPETX1DATAVALID, PIPETX1ELECIDLE, PIPETX1STARTBLOCK, PIPETX2COMPLIANCE, PIPETX2DATAVALID, PIPETX2ELECIDLE, PIPETX2STARTBLOCK, PIPETX3COMPLIANCE, PIPETX3DATAVALID, PIPETX3ELECIDLE, PIPETX3STARTBLOCK, PIPETX4COMPLIANCE, PIPETX4DATAVALID, PIPETX4ELECIDLE +, PIPETX4STARTBLOCK, PIPETX5COMPLIANCE, PIPETX5DATAVALID, PIPETX5ELECIDLE, PIPETX5STARTBLOCK, PIPETX6COMPLIANCE, PIPETX6DATAVALID, PIPETX6ELECIDLE, PIPETX6STARTBLOCK, PIPETX7COMPLIANCE, PIPETX7DATAVALID, PIPETX7ELECIDLE, PIPETX7STARTBLOCK, PIPETXDEEMPH, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, CFGFCCPLD, CFGFCNPD, CFGFCPD +, CFGVFSTATUS, MIREPLAYRAMWRITEDATA, MIREQUESTRAMWRITEDATA, CFGPERFUNCSTATUSDATA, DBGDATAOUT, DRPDO, CFGVFPOWERSTATE, CFGVFTPHSTMODE, CFGDPASUBSTATECHANGE, CFGFLRINPROCESS, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGLINKPOWERSTATE, CFGOBFFENABLE, CFGPHYLINKSTATUS, CFGRCBSTATUS, CFGTPHREQUESTERENABLE, MIREPLAYRAMREADENABLE, MIREPLAYRAMWRITEENABLE, PCIERQTAGAV +, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX0EQCONTROL, PIPERX1EQCONTROL, PIPERX2EQCONTROL, PIPERX3EQCONTROL, PIPERX4EQCONTROL, PIPERX5EQCONTROL, PIPERX6EQCONTROL, PIPERX7EQCONTROL, PIPETX0CHARISK, PIPETX0EQCONTROL, PIPETX0POWERDOWN, PIPETX0SYNCHEADER, PIPETX1CHARISK, PIPETX1EQCONTROL, PIPETX1POWERDOWN, PIPETX1SYNCHEADER, PIPETX2CHARISK, PIPETX2EQCONTROL, PIPETX2POWERDOWN +, PIPETX2SYNCHEADER, PIPETX3CHARISK, PIPETX3EQCONTROL, PIPETX3POWERDOWN, PIPETX3SYNCHEADER, PIPETX4CHARISK, PIPETX4EQCONTROL, PIPETX4POWERDOWN, PIPETX4SYNCHEADER, PIPETX5CHARISK, PIPETX5EQCONTROL, PIPETX5POWERDOWN, PIPETX5SYNCHEADER, PIPETX6CHARISK, PIPETX6EQCONTROL, PIPETX6POWERDOWN, PIPETX6SYNCHEADER, PIPETX7CHARISK, PIPETX7EQCONTROL, PIPETX7POWERDOWN, PIPETX7SYNCHEADER +, PIPETXRATE, PLEQPHASE, MAXISCQTDATA, MAXISRCTDATA, CFGCURRENTSPEED, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGTPHFUNCTIONNUM, PIPERX0EQPRESET, PIPERX1EQPRESET, PIPERX2EQPRESET, PIPERX3EQPRESET, PIPERX4EQPRESET, PIPERX5EQPRESET, PIPERX6EQPRESET, PIPERX7EQPRESET, PIPETXMARGIN, CFGEXTWRITEDATA, CFGINTERRUPTMSIDATA, CFGMGMTREADDATA, CFGTPHSTTWRITEDATA +, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGEXTWRITEBYTEENABLE, CFGNEGOTIATEDWIDTH, CFGTPHSTTWRITEBYTEVALID, MICOMPLETIONRAMREADENABLEL, MICOMPLETIONRAMREADENABLEU, MICOMPLETIONRAMWRITEENABLEL, MICOMPLETIONRAMWRITEENABLEU, MIREQUESTRAMREADENABLE, MIREQUESTRAMWRITEENABLE, PCIERQSEQNUM, PIPERX0EQLPTXPRESET, PIPERX1EQLPTXPRESET, PIPERX2EQLPTXPRESET +, PIPERX3EQLPTXPRESET, PIPERX4EQLPTXPRESET, PIPERX5EQLPTXPRESET, PIPERX6EQLPTXPRESET, PIPERX7EQLPTXPRESET, PIPETX0EQPRESET, PIPETX1EQPRESET, PIPETX2EQPRESET, PIPETX3EQPRESET, PIPETX4EQPRESET, PIPETX5EQPRESET, PIPETX6EQPRESET, PIPETX7EQPRESET, SAXISCCTREADY, SAXISRQTREADY, CFGMSGRECEIVEDTYPE, CFGTPHSTTADDRESS, CFGFUNCTIONPOWERSTATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSIVFENABLE, CFGINTERRUPTMSIXVFENABLE +, CFGINTERRUPTMSIXVFMASK, CFGLTSSMSTATE, CFGTPHSTMODE, CFGVFFLRINPROCESS, CFGVFTPHREQUESTERENABLE, PCIECQNPREQCOUNT, PCIERQTAG, PIPERX0EQLPLFFS, PIPERX1EQLPLFFS, PIPERX2EQLPLFFS, PIPERX3EQLPLFFS, PIPERX4EQLPLFFS, PIPERX5EQLPLFFS, PIPERX6EQLPLFFS, PIPERX7EQLPLFFS, PIPETX0EQDEEMPH, PIPETX1EQDEEMPH, PIPETX2EQDEEMPH, PIPETX3EQDEEMPH, PIPETX4EQDEEMPH, PIPETX5EQDEEMPH +, PIPETX6EQDEEMPH, PIPETX7EQDEEMPH, MICOMPLETIONRAMWRITEDATAL, MICOMPLETIONRAMWRITEDATAU, MAXISRCTUSER, CFGEXTFUNCTIONNUMBER, CFGFCCPLH, CFGFCNPH, CFGFCPH, CFGFUNCTIONSTATUS, CFGMSGRECEIVEDDATA, MAXISCQTKEEP, MAXISRCTKEEP, PLGEN3PCSRXSLIDE, MAXISCQTUSER, MIREPLAYRAMADDRESS, MIREQUESTRAMREADADDRESSA, MIREQUESTRAMREADADDRESSB, MIREQUESTRAMWRITEADDRESSA, MIREQUESTRAMWRITEADDRESSB, CFGEXTREGISTERNUMBER +, MICOMPLETIONRAMREADADDRESSAL, MICOMPLETIONRAMREADADDRESSAU, MICOMPLETIONRAMREADADDRESSBL, MICOMPLETIONRAMREADADDRESSBU, MICOMPLETIONRAMWRITEADDRESSAL, MICOMPLETIONRAMWRITEADDRESSAU, MICOMPLETIONRAMWRITEADDRESSBL, MICOMPLETIONRAMWRITEADDRESSBU, CFGCONFIGSPACEENABLE, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATAVALID, CFGHOTRESETIN, CFGINPUTUPDATEREQUEST, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSIXINT, CFGLINKTRAININGENABLE, CFGMCUPDATEREQUEST, CFGMGMTREAD, CFGMGMTTYPE1CFGREGACCESS, CFGMGMTWRITE +, CFGMSGTRANSMIT, CFGPERFUNCTIONOUTPUTREQUEST, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGTPHSTTREADDATAVALID, CORECLK, CORECLKMICOMPLETIONRAML, CORECLKMICOMPLETIONRAMU, CORECLKMIREPLAYRAM, CORECLKMIREQUESTRAM, DRPCLK, DRPEN, DRPWE, MGMTRESETN, MGMTSTICKYRESETN, PCIECQNPREQ, PIPECLK, PIPERESETN, PIPERX0DATAVALID, PIPERX0ELECIDLE, PIPERX0EQDONE +, PIPERX0EQLPADAPTDONE, PIPERX0EQLPLFFSSEL, PIPERX0PHYSTATUS, PIPERX0STARTBLOCK, PIPERX0VALID, PIPERX1DATAVALID, PIPERX1ELECIDLE, PIPERX1EQDONE, PIPERX1EQLPADAPTDONE, PIPERX1EQLPLFFSSEL, PIPERX1PHYSTATUS, PIPERX1STARTBLOCK, PIPERX1VALID, PIPERX2DATAVALID, PIPERX2ELECIDLE, PIPERX2EQDONE, PIPERX2EQLPADAPTDONE, PIPERX2EQLPLFFSSEL, PIPERX2PHYSTATUS, PIPERX2STARTBLOCK, PIPERX2VALID +, PIPERX3DATAVALID, PIPERX3ELECIDLE, PIPERX3EQDONE, PIPERX3EQLPADAPTDONE, PIPERX3EQLPLFFSSEL, PIPERX3PHYSTATUS, PIPERX3STARTBLOCK, PIPERX3VALID, PIPERX4DATAVALID, PIPERX4ELECIDLE, PIPERX4EQDONE, PIPERX4EQLPADAPTDONE, PIPERX4EQLPLFFSSEL, PIPERX4PHYSTATUS, PIPERX4STARTBLOCK, PIPERX4VALID, PIPERX5DATAVALID, PIPERX5ELECIDLE, PIPERX5EQDONE, PIPERX5EQLPADAPTDONE, PIPERX5EQLPLFFSSEL +, PIPERX5PHYSTATUS, PIPERX5STARTBLOCK, PIPERX5VALID, PIPERX6DATAVALID, PIPERX6ELECIDLE, PIPERX6EQDONE, PIPERX6EQLPADAPTDONE, PIPERX6EQLPLFFSSEL, PIPERX6PHYSTATUS, PIPERX6STARTBLOCK, PIPERX6VALID, PIPERX7DATAVALID, PIPERX7ELECIDLE, PIPERX7EQDONE, PIPERX7EQLPADAPTDONE, PIPERX7EQLPLFFSSEL, PIPERX7PHYSTATUS, PIPERX7STARTBLOCK, PIPERX7VALID, PIPETX0EQDONE, PIPETX1EQDONE +, PIPETX2EQDONE, PIPETX3EQDONE, PIPETX4EQDONE, PIPETX5EQDONE, PIPETX6EQDONE, PIPETX7EQDONE, PLDISABLESCRAMBLER, PLEQRESETEIEOSCOUNT, PLGEN3PCSDISABLE, RECCLK, RESETN, SAXISCCTLAST, SAXISCCTVALID, SAXISRQTLAST, SAXISRQTVALID, USERCLK, DRPADDR, MICOMPLETIONRAMREADDATA, MIREPLAYRAMREADDATA, MIREQUESTRAMREADDATA, CFGDEVID +, CFGSUBSYSID, CFGSUBSYSVENDID, CFGVENDID, DRPDI, PIPERX0EQLPNEWTXCOEFFORPRESET, PIPERX1EQLPNEWTXCOEFFORPRESET, PIPERX2EQLPNEWTXCOEFFORPRESET, PIPERX3EQLPNEWTXCOEFFORPRESET, PIPERX4EQLPNEWTXCOEFFORPRESET, PIPERX5EQLPNEWTXCOEFFORPRESET, PIPERX6EQLPNEWTXCOEFFORPRESET, PIPERX7EQLPNEWTXCOEFFORPRESET, PIPETX0EQCOEFF, PIPETX1EQCOEFF, PIPETX2EQCOEFF, PIPETX3EQCOEFF, PIPETX4EQCOEFF, PIPETX5EQCOEFF, PIPETX6EQCOEFF, PIPETX7EQCOEFF, CFGMGMTADDR +, CFGFLRDONE, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTPENDING, PIPERX0CHARISK, PIPERX0SYNCHEADER, PIPERX1CHARISK, PIPERX1SYNCHEADER, PIPERX2CHARISK, PIPERX2SYNCHEADER, PIPERX3CHARISK, PIPERX3SYNCHEADER, PIPERX4CHARISK, PIPERX4SYNCHEADER, PIPERX5CHARISK, PIPERX5SYNCHEADER, PIPERX6CHARISK, PIPERX6SYNCHEADER, PIPERX7CHARISK, PIPERX7SYNCHEADER, MAXISCQTREADY, MAXISRCTREADY +, SAXISCCTDATA, SAXISRQTDATA, CFGDSFUNCTIONNUMBER, CFGFCSEL, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGMSGTRANSMITTYPE, CFGPERFUNCSTATUSCONTROL, CFGPERFUNCTIONNUMBER, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, CFGEXTREADDATA, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIXDATA, CFGMGMTWRITEDATA +, CFGMSGTRANSMITDATA, CFGTPHSTTREADDATA, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, SAXISCCTUSER, CFGINTERRUPTINT, CFGINTERRUPTMSISELECT, CFGMGMTBYTEENABLE, CFGDSDEVICENUMBER, SAXISRQTUSER, CFGVFFLRDONE, PIPEEQFS, PIPEEQLF, CFGDSN, CFGINTERRUPTMSIPENDINGSTATUS +, CFGINTERRUPTMSIXADDRESS, CFGDSBUSNUMBER, CFGDSPORTNUMBER, CFGREVID, PLGEN3PCSRXSYNCDONE, SAXISCCTKEEP, SAXISRQTKEEP, CFGINTERRUPTMSITPHSTTAG); parameter ARI_CAP_ENABLE = "FALSE"; parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; @@ -22736,7 +23049,33 @@ module PCIE_3_0 (...); input [8:0] CFGINTERRUPTMSITPHSTTAG; endmodule -module PCIE_3_1 (...); +module PCIE_3_1(CFGCURRENTSPEED, CFGDPASUBSTATECHANGE, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE, CFGFUNCTIONSTATUS, CFGHOTRESETOUT +, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIVFENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFAIL, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXSENT, CFGINTERRUPTMSIXVFENABLE, CFGINTERRUPTMSIXVFMASK, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROR, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA +, CFGMGMTREADWRITEDONE, CFGMSGRECEIVED, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPERFUNCSTATUSDATA, CFGPERFUNCTIONUPDATEDONE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGTPHFUNCTIONNUM, CFGTPHREQUESTERENABLE, CFGTPHSTMODE, CFGTPHSTTADDRESS, CFGTPHSTTREADENABLE, CFGTPHSTTWRITEBYTEVALID, CFGTPHSTTWRITEDATA +, CFGTPHSTTWRITEENABLE, CFGVFFLRINPROCESS, CFGVFPOWERSTATE, CFGVFSTATUS, CFGVFTPHREQUESTERENABLE, CFGVFTPHSTMODE, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGDATAOUT, DBGMCAPCSB, DBGMCAPDATA, DBGMCAPEOS, DBGMCAPERROR, DBGMCAPMODE, DBGMCAPRDATAVALID, DBGMCAPRDWRB, DBGMCAPRESET +, DBGPLDATABLOCKRECEIVEDAFTEREDS, DBGPLGEN3FRAMINGERRORDETECTED, DBGPLGEN3SYNCHEADERERRORDETECTED, DBGPLINFERREDRXELECTRICALIDLE, DRPDO, DRPRDY, LL2LMMASTERTLPSENT0, LL2LMMASTERTLPSENT1, LL2LMMASTERTLPSENTTLPID0, LL2LMMASTERTLPSENTTLPID1, LL2LMMAXISRXTDATA, LL2LMMAXISRXTUSER, LL2LMMAXISRXTVALID, LL2LMSAXISTXTREADY, MAXISCQTDATA, MAXISCQTKEEP, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP +, MAXISRCTLAST, MAXISRCTUSER, MAXISRCTVALID, MICOMPLETIONRAMREADADDRESSAL, MICOMPLETIONRAMREADADDRESSAU, MICOMPLETIONRAMREADADDRESSBL, MICOMPLETIONRAMREADADDRESSBU, MICOMPLETIONRAMREADENABLEL, MICOMPLETIONRAMREADENABLEU, MICOMPLETIONRAMWRITEADDRESSAL, MICOMPLETIONRAMWRITEADDRESSAU, MICOMPLETIONRAMWRITEADDRESSBL, MICOMPLETIONRAMWRITEADDRESSBU, MICOMPLETIONRAMWRITEDATAL, MICOMPLETIONRAMWRITEDATAU, MICOMPLETIONRAMWRITEENABLEL, MICOMPLETIONRAMWRITEENABLEU, MIREPLAYRAMADDRESS, MIREPLAYRAMREADENABLE, MIREPLAYRAMWRITEDATA, MIREPLAYRAMWRITEENABLE +, MIREQUESTRAMREADADDRESSA, MIREQUESTRAMREADADDRESSB, MIREQUESTRAMREADENABLE, MIREQUESTRAMWRITEADDRESSA, MIREQUESTRAMWRITEADDRESSB, MIREQUESTRAMWRITEDATA, MIREQUESTRAMWRITEENABLE, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM, PCIERQSEQNUMVLD, PCIERQTAG, PCIERQTAGAV, PCIERQTAGVLD, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX0EQCONTROL, PIPERX0EQLPLFFS, PIPERX0EQLPTXPRESET, PIPERX0EQPRESET +, PIPERX0POLARITY, PIPERX1EQCONTROL, PIPERX1EQLPLFFS, PIPERX1EQLPTXPRESET, PIPERX1EQPRESET, PIPERX1POLARITY, PIPERX2EQCONTROL, PIPERX2EQLPLFFS, PIPERX2EQLPTXPRESET, PIPERX2EQPRESET, PIPERX2POLARITY, PIPERX3EQCONTROL, PIPERX3EQLPLFFS, PIPERX3EQLPTXPRESET, PIPERX3EQPRESET, PIPERX3POLARITY, PIPERX4EQCONTROL, PIPERX4EQLPLFFS, PIPERX4EQLPTXPRESET, PIPERX4EQPRESET, PIPERX4POLARITY +, PIPERX5EQCONTROL, PIPERX5EQLPLFFS, PIPERX5EQLPTXPRESET, PIPERX5EQPRESET, PIPERX5POLARITY, PIPERX6EQCONTROL, PIPERX6EQLPLFFS, PIPERX6EQLPTXPRESET, PIPERX6EQPRESET, PIPERX6POLARITY, PIPERX7EQCONTROL, PIPERX7EQLPLFFS, PIPERX7EQLPTXPRESET, PIPERX7EQPRESET, PIPERX7POLARITY, PIPETX0CHARISK, PIPETX0COMPLIANCE, PIPETX0DATA, PIPETX0DATAVALID, PIPETX0DEEMPH, PIPETX0ELECIDLE +, PIPETX0EQCONTROL, PIPETX0EQDEEMPH, PIPETX0EQPRESET, PIPETX0MARGIN, PIPETX0POWERDOWN, PIPETX0RATE, PIPETX0RCVRDET, PIPETX0RESET, PIPETX0STARTBLOCK, PIPETX0SWING, PIPETX0SYNCHEADER, PIPETX1CHARISK, PIPETX1COMPLIANCE, PIPETX1DATA, PIPETX1DATAVALID, PIPETX1DEEMPH, PIPETX1ELECIDLE, PIPETX1EQCONTROL, PIPETX1EQDEEMPH, PIPETX1EQPRESET, PIPETX1MARGIN +, PIPETX1POWERDOWN, PIPETX1RATE, PIPETX1RCVRDET, PIPETX1RESET, PIPETX1STARTBLOCK, PIPETX1SWING, PIPETX1SYNCHEADER, PIPETX2CHARISK, PIPETX2COMPLIANCE, PIPETX2DATA, PIPETX2DATAVALID, PIPETX2DEEMPH, PIPETX2ELECIDLE, PIPETX2EQCONTROL, PIPETX2EQDEEMPH, PIPETX2EQPRESET, PIPETX2MARGIN, PIPETX2POWERDOWN, PIPETX2RATE, PIPETX2RCVRDET, PIPETX2RESET +, PIPETX2STARTBLOCK, PIPETX2SWING, PIPETX2SYNCHEADER, PIPETX3CHARISK, PIPETX3COMPLIANCE, PIPETX3DATA, PIPETX3DATAVALID, PIPETX3DEEMPH, PIPETX3ELECIDLE, PIPETX3EQCONTROL, PIPETX3EQDEEMPH, PIPETX3EQPRESET, PIPETX3MARGIN, PIPETX3POWERDOWN, PIPETX3RATE, PIPETX3RCVRDET, PIPETX3RESET, PIPETX3STARTBLOCK, PIPETX3SWING, PIPETX3SYNCHEADER, PIPETX4CHARISK +, PIPETX4COMPLIANCE, PIPETX4DATA, PIPETX4DATAVALID, PIPETX4DEEMPH, PIPETX4ELECIDLE, PIPETX4EQCONTROL, PIPETX4EQDEEMPH, PIPETX4EQPRESET, PIPETX4MARGIN, PIPETX4POWERDOWN, PIPETX4RATE, PIPETX4RCVRDET, PIPETX4RESET, PIPETX4STARTBLOCK, PIPETX4SWING, PIPETX4SYNCHEADER, PIPETX5CHARISK, PIPETX5COMPLIANCE, PIPETX5DATA, PIPETX5DATAVALID, PIPETX5DEEMPH +, PIPETX5ELECIDLE, PIPETX5EQCONTROL, PIPETX5EQDEEMPH, PIPETX5EQPRESET, PIPETX5MARGIN, PIPETX5POWERDOWN, PIPETX5RATE, PIPETX5RCVRDET, PIPETX5RESET, PIPETX5STARTBLOCK, PIPETX5SWING, PIPETX5SYNCHEADER, PIPETX6CHARISK, PIPETX6COMPLIANCE, PIPETX6DATA, PIPETX6DATAVALID, PIPETX6DEEMPH, PIPETX6ELECIDLE, PIPETX6EQCONTROL, PIPETX6EQDEEMPH, PIPETX6EQPRESET +, PIPETX6MARGIN, PIPETX6POWERDOWN, PIPETX6RATE, PIPETX6RCVRDET, PIPETX6RESET, PIPETX6STARTBLOCK, PIPETX6SWING, PIPETX6SYNCHEADER, PIPETX7CHARISK, PIPETX7COMPLIANCE, PIPETX7DATA, PIPETX7DATAVALID, PIPETX7DEEMPH, PIPETX7ELECIDLE, PIPETX7EQCONTROL, PIPETX7EQDEEMPH, PIPETX7EQPRESET, PIPETX7MARGIN, PIPETX7POWERDOWN, PIPETX7RATE, PIPETX7RCVRDET +, PIPETX7RESET, PIPETX7STARTBLOCK, PIPETX7SWING, PIPETX7SYNCHEADER, PLEQINPROGRESS, PLEQPHASE, SAXISCCTREADY, SAXISRQTREADY, SPAREOUT, CFGCONFIGSPACEENABLE, CFGDEVID, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL +, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTREAD +, CFGMGMTTYPE1CFGREGACCESS, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA, CFGMSGTRANSMITTYPE, CFGPERFUNCSTATUSCONTROL, CFGPERFUNCTIONNUMBER, CFGPERFUNCTIONOUTPUTREQUEST, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGREVID, CFGSUBSYSID, CFGSUBSYSVENDID, CFGTPHSTTREADDATA, CFGTPHSTTREADDATAVALID, CFGVENDID, CFGVFFLRDONE, CONFMCAPREQUESTBYCONF, CONFREQDATA, CONFREQREGNUM +, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKMICOMPLETIONRAML, CORECLKMICOMPLETIONRAMU, CORECLKMIREPLAYRAM, CORECLKMIREQUESTRAM, DBGCFGLOCALMGMTREGOVERRIDE, DBGDATASEL, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, LL2LMSAXISTXTUSER, LL2LMSAXISTXTVALID, LL2LMTXTLPID0, LL2LMTXTLPID1, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK +, MCAPPERST0B, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MICOMPLETIONRAMREADDATA, MIREPLAYRAMREADDATA, MIREQUESTRAMREADDATA, PCIECQNPREQ, PIPECLK, PIPEEQFS, PIPEEQLF, PIPERESETN, PIPERX0CHARISK, PIPERX0DATA, PIPERX0DATAVALID, PIPERX0ELECIDLE, PIPERX0EQDONE, PIPERX0EQLPADAPTDONE, PIPERX0EQLPLFFSSEL, PIPERX0EQLPNEWTXCOEFFORPRESET, PIPERX0PHYSTATUS +, PIPERX0STARTBLOCK, PIPERX0STATUS, PIPERX0SYNCHEADER, PIPERX0VALID, PIPERX1CHARISK, PIPERX1DATA, PIPERX1DATAVALID, PIPERX1ELECIDLE, PIPERX1EQDONE, PIPERX1EQLPADAPTDONE, PIPERX1EQLPLFFSSEL, PIPERX1EQLPNEWTXCOEFFORPRESET, PIPERX1PHYSTATUS, PIPERX1STARTBLOCK, PIPERX1STATUS, PIPERX1SYNCHEADER, PIPERX1VALID, PIPERX2CHARISK, PIPERX2DATA, PIPERX2DATAVALID, PIPERX2ELECIDLE +, PIPERX2EQDONE, PIPERX2EQLPADAPTDONE, PIPERX2EQLPLFFSSEL, PIPERX2EQLPNEWTXCOEFFORPRESET, PIPERX2PHYSTATUS, PIPERX2STARTBLOCK, PIPERX2STATUS, PIPERX2SYNCHEADER, PIPERX2VALID, PIPERX3CHARISK, PIPERX3DATA, PIPERX3DATAVALID, PIPERX3ELECIDLE, PIPERX3EQDONE, PIPERX3EQLPADAPTDONE, PIPERX3EQLPLFFSSEL, PIPERX3EQLPNEWTXCOEFFORPRESET, PIPERX3PHYSTATUS, PIPERX3STARTBLOCK, PIPERX3STATUS, PIPERX3SYNCHEADER +, PIPERX3VALID, PIPERX4CHARISK, PIPERX4DATA, PIPERX4DATAVALID, PIPERX4ELECIDLE, PIPERX4EQDONE, PIPERX4EQLPADAPTDONE, PIPERX4EQLPLFFSSEL, PIPERX4EQLPNEWTXCOEFFORPRESET, PIPERX4PHYSTATUS, PIPERX4STARTBLOCK, PIPERX4STATUS, PIPERX4SYNCHEADER, PIPERX4VALID, PIPERX5CHARISK, PIPERX5DATA, PIPERX5DATAVALID, PIPERX5ELECIDLE, PIPERX5EQDONE, PIPERX5EQLPADAPTDONE, PIPERX5EQLPLFFSSEL +, PIPERX5EQLPNEWTXCOEFFORPRESET, PIPERX5PHYSTATUS, PIPERX5STARTBLOCK, PIPERX5STATUS, PIPERX5SYNCHEADER, PIPERX5VALID, PIPERX6CHARISK, PIPERX6DATA, PIPERX6DATAVALID, PIPERX6ELECIDLE, PIPERX6EQDONE, PIPERX6EQLPADAPTDONE, PIPERX6EQLPLFFSSEL, PIPERX6EQLPNEWTXCOEFFORPRESET, PIPERX6PHYSTATUS, PIPERX6STARTBLOCK, PIPERX6STATUS, PIPERX6SYNCHEADER, PIPERX6VALID, PIPERX7CHARISK, PIPERX7DATA +, PIPERX7DATAVALID, PIPERX7ELECIDLE, PIPERX7EQDONE, PIPERX7EQLPADAPTDONE, PIPERX7EQLPLFFSSEL, PIPERX7EQLPNEWTXCOEFFORPRESET, PIPERX7PHYSTATUS, PIPERX7STARTBLOCK, PIPERX7STATUS, PIPERX7SYNCHEADER, PIPERX7VALID, PIPETX0EQCOEFF, PIPETX0EQDONE, PIPETX1EQCOEFF, PIPETX1EQDONE, PIPETX2EQCOEFF, PIPETX2EQDONE, PIPETX3EQCOEFF, PIPETX3EQDONE, PIPETX4EQCOEFF, PIPETX4EQDONE +, PIPETX5EQCOEFF, PIPETX5EQDONE, PIPETX6EQCOEFF, PIPETX6EQDONE, PIPETX7EQCOEFF, PIPETX7EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, RESETN, SAXISCCTDATA, SAXISCCTKEEP, SAXISCCTLAST, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, SPAREIN, USERCLK +); parameter ARI_CAP_ENABLE = "FALSE"; parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; @@ -24004,7 +24343,40 @@ module PCIE_3_1 (...); input USERCLK; endmodule -module PCIE40E4 (...); +module PCIE40E4(AXIUSEROUT, CFGBUSNUMBER, CFGCURRENTSPEED, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE, CFGFUNCTIONSTATUS +, CFGHOTRESETOUT, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXVECPENDINGSTATUS, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROROUT, CFGLOCALERRORVALID, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA, CFGMGMTREADWRITEDONE, CFGMSGRECEIVED +, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGMSIXRAMADDRESS, CFGMSIXRAMREADENABLE, CFGMSIXRAMWRITEBYTEENABLE, CFGMSIXRAMWRITEDATA, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGRXPMSTATE, CFGTPHRAMADDRESS, CFGTPHRAMREADENABLE, CFGTPHRAMWRITEBYTEENABLE, CFGTPHRAMWRITEDATA, CFGTPHREQUESTERENABLE, CFGTPHSTMODE +, CFGTXPMSTATE, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGCTRL0OUT, DBGCTRL1OUT, DBGDATA0OUT, DBGDATA1OUT, DRPDO, DRPRDY, MAXISCQTDATA, MAXISCQTKEEP, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP, MAXISRCTLAST +, MAXISRCTUSER, MAXISRCTVALID, MIREPLAYRAMADDRESS0, MIREPLAYRAMADDRESS1, MIREPLAYRAMREADENABLE0, MIREPLAYRAMREADENABLE1, MIREPLAYRAMWRITEDATA0, MIREPLAYRAMWRITEDATA1, MIREPLAYRAMWRITEENABLE0, MIREPLAYRAMWRITEENABLE1, MIRXCOMPLETIONRAMREADADDRESS0, MIRXCOMPLETIONRAMREADADDRESS1, MIRXCOMPLETIONRAMREADENABLE0, MIRXCOMPLETIONRAMREADENABLE1, MIRXCOMPLETIONRAMWRITEADDRESS0, MIRXCOMPLETIONRAMWRITEADDRESS1, MIRXCOMPLETIONRAMWRITEDATA0, MIRXCOMPLETIONRAMWRITEDATA1, MIRXCOMPLETIONRAMWRITEENABLE0, MIRXCOMPLETIONRAMWRITEENABLE1, MIRXPOSTEDREQUESTRAMREADADDRESS0 +, MIRXPOSTEDREQUESTRAMREADADDRESS1, MIRXPOSTEDREQUESTRAMREADENABLE0, MIRXPOSTEDREQUESTRAMREADENABLE1, MIRXPOSTEDREQUESTRAMWRITEADDRESS0, MIRXPOSTEDREQUESTRAMWRITEADDRESS1, MIRXPOSTEDREQUESTRAMWRITEDATA0, MIRXPOSTEDREQUESTRAMWRITEDATA1, MIRXPOSTEDREQUESTRAMWRITEENABLE0, MIRXPOSTEDREQUESTRAMWRITEENABLE1, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM0, PCIERQSEQNUM1, PCIERQSEQNUMVLD0, PCIERQSEQNUMVLD1, PCIERQTAG0, PCIERQTAG1, PCIERQTAGAV, PCIERQTAGVLD0, PCIERQTAGVLD1 +, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX00EQCONTROL, PIPERX00POLARITY, PIPERX01EQCONTROL, PIPERX01POLARITY, PIPERX02EQCONTROL, PIPERX02POLARITY, PIPERX03EQCONTROL, PIPERX03POLARITY, PIPERX04EQCONTROL, PIPERX04POLARITY, PIPERX05EQCONTROL, PIPERX05POLARITY, PIPERX06EQCONTROL, PIPERX06POLARITY, PIPERX07EQCONTROL, PIPERX07POLARITY, PIPERX08EQCONTROL, PIPERX08POLARITY, PIPERX09EQCONTROL +, PIPERX09POLARITY, PIPERX10EQCONTROL, PIPERX10POLARITY, PIPERX11EQCONTROL, PIPERX11POLARITY, PIPERX12EQCONTROL, PIPERX12POLARITY, PIPERX13EQCONTROL, PIPERX13POLARITY, PIPERX14EQCONTROL, PIPERX14POLARITY, PIPERX15EQCONTROL, PIPERX15POLARITY, PIPERXEQLPLFFS, PIPERXEQLPTXPRESET, PIPETX00CHARISK, PIPETX00COMPLIANCE, PIPETX00DATA, PIPETX00DATAVALID, PIPETX00ELECIDLE, PIPETX00EQCONTROL +, PIPETX00EQDEEMPH, PIPETX00POWERDOWN, PIPETX00STARTBLOCK, PIPETX00SYNCHEADER, PIPETX01CHARISK, PIPETX01COMPLIANCE, PIPETX01DATA, PIPETX01DATAVALID, PIPETX01ELECIDLE, PIPETX01EQCONTROL, PIPETX01EQDEEMPH, PIPETX01POWERDOWN, PIPETX01STARTBLOCK, PIPETX01SYNCHEADER, PIPETX02CHARISK, PIPETX02COMPLIANCE, PIPETX02DATA, PIPETX02DATAVALID, PIPETX02ELECIDLE, PIPETX02EQCONTROL, PIPETX02EQDEEMPH +, PIPETX02POWERDOWN, PIPETX02STARTBLOCK, PIPETX02SYNCHEADER, PIPETX03CHARISK, PIPETX03COMPLIANCE, PIPETX03DATA, PIPETX03DATAVALID, PIPETX03ELECIDLE, PIPETX03EQCONTROL, PIPETX03EQDEEMPH, PIPETX03POWERDOWN, PIPETX03STARTBLOCK, PIPETX03SYNCHEADER, PIPETX04CHARISK, PIPETX04COMPLIANCE, PIPETX04DATA, PIPETX04DATAVALID, PIPETX04ELECIDLE, PIPETX04EQCONTROL, PIPETX04EQDEEMPH, PIPETX04POWERDOWN +, PIPETX04STARTBLOCK, PIPETX04SYNCHEADER, PIPETX05CHARISK, PIPETX05COMPLIANCE, PIPETX05DATA, PIPETX05DATAVALID, PIPETX05ELECIDLE, PIPETX05EQCONTROL, PIPETX05EQDEEMPH, PIPETX05POWERDOWN, PIPETX05STARTBLOCK, PIPETX05SYNCHEADER, PIPETX06CHARISK, PIPETX06COMPLIANCE, PIPETX06DATA, PIPETX06DATAVALID, PIPETX06ELECIDLE, PIPETX06EQCONTROL, PIPETX06EQDEEMPH, PIPETX06POWERDOWN, PIPETX06STARTBLOCK +, PIPETX06SYNCHEADER, PIPETX07CHARISK, PIPETX07COMPLIANCE, PIPETX07DATA, PIPETX07DATAVALID, PIPETX07ELECIDLE, PIPETX07EQCONTROL, PIPETX07EQDEEMPH, PIPETX07POWERDOWN, PIPETX07STARTBLOCK, PIPETX07SYNCHEADER, PIPETX08CHARISK, PIPETX08COMPLIANCE, PIPETX08DATA, PIPETX08DATAVALID, PIPETX08ELECIDLE, PIPETX08EQCONTROL, PIPETX08EQDEEMPH, PIPETX08POWERDOWN, PIPETX08STARTBLOCK, PIPETX08SYNCHEADER +, PIPETX09CHARISK, PIPETX09COMPLIANCE, PIPETX09DATA, PIPETX09DATAVALID, PIPETX09ELECIDLE, PIPETX09EQCONTROL, PIPETX09EQDEEMPH, PIPETX09POWERDOWN, PIPETX09STARTBLOCK, PIPETX09SYNCHEADER, PIPETX10CHARISK, PIPETX10COMPLIANCE, PIPETX10DATA, PIPETX10DATAVALID, PIPETX10ELECIDLE, PIPETX10EQCONTROL, PIPETX10EQDEEMPH, PIPETX10POWERDOWN, PIPETX10STARTBLOCK, PIPETX10SYNCHEADER, PIPETX11CHARISK +, PIPETX11COMPLIANCE, PIPETX11DATA, PIPETX11DATAVALID, PIPETX11ELECIDLE, PIPETX11EQCONTROL, PIPETX11EQDEEMPH, PIPETX11POWERDOWN, PIPETX11STARTBLOCK, PIPETX11SYNCHEADER, PIPETX12CHARISK, PIPETX12COMPLIANCE, PIPETX12DATA, PIPETX12DATAVALID, PIPETX12ELECIDLE, PIPETX12EQCONTROL, PIPETX12EQDEEMPH, PIPETX12POWERDOWN, PIPETX12STARTBLOCK, PIPETX12SYNCHEADER, PIPETX13CHARISK, PIPETX13COMPLIANCE +, PIPETX13DATA, PIPETX13DATAVALID, PIPETX13ELECIDLE, PIPETX13EQCONTROL, PIPETX13EQDEEMPH, PIPETX13POWERDOWN, PIPETX13STARTBLOCK, PIPETX13SYNCHEADER, PIPETX14CHARISK, PIPETX14COMPLIANCE, PIPETX14DATA, PIPETX14DATAVALID, PIPETX14ELECIDLE, PIPETX14EQCONTROL, PIPETX14EQDEEMPH, PIPETX14POWERDOWN, PIPETX14STARTBLOCK, PIPETX14SYNCHEADER, PIPETX15CHARISK, PIPETX15COMPLIANCE, PIPETX15DATA +, PIPETX15DATAVALID, PIPETX15ELECIDLE, PIPETX15EQCONTROL, PIPETX15EQDEEMPH, PIPETX15POWERDOWN, PIPETX15STARTBLOCK, PIPETX15SYNCHEADER, PIPETXDEEMPH, PIPETXMARGIN, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, PLEQPHASE, PLGEN34EQMISMATCH, SAXISCCTREADY, SAXISRQTREADY, USERSPAREOUT, AXIUSERIN, CFGCONFIGSPACEENABLE +, CFGDEVIDPF0, CFGDEVIDPF1, CFGDEVIDPF2, CFGDEVIDPF3, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS +, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTMSIXVECPENDING, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTDEBUGACCESS, CFGMGMTFUNCTIONNUMBER, CFGMGMTREAD, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA +, CFGMSGTRANSMITTYPE, CFGMSIXRAMREADDATA, CFGPMASPML1ENTRYREJECT, CFGPMASPMTXL0SENTRYDISABLE, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGREVIDPF0, CFGREVIDPF1, CFGREVIDPF2, CFGREVIDPF3, CFGSUBSYSIDPF0, CFGSUBSYSIDPF1, CFGSUBSYSIDPF2, CFGSUBSYSIDPF3, CFGSUBSYSVENDID, CFGTPHRAMREADDATA, CFGVENDID, CFGVFFLRDONE, CFGVFFLRFUNCNUM, CONFMCAPREQUESTBYCONF, CONFREQDATA +, CONFREQREGNUM, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKMIREPLAYRAM0, CORECLKMIREPLAYRAM1, CORECLKMIRXCOMPLETIONRAM0, CORECLKMIRXCOMPLETIONRAM1, CORECLKMIRXPOSTEDREQUESTRAM0, CORECLKMIRXPOSTEDREQUESTRAM1, DBGSEL0, DBGSEL1, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK, MCAPPERST0B +, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MIREPLAYRAMERRCOR, MIREPLAYRAMERRUNCOR, MIREPLAYRAMREADDATA0, MIREPLAYRAMREADDATA1, MIRXCOMPLETIONRAMERRCOR, MIRXCOMPLETIONRAMERRUNCOR, MIRXCOMPLETIONRAMREADDATA0, MIRXCOMPLETIONRAMREADDATA1, MIRXPOSTEDREQUESTRAMERRCOR, MIRXPOSTEDREQUESTRAMERRUNCOR, MIRXPOSTEDREQUESTRAMREADDATA0, MIRXPOSTEDREQUESTRAMREADDATA1, PCIECOMPLDELIVERED, PCIECOMPLDELIVEREDTAG0, PCIECOMPLDELIVEREDTAG1, PCIECQNPREQ, PCIECQNPUSERCREDITRCVD, PCIECQPIPELINEEMPTY +, PCIEPOSTEDREQDELIVERED, PIPECLK, PIPECLKEN, PIPEEQFS, PIPEEQLF, PIPERESETN, PIPERX00CHARISK, PIPERX00DATA, PIPERX00DATAVALID, PIPERX00ELECIDLE, PIPERX00EQDONE, PIPERX00EQLPADAPTDONE, PIPERX00EQLPLFFSSEL, PIPERX00EQLPNEWTXCOEFFORPRESET, PIPERX00PHYSTATUS, PIPERX00STARTBLOCK, PIPERX00STATUS, PIPERX00SYNCHEADER, PIPERX00VALID, PIPERX01CHARISK, PIPERX01DATA +, PIPERX01DATAVALID, PIPERX01ELECIDLE, PIPERX01EQDONE, PIPERX01EQLPADAPTDONE, PIPERX01EQLPLFFSSEL, PIPERX01EQLPNEWTXCOEFFORPRESET, PIPERX01PHYSTATUS, PIPERX01STARTBLOCK, PIPERX01STATUS, PIPERX01SYNCHEADER, PIPERX01VALID, PIPERX02CHARISK, PIPERX02DATA, PIPERX02DATAVALID, PIPERX02ELECIDLE, PIPERX02EQDONE, PIPERX02EQLPADAPTDONE, PIPERX02EQLPLFFSSEL, PIPERX02EQLPNEWTXCOEFFORPRESET, PIPERX02PHYSTATUS, PIPERX02STARTBLOCK +, PIPERX02STATUS, PIPERX02SYNCHEADER, PIPERX02VALID, PIPERX03CHARISK, PIPERX03DATA, PIPERX03DATAVALID, PIPERX03ELECIDLE, PIPERX03EQDONE, PIPERX03EQLPADAPTDONE, PIPERX03EQLPLFFSSEL, PIPERX03EQLPNEWTXCOEFFORPRESET, PIPERX03PHYSTATUS, PIPERX03STARTBLOCK, PIPERX03STATUS, PIPERX03SYNCHEADER, PIPERX03VALID, PIPERX04CHARISK, PIPERX04DATA, PIPERX04DATAVALID, PIPERX04ELECIDLE, PIPERX04EQDONE +, PIPERX04EQLPADAPTDONE, PIPERX04EQLPLFFSSEL, PIPERX04EQLPNEWTXCOEFFORPRESET, PIPERX04PHYSTATUS, PIPERX04STARTBLOCK, PIPERX04STATUS, PIPERX04SYNCHEADER, PIPERX04VALID, PIPERX05CHARISK, PIPERX05DATA, PIPERX05DATAVALID, PIPERX05ELECIDLE, PIPERX05EQDONE, PIPERX05EQLPADAPTDONE, PIPERX05EQLPLFFSSEL, PIPERX05EQLPNEWTXCOEFFORPRESET, PIPERX05PHYSTATUS, PIPERX05STARTBLOCK, PIPERX05STATUS, PIPERX05SYNCHEADER, PIPERX05VALID +, PIPERX06CHARISK, PIPERX06DATA, PIPERX06DATAVALID, PIPERX06ELECIDLE, PIPERX06EQDONE, PIPERX06EQLPADAPTDONE, PIPERX06EQLPLFFSSEL, PIPERX06EQLPNEWTXCOEFFORPRESET, PIPERX06PHYSTATUS, PIPERX06STARTBLOCK, PIPERX06STATUS, PIPERX06SYNCHEADER, PIPERX06VALID, PIPERX07CHARISK, PIPERX07DATA, PIPERX07DATAVALID, PIPERX07ELECIDLE, PIPERX07EQDONE, PIPERX07EQLPADAPTDONE, PIPERX07EQLPLFFSSEL, PIPERX07EQLPNEWTXCOEFFORPRESET +, PIPERX07PHYSTATUS, PIPERX07STARTBLOCK, PIPERX07STATUS, PIPERX07SYNCHEADER, PIPERX07VALID, PIPERX08CHARISK, PIPERX08DATA, PIPERX08DATAVALID, PIPERX08ELECIDLE, PIPERX08EQDONE, PIPERX08EQLPADAPTDONE, PIPERX08EQLPLFFSSEL, PIPERX08EQLPNEWTXCOEFFORPRESET, PIPERX08PHYSTATUS, PIPERX08STARTBLOCK, PIPERX08STATUS, PIPERX08SYNCHEADER, PIPERX08VALID, PIPERX09CHARISK, PIPERX09DATA, PIPERX09DATAVALID +, PIPERX09ELECIDLE, PIPERX09EQDONE, PIPERX09EQLPADAPTDONE, PIPERX09EQLPLFFSSEL, PIPERX09EQLPNEWTXCOEFFORPRESET, PIPERX09PHYSTATUS, PIPERX09STARTBLOCK, PIPERX09STATUS, PIPERX09SYNCHEADER, PIPERX09VALID, PIPERX10CHARISK, PIPERX10DATA, PIPERX10DATAVALID, PIPERX10ELECIDLE, PIPERX10EQDONE, PIPERX10EQLPADAPTDONE, PIPERX10EQLPLFFSSEL, PIPERX10EQLPNEWTXCOEFFORPRESET, PIPERX10PHYSTATUS, PIPERX10STARTBLOCK, PIPERX10STATUS +, PIPERX10SYNCHEADER, PIPERX10VALID, PIPERX11CHARISK, PIPERX11DATA, PIPERX11DATAVALID, PIPERX11ELECIDLE, PIPERX11EQDONE, PIPERX11EQLPADAPTDONE, PIPERX11EQLPLFFSSEL, PIPERX11EQLPNEWTXCOEFFORPRESET, PIPERX11PHYSTATUS, PIPERX11STARTBLOCK, PIPERX11STATUS, PIPERX11SYNCHEADER, PIPERX11VALID, PIPERX12CHARISK, PIPERX12DATA, PIPERX12DATAVALID, PIPERX12ELECIDLE, PIPERX12EQDONE, PIPERX12EQLPADAPTDONE +, PIPERX12EQLPLFFSSEL, PIPERX12EQLPNEWTXCOEFFORPRESET, PIPERX12PHYSTATUS, PIPERX12STARTBLOCK, PIPERX12STATUS, PIPERX12SYNCHEADER, PIPERX12VALID, PIPERX13CHARISK, PIPERX13DATA, PIPERX13DATAVALID, PIPERX13ELECIDLE, PIPERX13EQDONE, PIPERX13EQLPADAPTDONE, PIPERX13EQLPLFFSSEL, PIPERX13EQLPNEWTXCOEFFORPRESET, PIPERX13PHYSTATUS, PIPERX13STARTBLOCK, PIPERX13STATUS, PIPERX13SYNCHEADER, PIPERX13VALID, PIPERX14CHARISK +, PIPERX14DATA, PIPERX14DATAVALID, PIPERX14ELECIDLE, PIPERX14EQDONE, PIPERX14EQLPADAPTDONE, PIPERX14EQLPLFFSSEL, PIPERX14EQLPNEWTXCOEFFORPRESET, PIPERX14PHYSTATUS, PIPERX14STARTBLOCK, PIPERX14STATUS, PIPERX14SYNCHEADER, PIPERX14VALID, PIPERX15CHARISK, PIPERX15DATA, PIPERX15DATAVALID, PIPERX15ELECIDLE, PIPERX15EQDONE, PIPERX15EQLPADAPTDONE, PIPERX15EQLPLFFSSEL, PIPERX15EQLPNEWTXCOEFFORPRESET, PIPERX15PHYSTATUS +, PIPERX15STARTBLOCK, PIPERX15STATUS, PIPERX15SYNCHEADER, PIPERX15VALID, PIPETX00EQCOEFF, PIPETX00EQDONE, PIPETX01EQCOEFF, PIPETX01EQDONE, PIPETX02EQCOEFF, PIPETX02EQDONE, PIPETX03EQCOEFF, PIPETX03EQDONE, PIPETX04EQCOEFF, PIPETX04EQDONE, PIPETX05EQCOEFF, PIPETX05EQDONE, PIPETX06EQCOEFF, PIPETX06EQDONE, PIPETX07EQCOEFF, PIPETX07EQDONE, PIPETX08EQCOEFF +, PIPETX08EQDONE, PIPETX09EQCOEFF, PIPETX09EQDONE, PIPETX10EQCOEFF, PIPETX10EQDONE, PIPETX11EQCOEFF, PIPETX11EQDONE, PIPETX12EQCOEFF, PIPETX12EQDONE, PIPETX13EQCOEFF, PIPETX13EQDONE, PIPETX14EQCOEFF, PIPETX14EQDONE, PIPETX15EQCOEFF, PIPETX15EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, PLGEN34REDOEQSPEED, PLGEN34REDOEQUALIZATION, RESETN, SAXISCCTDATA +, SAXISCCTKEEP, SAXISCCTLAST, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, USERCLK, USERCLK2, USERCLKEN, USERSPAREIN); parameter ARI_CAP_ENABLE = "FALSE"; parameter AUTO_FLR_RESPONSE = "FALSE"; parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; @@ -25233,7 +25605,41 @@ module PCIE40E4 (...); input [31:0] USERSPAREIN; endmodule -module PCIE4CE4 (...); +module PCIE4CE4(AXIUSEROUT, CCIXTXCREDIT, CFGBUSNUMBER, CFGCURRENTSPEED, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE +, CFGFUNCTIONSTATUS, CFGHOTRESETOUT, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXVECPENDINGSTATUS, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROROUT, CFGLOCALERRORVALID, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA, CFGMGMTREADWRITEDONE +, CFGMSGRECEIVED, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGMSIXRAMADDRESS, CFGMSIXRAMREADENABLE, CFGMSIXRAMWRITEBYTEENABLE, CFGMSIXRAMWRITEDATA, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGRXPMSTATE, CFGTPHRAMADDRESS, CFGTPHRAMREADENABLE, CFGTPHRAMWRITEBYTEENABLE, CFGTPHRAMWRITEDATA, CFGTPHREQUESTERENABLE +, CFGTPHSTMODE, CFGTXPMSTATE, CFGVC1ENABLE, CFGVC1NEGOTIATIONPENDING, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGCCIXOUT, DBGCTRL0OUT, DBGCTRL1OUT, DBGDATA0OUT, DBGDATA1OUT, DRPDO, DRPRDY, MAXISCCIXRXTUSER, MAXISCCIXRXTVALID, MAXISCQTDATA, MAXISCQTKEEP +, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP, MAXISRCTLAST, MAXISRCTUSER, MAXISRCTVALID, MIREPLAYRAMADDRESS0, MIREPLAYRAMADDRESS1, MIREPLAYRAMREADENABLE0, MIREPLAYRAMREADENABLE1, MIREPLAYRAMWRITEDATA0, MIREPLAYRAMWRITEDATA1, MIREPLAYRAMWRITEENABLE0, MIREPLAYRAMWRITEENABLE1, MIRXCOMPLETIONRAMREADADDRESS0, MIRXCOMPLETIONRAMREADADDRESS1, MIRXCOMPLETIONRAMREADENABLE0, MIRXCOMPLETIONRAMREADENABLE1, MIRXCOMPLETIONRAMWRITEADDRESS0 +, MIRXCOMPLETIONRAMWRITEADDRESS1, MIRXCOMPLETIONRAMWRITEDATA0, MIRXCOMPLETIONRAMWRITEDATA1, MIRXCOMPLETIONRAMWRITEENABLE0, MIRXCOMPLETIONRAMWRITEENABLE1, MIRXPOSTEDREQUESTRAMREADADDRESS0, MIRXPOSTEDREQUESTRAMREADADDRESS1, MIRXPOSTEDREQUESTRAMREADENABLE0, MIRXPOSTEDREQUESTRAMREADENABLE1, MIRXPOSTEDREQUESTRAMWRITEADDRESS0, MIRXPOSTEDREQUESTRAMWRITEADDRESS1, MIRXPOSTEDREQUESTRAMWRITEDATA0, MIRXPOSTEDREQUESTRAMWRITEDATA1, MIRXPOSTEDREQUESTRAMWRITEENABLE0, MIRXPOSTEDREQUESTRAMWRITEENABLE1, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM0, PCIERQSEQNUM1, PCIERQSEQNUMVLD0 +, PCIERQSEQNUMVLD1, PCIERQTAG0, PCIERQTAG1, PCIERQTAGAV, PCIERQTAGVLD0, PCIERQTAGVLD1, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX00EQCONTROL, PIPERX00POLARITY, PIPERX01EQCONTROL, PIPERX01POLARITY, PIPERX02EQCONTROL, PIPERX02POLARITY, PIPERX03EQCONTROL, PIPERX03POLARITY, PIPERX04EQCONTROL, PIPERX04POLARITY, PIPERX05EQCONTROL, PIPERX05POLARITY, PIPERX06EQCONTROL +, PIPERX06POLARITY, PIPERX07EQCONTROL, PIPERX07POLARITY, PIPERX08EQCONTROL, PIPERX08POLARITY, PIPERX09EQCONTROL, PIPERX09POLARITY, PIPERX10EQCONTROL, PIPERX10POLARITY, PIPERX11EQCONTROL, PIPERX11POLARITY, PIPERX12EQCONTROL, PIPERX12POLARITY, PIPERX13EQCONTROL, PIPERX13POLARITY, PIPERX14EQCONTROL, PIPERX14POLARITY, PIPERX15EQCONTROL, PIPERX15POLARITY, PIPERXEQLPLFFS, PIPERXEQLPTXPRESET +, PIPETX00CHARISK, PIPETX00COMPLIANCE, PIPETX00DATA, PIPETX00DATAVALID, PIPETX00ELECIDLE, PIPETX00EQCONTROL, PIPETX00EQDEEMPH, PIPETX00POWERDOWN, PIPETX00STARTBLOCK, PIPETX00SYNCHEADER, PIPETX01CHARISK, PIPETX01COMPLIANCE, PIPETX01DATA, PIPETX01DATAVALID, PIPETX01ELECIDLE, PIPETX01EQCONTROL, PIPETX01EQDEEMPH, PIPETX01POWERDOWN, PIPETX01STARTBLOCK, PIPETX01SYNCHEADER, PIPETX02CHARISK +, PIPETX02COMPLIANCE, PIPETX02DATA, PIPETX02DATAVALID, PIPETX02ELECIDLE, PIPETX02EQCONTROL, PIPETX02EQDEEMPH, PIPETX02POWERDOWN, PIPETX02STARTBLOCK, PIPETX02SYNCHEADER, PIPETX03CHARISK, PIPETX03COMPLIANCE, PIPETX03DATA, PIPETX03DATAVALID, PIPETX03ELECIDLE, PIPETX03EQCONTROL, PIPETX03EQDEEMPH, PIPETX03POWERDOWN, PIPETX03STARTBLOCK, PIPETX03SYNCHEADER, PIPETX04CHARISK, PIPETX04COMPLIANCE +, PIPETX04DATA, PIPETX04DATAVALID, PIPETX04ELECIDLE, PIPETX04EQCONTROL, PIPETX04EQDEEMPH, PIPETX04POWERDOWN, PIPETX04STARTBLOCK, PIPETX04SYNCHEADER, PIPETX05CHARISK, PIPETX05COMPLIANCE, PIPETX05DATA, PIPETX05DATAVALID, PIPETX05ELECIDLE, PIPETX05EQCONTROL, PIPETX05EQDEEMPH, PIPETX05POWERDOWN, PIPETX05STARTBLOCK, PIPETX05SYNCHEADER, PIPETX06CHARISK, PIPETX06COMPLIANCE, PIPETX06DATA +, PIPETX06DATAVALID, PIPETX06ELECIDLE, PIPETX06EQCONTROL, PIPETX06EQDEEMPH, PIPETX06POWERDOWN, PIPETX06STARTBLOCK, PIPETX06SYNCHEADER, PIPETX07CHARISK, PIPETX07COMPLIANCE, PIPETX07DATA, PIPETX07DATAVALID, PIPETX07ELECIDLE, PIPETX07EQCONTROL, PIPETX07EQDEEMPH, PIPETX07POWERDOWN, PIPETX07STARTBLOCK, PIPETX07SYNCHEADER, PIPETX08CHARISK, PIPETX08COMPLIANCE, PIPETX08DATA, PIPETX08DATAVALID +, PIPETX08ELECIDLE, PIPETX08EQCONTROL, PIPETX08EQDEEMPH, PIPETX08POWERDOWN, PIPETX08STARTBLOCK, PIPETX08SYNCHEADER, PIPETX09CHARISK, PIPETX09COMPLIANCE, PIPETX09DATA, PIPETX09DATAVALID, PIPETX09ELECIDLE, PIPETX09EQCONTROL, PIPETX09EQDEEMPH, PIPETX09POWERDOWN, PIPETX09STARTBLOCK, PIPETX09SYNCHEADER, PIPETX10CHARISK, PIPETX10COMPLIANCE, PIPETX10DATA, PIPETX10DATAVALID, PIPETX10ELECIDLE +, PIPETX10EQCONTROL, PIPETX10EQDEEMPH, PIPETX10POWERDOWN, PIPETX10STARTBLOCK, PIPETX10SYNCHEADER, PIPETX11CHARISK, PIPETX11COMPLIANCE, PIPETX11DATA, PIPETX11DATAVALID, PIPETX11ELECIDLE, PIPETX11EQCONTROL, PIPETX11EQDEEMPH, PIPETX11POWERDOWN, PIPETX11STARTBLOCK, PIPETX11SYNCHEADER, PIPETX12CHARISK, PIPETX12COMPLIANCE, PIPETX12DATA, PIPETX12DATAVALID, PIPETX12ELECIDLE, PIPETX12EQCONTROL +, PIPETX12EQDEEMPH, PIPETX12POWERDOWN, PIPETX12STARTBLOCK, PIPETX12SYNCHEADER, PIPETX13CHARISK, PIPETX13COMPLIANCE, PIPETX13DATA, PIPETX13DATAVALID, PIPETX13ELECIDLE, PIPETX13EQCONTROL, PIPETX13EQDEEMPH, PIPETX13POWERDOWN, PIPETX13STARTBLOCK, PIPETX13SYNCHEADER, PIPETX14CHARISK, PIPETX14COMPLIANCE, PIPETX14DATA, PIPETX14DATAVALID, PIPETX14ELECIDLE, PIPETX14EQCONTROL, PIPETX14EQDEEMPH +, PIPETX14POWERDOWN, PIPETX14STARTBLOCK, PIPETX14SYNCHEADER, PIPETX15CHARISK, PIPETX15COMPLIANCE, PIPETX15DATA, PIPETX15DATAVALID, PIPETX15ELECIDLE, PIPETX15EQCONTROL, PIPETX15EQDEEMPH, PIPETX15POWERDOWN, PIPETX15STARTBLOCK, PIPETX15SYNCHEADER, PIPETXDEEMPH, PIPETXMARGIN, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, PLEQPHASE +, PLGEN34EQMISMATCH, SAXISCCTREADY, SAXISRQTREADY, USERSPAREOUT, AXIUSERIN, CCIXOPTIMIZEDTLPTXANDRXENABLE, CCIXRXCORRECTABLEERRORDETECTED, CCIXRXFIFOOVERFLOW, CCIXRXTLPFORWARDED0, CCIXRXTLPFORWARDED1, CCIXRXTLPFORWARDEDLENGTH0, CCIXRXTLPFORWARDEDLENGTH1, CCIXRXUNCORRECTABLEERRORDETECTED, CFGCONFIGSPACEENABLE, CFGDEVIDPF0, CFGDEVIDPF1, CFGDEVIDPF2, CFGDEVIDPF3, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER +, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL, CFGFCVCSEL, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE +, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTMSIXVECPENDING, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTDEBUGACCESS, CFGMGMTFUNCTIONNUMBER, CFGMGMTREAD, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA, CFGMSGTRANSMITTYPE, CFGMSIXRAMREADDATA, CFGPMASPML1ENTRYREJECT, CFGPMASPMTXL0SENTRYDISABLE, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY +, CFGREVIDPF0, CFGREVIDPF1, CFGREVIDPF2, CFGREVIDPF3, CFGSUBSYSIDPF0, CFGSUBSYSIDPF1, CFGSUBSYSIDPF2, CFGSUBSYSIDPF3, CFGSUBSYSVENDID, CFGTPHRAMREADDATA, CFGVENDID, CFGVFFLRDONE, CFGVFFLRFUNCNUM, CONFMCAPREQUESTBYCONF, CONFREQDATA, CONFREQREGNUM, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKCCIX, CORECLKMIREPLAYRAM0 +, CORECLKMIREPLAYRAM1, CORECLKMIRXCOMPLETIONRAM0, CORECLKMIRXCOMPLETIONRAM1, CORECLKMIRXPOSTEDREQUESTRAM0, CORECLKMIRXPOSTEDREQUESTRAM1, DBGSEL0, DBGSEL1, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK, MCAPPERST0B, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MIREPLAYRAMERRCOR, MIREPLAYRAMERRUNCOR +, MIREPLAYRAMREADDATA0, MIREPLAYRAMREADDATA1, MIRXCOMPLETIONRAMERRCOR, MIRXCOMPLETIONRAMERRUNCOR, MIRXCOMPLETIONRAMREADDATA0, MIRXCOMPLETIONRAMREADDATA1, MIRXPOSTEDREQUESTRAMERRCOR, MIRXPOSTEDREQUESTRAMERRUNCOR, MIRXPOSTEDREQUESTRAMREADDATA0, MIRXPOSTEDREQUESTRAMREADDATA1, PCIECOMPLDELIVERED, PCIECOMPLDELIVEREDTAG0, PCIECOMPLDELIVEREDTAG1, PCIECQNPREQ, PCIECQNPUSERCREDITRCVD, PCIECQPIPELINEEMPTY, PCIEPOSTEDREQDELIVERED, PIPECLK, PIPECLKEN, PIPEEQFS, PIPEEQLF +, PIPERESETN, PIPERX00CHARISK, PIPERX00DATA, PIPERX00DATAVALID, PIPERX00ELECIDLE, PIPERX00EQDONE, PIPERX00EQLPADAPTDONE, PIPERX00EQLPLFFSSEL, PIPERX00EQLPNEWTXCOEFFORPRESET, PIPERX00PHYSTATUS, PIPERX00STARTBLOCK, PIPERX00STATUS, PIPERX00SYNCHEADER, PIPERX00VALID, PIPERX01CHARISK, PIPERX01DATA, PIPERX01DATAVALID, PIPERX01ELECIDLE, PIPERX01EQDONE, PIPERX01EQLPADAPTDONE, PIPERX01EQLPLFFSSEL +, PIPERX01EQLPNEWTXCOEFFORPRESET, PIPERX01PHYSTATUS, PIPERX01STARTBLOCK, PIPERX01STATUS, PIPERX01SYNCHEADER, PIPERX01VALID, PIPERX02CHARISK, PIPERX02DATA, PIPERX02DATAVALID, PIPERX02ELECIDLE, PIPERX02EQDONE, PIPERX02EQLPADAPTDONE, PIPERX02EQLPLFFSSEL, PIPERX02EQLPNEWTXCOEFFORPRESET, PIPERX02PHYSTATUS, PIPERX02STARTBLOCK, PIPERX02STATUS, PIPERX02SYNCHEADER, PIPERX02VALID, PIPERX03CHARISK, PIPERX03DATA +, PIPERX03DATAVALID, PIPERX03ELECIDLE, PIPERX03EQDONE, PIPERX03EQLPADAPTDONE, PIPERX03EQLPLFFSSEL, PIPERX03EQLPNEWTXCOEFFORPRESET, PIPERX03PHYSTATUS, PIPERX03STARTBLOCK, PIPERX03STATUS, PIPERX03SYNCHEADER, PIPERX03VALID, PIPERX04CHARISK, PIPERX04DATA, PIPERX04DATAVALID, PIPERX04ELECIDLE, PIPERX04EQDONE, PIPERX04EQLPADAPTDONE, PIPERX04EQLPLFFSSEL, PIPERX04EQLPNEWTXCOEFFORPRESET, PIPERX04PHYSTATUS, PIPERX04STARTBLOCK +, PIPERX04STATUS, PIPERX04SYNCHEADER, PIPERX04VALID, PIPERX05CHARISK, PIPERX05DATA, PIPERX05DATAVALID, PIPERX05ELECIDLE, PIPERX05EQDONE, PIPERX05EQLPADAPTDONE, PIPERX05EQLPLFFSSEL, PIPERX05EQLPNEWTXCOEFFORPRESET, PIPERX05PHYSTATUS, PIPERX05STARTBLOCK, PIPERX05STATUS, PIPERX05SYNCHEADER, PIPERX05VALID, PIPERX06CHARISK, PIPERX06DATA, PIPERX06DATAVALID, PIPERX06ELECIDLE, PIPERX06EQDONE +, PIPERX06EQLPADAPTDONE, PIPERX06EQLPLFFSSEL, PIPERX06EQLPNEWTXCOEFFORPRESET, PIPERX06PHYSTATUS, PIPERX06STARTBLOCK, PIPERX06STATUS, PIPERX06SYNCHEADER, PIPERX06VALID, PIPERX07CHARISK, PIPERX07DATA, PIPERX07DATAVALID, PIPERX07ELECIDLE, PIPERX07EQDONE, PIPERX07EQLPADAPTDONE, PIPERX07EQLPLFFSSEL, PIPERX07EQLPNEWTXCOEFFORPRESET, PIPERX07PHYSTATUS, PIPERX07STARTBLOCK, PIPERX07STATUS, PIPERX07SYNCHEADER, PIPERX07VALID +, PIPERX08CHARISK, PIPERX08DATA, PIPERX08DATAVALID, PIPERX08ELECIDLE, PIPERX08EQDONE, PIPERX08EQLPADAPTDONE, PIPERX08EQLPLFFSSEL, PIPERX08EQLPNEWTXCOEFFORPRESET, PIPERX08PHYSTATUS, PIPERX08STARTBLOCK, PIPERX08STATUS, PIPERX08SYNCHEADER, PIPERX08VALID, PIPERX09CHARISK, PIPERX09DATA, PIPERX09DATAVALID, PIPERX09ELECIDLE, PIPERX09EQDONE, PIPERX09EQLPADAPTDONE, PIPERX09EQLPLFFSSEL, PIPERX09EQLPNEWTXCOEFFORPRESET +, PIPERX09PHYSTATUS, PIPERX09STARTBLOCK, PIPERX09STATUS, PIPERX09SYNCHEADER, PIPERX09VALID, PIPERX10CHARISK, PIPERX10DATA, PIPERX10DATAVALID, PIPERX10ELECIDLE, PIPERX10EQDONE, PIPERX10EQLPADAPTDONE, PIPERX10EQLPLFFSSEL, PIPERX10EQLPNEWTXCOEFFORPRESET, PIPERX10PHYSTATUS, PIPERX10STARTBLOCK, PIPERX10STATUS, PIPERX10SYNCHEADER, PIPERX10VALID, PIPERX11CHARISK, PIPERX11DATA, PIPERX11DATAVALID +, PIPERX11ELECIDLE, PIPERX11EQDONE, PIPERX11EQLPADAPTDONE, PIPERX11EQLPLFFSSEL, PIPERX11EQLPNEWTXCOEFFORPRESET, PIPERX11PHYSTATUS, PIPERX11STARTBLOCK, PIPERX11STATUS, PIPERX11SYNCHEADER, PIPERX11VALID, PIPERX12CHARISK, PIPERX12DATA, PIPERX12DATAVALID, PIPERX12ELECIDLE, PIPERX12EQDONE, PIPERX12EQLPADAPTDONE, PIPERX12EQLPLFFSSEL, PIPERX12EQLPNEWTXCOEFFORPRESET, PIPERX12PHYSTATUS, PIPERX12STARTBLOCK, PIPERX12STATUS +, PIPERX12SYNCHEADER, PIPERX12VALID, PIPERX13CHARISK, PIPERX13DATA, PIPERX13DATAVALID, PIPERX13ELECIDLE, PIPERX13EQDONE, PIPERX13EQLPADAPTDONE, PIPERX13EQLPLFFSSEL, PIPERX13EQLPNEWTXCOEFFORPRESET, PIPERX13PHYSTATUS, PIPERX13STARTBLOCK, PIPERX13STATUS, PIPERX13SYNCHEADER, PIPERX13VALID, PIPERX14CHARISK, PIPERX14DATA, PIPERX14DATAVALID, PIPERX14ELECIDLE, PIPERX14EQDONE, PIPERX14EQLPADAPTDONE +, PIPERX14EQLPLFFSSEL, PIPERX14EQLPNEWTXCOEFFORPRESET, PIPERX14PHYSTATUS, PIPERX14STARTBLOCK, PIPERX14STATUS, PIPERX14SYNCHEADER, PIPERX14VALID, PIPERX15CHARISK, PIPERX15DATA, PIPERX15DATAVALID, PIPERX15ELECIDLE, PIPERX15EQDONE, PIPERX15EQLPADAPTDONE, PIPERX15EQLPLFFSSEL, PIPERX15EQLPNEWTXCOEFFORPRESET, PIPERX15PHYSTATUS, PIPERX15STARTBLOCK, PIPERX15STATUS, PIPERX15SYNCHEADER, PIPERX15VALID, PIPETX00EQCOEFF +, PIPETX00EQDONE, PIPETX01EQCOEFF, PIPETX01EQDONE, PIPETX02EQCOEFF, PIPETX02EQDONE, PIPETX03EQCOEFF, PIPETX03EQDONE, PIPETX04EQCOEFF, PIPETX04EQDONE, PIPETX05EQCOEFF, PIPETX05EQDONE, PIPETX06EQCOEFF, PIPETX06EQDONE, PIPETX07EQCOEFF, PIPETX07EQDONE, PIPETX08EQCOEFF, PIPETX08EQDONE, PIPETX09EQCOEFF, PIPETX09EQDONE, PIPETX10EQCOEFF, PIPETX10EQDONE +, PIPETX11EQCOEFF, PIPETX11EQDONE, PIPETX12EQCOEFF, PIPETX12EQDONE, PIPETX13EQCOEFF, PIPETX13EQDONE, PIPETX14EQCOEFF, PIPETX14EQDONE, PIPETX15EQCOEFF, PIPETX15EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, PLGEN34REDOEQSPEED, PLGEN34REDOEQUALIZATION, RESETN, SAXISCCIXTXTDATA, SAXISCCIXTXTUSER, SAXISCCIXTXTVALID, SAXISCCTDATA, SAXISCCTKEEP, SAXISCCTLAST +, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, USERCLK, USERCLK2, USERCLKEN, USERSPAREIN); parameter ARI_CAP_ENABLE = "FALSE"; parameter AUTO_FLR_RESPONSE = "FALSE"; parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08; @@ -26539,7 +26945,14 @@ module PCIE4CE4 (...); input [31:0] USERSPAREIN; endmodule -module EMAC (...); +module EMAC(DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXDVREG6, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXGMIIMIICLKOUT, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB +, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXDVREG6, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME +, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXGMIIMIICLKOUT, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL +, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXEN, EMAC1PHYTXER, EMACDCRACK, HOSTMIIMRDY, EMACDCRDBUS, EMAC0CLIENTRXD, EMAC1CLIENTRXD, HOSTRDDATA, EMAC0CLIENTRXSTATS, EMAC1CLIENTRXSTATS, EMAC0PHYTXD, EMAC1PHYTXD, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE +, CLIENTEMAC0TXGMIIMIICLKIN, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXGMIIMIICLKIN, CLIENTEMAC1TXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTREQ, PHYEMAC0COL, PHYEMAC0CRS +, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0RXBUFERR, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCOMMADET, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN +, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1RXBUFERR, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCOMMADET, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, RESET, DCREMACDBUS, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0TXD, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1TXD +, HOSTOPCODE, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXLOSSOFSYNC, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXLOSSOFSYNC, PHYEMAC0RXCLKCORCNT, PHYEMAC1RXCLKCORCNT, HOSTWRDATA, TIEEMAC0UNICASTADDR, TIEEMAC1UNICASTADDR, PHYEMAC0PHYAD, PHYEMAC1PHYAD, TIEEMAC0CONFIGVEC, TIEEMAC1CONFIGVEC, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC1TXIFGDELAY, PHYEMAC0RXD, PHYEMAC1RXD, DCREMACABUS, HOSTADDR); parameter EMAC0_MODE = "RGMII"; parameter EMAC1_MODE = "RGMII"; output DCRHOSTDONEIR; @@ -26711,7 +27124,14 @@ module EMAC (...); input [9:0] HOSTADDR; endmodule -module TEMAC (...); +module TEMAC(DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT +, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC0PHYTXGMIIMIICLKOUT, EMAC0SPEEDIS10100, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATSBYTEVLD +, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK +, EMAC1PHYTXEN, EMAC1PHYTXER, EMAC1PHYTXGMIIMIICLKOUT, EMAC1SPEEDIS10100, EMACDCRACK, HOSTMIIMRDY, EMACDCRDBUS, EMAC0CLIENTRXD, EMAC1CLIENTRXD, HOSTRDDATA, EMAC0CLIENTRXSTATS, EMAC1CLIENTRXSTATS, EMAC0PHYTXD, EMAC1PHYTXD, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE +, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTREQ, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN +, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0RXBUFERR, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCOMMADET, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC0TXGMIIMIICLKIN, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN +, PHYEMAC1MIITXCLK, PHYEMAC1RXBUFERR, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCOMMADET, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, PHYEMAC1TXGMIIMIICLKIN, RESET, DCREMACDBUS, DCREMACABUS, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0TXD, CLIENTEMAC1PAUSEVAL +, CLIENTEMAC1TXD, HOSTOPCODE, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXLOSSOFSYNC, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXLOSSOFSYNC, PHYEMAC0RXCLKCORCNT, PHYEMAC1RXCLKCORCNT, HOSTWRDATA, PHYEMAC0PHYAD, PHYEMAC1PHYAD, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC1TXIFGDELAY, PHYEMAC0RXD, PHYEMAC1RXD, HOSTADDR); parameter EMAC0_1000BASEX_ENABLE = "FALSE"; parameter EMAC0_ADDRFILTER_ENABLE = "FALSE"; parameter EMAC0_BYTEPHY = "FALSE"; @@ -26957,7 +27377,11 @@ module TEMAC (...); input [9:0] HOSTADDR; endmodule -module TEMAC_SINGLE (...); +module TEMAC_SINGLE(DCRHOSTDONEIR, EMACCLIENTANINTERRUPT, EMACCLIENTRXBADFRAME, EMACCLIENTRXCLIENTCLKOUT, EMACCLIENTRXDVLD, EMACCLIENTRXDVLDMSW, EMACCLIENTRXFRAMEDROP, EMACCLIENTRXGOODFRAME, EMACCLIENTRXSTATSBYTEVLD, EMACCLIENTRXSTATSVLD, EMACCLIENTTXACK, EMACCLIENTTXCLIENTCLKOUT, EMACCLIENTTXCOLLISION, EMACCLIENTTXRETRANSMIT, EMACCLIENTTXSTATS, EMACCLIENTTXSTATSBYTEVLD, EMACCLIENTTXSTATSVLD, EMACDCRACK, EMACPHYENCOMMAALIGN, EMACPHYLOOPBACKMSB, EMACPHYMCLKOUT +, EMACPHYMDOUT, EMACPHYMDTRI, EMACPHYMGTRXRESET, EMACPHYMGTTXRESET, EMACPHYPOWERDOWN, EMACPHYSYNCACQSTATUS, EMACPHYTXCHARDISPMODE, EMACPHYTXCHARDISPVAL, EMACPHYTXCHARISK, EMACPHYTXCLK, EMACPHYTXEN, EMACPHYTXER, EMACPHYTXGMIIMIICLKOUT, EMACSPEEDIS10100, HOSTMIIMRDY, EMACDCRDBUS, EMACCLIENTRXD, HOSTRDDATA, EMACCLIENTRXSTATS, EMACPHYTXD, CLIENTEMACDCMLOCKED +, CLIENTEMACPAUSEREQ, CLIENTEMACRXCLIENTCLKIN, CLIENTEMACTXCLIENTCLKIN, CLIENTEMACTXDVLD, CLIENTEMACTXDVLDMSW, CLIENTEMACTXFIRSTBYTE, CLIENTEMACTXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTMIIMSEL, HOSTREQ, PHYEMACCOL, PHYEMACCRS, PHYEMACGTXCLK, PHYEMACMCLKIN, PHYEMACMDIN, PHYEMACMIITXCLK, PHYEMACRXCHARISCOMMA +, PHYEMACRXCHARISK, PHYEMACRXCLK, PHYEMACRXDISPERR, PHYEMACRXDV, PHYEMACRXER, PHYEMACRXNOTINTABLE, PHYEMACRXRUNDISP, PHYEMACSIGNALDET, PHYEMACTXBUFERR, PHYEMACTXGMIIMIICLKIN, RESET, DCREMACDBUS, DCREMACABUS, CLIENTEMACPAUSEVAL, CLIENTEMACTXD, HOSTOPCODE, PHYEMACRXBUFSTATUS, PHYEMACRXCLKCORCNT, HOSTWRDATA, PHYEMACPHYAD, CLIENTEMACTXIFGDELAY +, PHYEMACRXD, HOSTADDR); parameter EMAC_1000BASEX_ENABLE = "FALSE"; parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; parameter EMAC_BYTEPHY = "FALSE"; @@ -27088,7 +27512,24 @@ module TEMAC_SINGLE (...); input [9:0] HOSTADDR; endmodule -module CMAC (...); +module CMAC(DRP_DO, DRP_RDY, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_LANE_ALIGNER_FILL_0, RX_LANE_ALIGNER_FILL_1, RX_LANE_ALIGNER_FILL_10 +, RX_LANE_ALIGNER_FILL_11, RX_LANE_ALIGNER_FILL_12, RX_LANE_ALIGNER_FILL_13, RX_LANE_ALIGNER_FILL_14, RX_LANE_ALIGNER_FILL_15, RX_LANE_ALIGNER_FILL_16, RX_LANE_ALIGNER_FILL_17, RX_LANE_ALIGNER_FILL_18, RX_LANE_ALIGNER_FILL_19, RX_LANE_ALIGNER_FILL_2, RX_LANE_ALIGNER_FILL_3, RX_LANE_ALIGNER_FILL_4, RX_LANE_ALIGNER_FILL_5, RX_LANE_ALIGNER_FILL_6, RX_LANE_ALIGNER_FILL_7, RX_LANE_ALIGNER_FILL_8, RX_LANE_ALIGNER_FILL_9, RX_MTYOUT0, RX_MTYOUT1, RX_MTYOUT2, RX_MTYOUT3 +, RX_PTP_PCSLANE_OUT, RX_PTP_TSTAMP_OUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_CODE, STAT_RX_BAD_FCS, STAT_RX_BAD_PREAMBLE, STAT_RX_BAD_SFD, STAT_RX_BIP_ERR_0, STAT_RX_BIP_ERR_1, STAT_RX_BIP_ERR_10, STAT_RX_BIP_ERR_11, STAT_RX_BIP_ERR_12, STAT_RX_BIP_ERR_13, STAT_RX_BIP_ERR_14, STAT_RX_BIP_ERR_15, STAT_RX_BIP_ERR_16 +, STAT_RX_BIP_ERR_17, STAT_RX_BIP_ERR_18, STAT_RX_BIP_ERR_19, STAT_RX_BIP_ERR_2, STAT_RX_BIP_ERR_3, STAT_RX_BIP_ERR_4, STAT_RX_BIP_ERR_5, STAT_RX_BIP_ERR_6, STAT_RX_BIP_ERR_7, STAT_RX_BIP_ERR_8, STAT_RX_BIP_ERR_9, STAT_RX_BLOCK_LOCK, STAT_RX_BROADCAST, STAT_RX_FRAGMENT, STAT_RX_FRAMING_ERR_0, STAT_RX_FRAMING_ERR_1, STAT_RX_FRAMING_ERR_10, STAT_RX_FRAMING_ERR_11, STAT_RX_FRAMING_ERR_12, STAT_RX_FRAMING_ERR_13, STAT_RX_FRAMING_ERR_14 +, STAT_RX_FRAMING_ERR_15, STAT_RX_FRAMING_ERR_16, STAT_RX_FRAMING_ERR_17, STAT_RX_FRAMING_ERR_18, STAT_RX_FRAMING_ERR_19, STAT_RX_FRAMING_ERR_2, STAT_RX_FRAMING_ERR_3, STAT_RX_FRAMING_ERR_4, STAT_RX_FRAMING_ERR_5, STAT_RX_FRAMING_ERR_6, STAT_RX_FRAMING_ERR_7, STAT_RX_FRAMING_ERR_8, STAT_RX_FRAMING_ERR_9, STAT_RX_FRAMING_ERR_VALID_0, STAT_RX_FRAMING_ERR_VALID_1, STAT_RX_FRAMING_ERR_VALID_10, STAT_RX_FRAMING_ERR_VALID_11, STAT_RX_FRAMING_ERR_VALID_12, STAT_RX_FRAMING_ERR_VALID_13, STAT_RX_FRAMING_ERR_VALID_14, STAT_RX_FRAMING_ERR_VALID_15 +, STAT_RX_FRAMING_ERR_VALID_16, STAT_RX_FRAMING_ERR_VALID_17, STAT_RX_FRAMING_ERR_VALID_18, STAT_RX_FRAMING_ERR_VALID_19, STAT_RX_FRAMING_ERR_VALID_2, STAT_RX_FRAMING_ERR_VALID_3, STAT_RX_FRAMING_ERR_VALID_4, STAT_RX_FRAMING_ERR_VALID_5, STAT_RX_FRAMING_ERR_VALID_6, STAT_RX_FRAMING_ERR_VALID_7, STAT_RX_FRAMING_ERR_VALID_8, STAT_RX_FRAMING_ERR_VALID_9, STAT_RX_GOT_SIGNAL_OS, STAT_RX_HI_BER, STAT_RX_INRANGEERR, STAT_RX_INTERNAL_LOCAL_FAULT, STAT_RX_JABBER, STAT_RX_LANE0_VLM_BIP7, STAT_RX_LANE0_VLM_BIP7_VALID, STAT_RX_LOCAL_FAULT, STAT_RX_MF_ERR +, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MULTICAST, STAT_RX_OVERSIZE, STAT_RX_PACKET_1024_1518_BYTES, STAT_RX_PACKET_128_255_BYTES, STAT_RX_PACKET_1519_1522_BYTES, STAT_RX_PACKET_1523_1548_BYTES, STAT_RX_PACKET_1549_2047_BYTES, STAT_RX_PACKET_2048_4095_BYTES, STAT_RX_PACKET_256_511_BYTES, STAT_RX_PACKET_4096_8191_BYTES, STAT_RX_PACKET_512_1023_BYTES, STAT_RX_PACKET_64_BYTES, STAT_RX_PACKET_65_127_BYTES, STAT_RX_PACKET_8192_9215_BYTES, STAT_RX_PACKET_BAD_FCS, STAT_RX_PACKET_LARGE, STAT_RX_PACKET_SMALL, STAT_RX_PAUSE +, STAT_RX_PAUSE_QUANTA0, STAT_RX_PAUSE_QUANTA1, STAT_RX_PAUSE_QUANTA2, STAT_RX_PAUSE_QUANTA3, STAT_RX_PAUSE_QUANTA4, STAT_RX_PAUSE_QUANTA5, STAT_RX_PAUSE_QUANTA6, STAT_RX_PAUSE_QUANTA7, STAT_RX_PAUSE_QUANTA8, STAT_RX_PAUSE_REQ, STAT_RX_PAUSE_VALID, STAT_RX_RECEIVED_LOCAL_FAULT, STAT_RX_REMOTE_FAULT, STAT_RX_STATUS, STAT_RX_STOMPED_FCS, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR, STAT_RX_TEST_PATTERN_MISMATCH, STAT_RX_TOOLONG, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_GOOD_BYTES +, STAT_RX_TOTAL_GOOD_PACKETS, STAT_RX_TOTAL_PACKETS, STAT_RX_TRUNCATED, STAT_RX_UNDERSIZE, STAT_RX_UNICAST, STAT_RX_USER_PAUSE, STAT_RX_VLAN, STAT_RX_VL_DEMUXED, STAT_RX_VL_NUMBER_0, STAT_RX_VL_NUMBER_1, STAT_RX_VL_NUMBER_10, STAT_RX_VL_NUMBER_11, STAT_RX_VL_NUMBER_12, STAT_RX_VL_NUMBER_13, STAT_RX_VL_NUMBER_14, STAT_RX_VL_NUMBER_15, STAT_RX_VL_NUMBER_16, STAT_RX_VL_NUMBER_17, STAT_RX_VL_NUMBER_18, STAT_RX_VL_NUMBER_19, STAT_RX_VL_NUMBER_2 +, STAT_RX_VL_NUMBER_3, STAT_RX_VL_NUMBER_4, STAT_RX_VL_NUMBER_5, STAT_RX_VL_NUMBER_6, STAT_RX_VL_NUMBER_7, STAT_RX_VL_NUMBER_8, STAT_RX_VL_NUMBER_9, STAT_TX_BAD_FCS, STAT_TX_BROADCAST, STAT_TX_FRAME_ERROR, STAT_TX_LOCAL_FAULT, STAT_TX_MULTICAST, STAT_TX_PACKET_1024_1518_BYTES, STAT_TX_PACKET_128_255_BYTES, STAT_TX_PACKET_1519_1522_BYTES, STAT_TX_PACKET_1523_1548_BYTES, STAT_TX_PACKET_1549_2047_BYTES, STAT_TX_PACKET_2048_4095_BYTES, STAT_TX_PACKET_256_511_BYTES, STAT_TX_PACKET_4096_8191_BYTES, STAT_TX_PACKET_512_1023_BYTES +, STAT_TX_PACKET_64_BYTES, STAT_TX_PACKET_65_127_BYTES, STAT_TX_PACKET_8192_9215_BYTES, STAT_TX_PACKET_LARGE, STAT_TX_PACKET_SMALL, STAT_TX_PAUSE, STAT_TX_PAUSE_VALID, STAT_TX_PTP_FIFO_READ_ERROR, STAT_TX_PTP_FIFO_WRITE_ERROR, STAT_TX_TOTAL_BYTES, STAT_TX_TOTAL_GOOD_BYTES, STAT_TX_TOTAL_GOOD_PACKETS, STAT_TX_TOTAL_PACKETS, STAT_TX_UNICAST, STAT_TX_USER_PAUSE, STAT_TX_VLAN, TX_OVFOUT, TX_PTP_PCSLANE_OUT, TX_PTP_TSTAMP_OUT, TX_PTP_TSTAMP_TAG_OUT, TX_PTP_TSTAMP_VALID_OUT +, TX_RDYOUT, TX_SERDES_ALT_DATA0, TX_SERDES_ALT_DATA1, TX_SERDES_ALT_DATA2, TX_SERDES_ALT_DATA3, TX_SERDES_DATA0, TX_SERDES_DATA1, TX_SERDES_DATA2, TX_SERDES_DATA3, TX_SERDES_DATA4, TX_SERDES_DATA5, TX_SERDES_DATA6, TX_SERDES_DATA7, TX_SERDES_DATA8, TX_SERDES_DATA9, TX_UNFOUT, CTL_CAUI4_MODE, CTL_RX_CHECK_ETYPE_GCP, CTL_RX_CHECK_ETYPE_GPP, CTL_RX_CHECK_ETYPE_PCP, CTL_RX_CHECK_ETYPE_PPP +, CTL_RX_CHECK_MCAST_GCP, CTL_RX_CHECK_MCAST_GPP, CTL_RX_CHECK_MCAST_PCP, CTL_RX_CHECK_MCAST_PPP, CTL_RX_CHECK_OPCODE_GCP, CTL_RX_CHECK_OPCODE_GPP, CTL_RX_CHECK_OPCODE_PCP, CTL_RX_CHECK_OPCODE_PPP, CTL_RX_CHECK_SA_GCP, CTL_RX_CHECK_SA_GPP, CTL_RX_CHECK_SA_PCP, CTL_RX_CHECK_SA_PPP, CTL_RX_CHECK_UCAST_GCP, CTL_RX_CHECK_UCAST_GPP, CTL_RX_CHECK_UCAST_PCP, CTL_RX_CHECK_UCAST_PPP, CTL_RX_ENABLE, CTL_RX_ENABLE_GCP, CTL_RX_ENABLE_GPP, CTL_RX_ENABLE_PCP, CTL_RX_ENABLE_PPP +, CTL_RX_FORCE_RESYNC, CTL_RX_PAUSE_ACK, CTL_RX_PAUSE_ENABLE, CTL_RX_SYSTEMTIMERIN, CTL_RX_TEST_PATTERN, CTL_TX_ENABLE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, CTL_TX_PAUSE_ENABLE, CTL_TX_PAUSE_QUANTA0, CTL_TX_PAUSE_QUANTA1, CTL_TX_PAUSE_QUANTA2, CTL_TX_PAUSE_QUANTA3, CTL_TX_PAUSE_QUANTA4, CTL_TX_PAUSE_QUANTA5, CTL_TX_PAUSE_QUANTA6, CTL_TX_PAUSE_QUANTA7, CTL_TX_PAUSE_QUANTA8, CTL_TX_PAUSE_REFRESH_TIMER0, CTL_TX_PAUSE_REFRESH_TIMER1, CTL_TX_PAUSE_REFRESH_TIMER2 +, CTL_TX_PAUSE_REFRESH_TIMER3, CTL_TX_PAUSE_REFRESH_TIMER4, CTL_TX_PAUSE_REFRESH_TIMER5, CTL_TX_PAUSE_REFRESH_TIMER6, CTL_TX_PAUSE_REFRESH_TIMER7, CTL_TX_PAUSE_REFRESH_TIMER8, CTL_TX_PAUSE_REQ, CTL_TX_PTP_VLANE_ADJUST_MODE, CTL_TX_RESEND_PAUSE, CTL_TX_SEND_IDLE, CTL_TX_SEND_RFI, CTL_TX_SYSTEMTIMERIN, CTL_TX_TEST_PATTERN, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE, RX_CLK, RX_RESET, RX_SERDES_ALT_DATA0 +, RX_SERDES_ALT_DATA1, RX_SERDES_ALT_DATA2, RX_SERDES_ALT_DATA3, RX_SERDES_CLK, RX_SERDES_DATA0, RX_SERDES_DATA1, RX_SERDES_DATA2, RX_SERDES_DATA3, RX_SERDES_DATA4, RX_SERDES_DATA5, RX_SERDES_DATA6, RX_SERDES_DATA7, RX_SERDES_DATA8, RX_SERDES_DATA9, RX_SERDES_RESET, TX_CLK, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0 +, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_PTP_1588OP_IN, TX_PTP_CHKSUM_OFFSET_IN, TX_PTP_RXTSTAMP_IN, TX_PTP_TAG_FIELD_IN, TX_PTP_TSTAMP_OFFSET_IN, TX_PTP_UPD_CHKSUM_IN +, TX_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; parameter CTL_RX_CHECK_ACK = "TRUE"; parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; @@ -27533,7 +27974,26 @@ module CMAC (...); input TX_SOPIN3; endmodule -module CMACE4 (...); +module CMACE4(DRP_DO, DRP_RDY, RSFEC_BYPASS_RX_DOUT, RSFEC_BYPASS_RX_DOUT_CW_START, RSFEC_BYPASS_RX_DOUT_VALID, RSFEC_BYPASS_TX_DOUT, RSFEC_BYPASS_TX_DOUT_CW_START, RSFEC_BYPASS_TX_DOUT_VALID, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0 +, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_LANE_ALIGNER_FILL_0, RX_LANE_ALIGNER_FILL_1, RX_LANE_ALIGNER_FILL_10, RX_LANE_ALIGNER_FILL_11, RX_LANE_ALIGNER_FILL_12, RX_LANE_ALIGNER_FILL_13, RX_LANE_ALIGNER_FILL_14, RX_LANE_ALIGNER_FILL_15, RX_LANE_ALIGNER_FILL_16, RX_LANE_ALIGNER_FILL_17, RX_LANE_ALIGNER_FILL_18, RX_LANE_ALIGNER_FILL_19, RX_LANE_ALIGNER_FILL_2, RX_LANE_ALIGNER_FILL_3, RX_LANE_ALIGNER_FILL_4, RX_LANE_ALIGNER_FILL_5, RX_LANE_ALIGNER_FILL_6, RX_LANE_ALIGNER_FILL_7 +, RX_LANE_ALIGNER_FILL_8, RX_LANE_ALIGNER_FILL_9, RX_MTYOUT0, RX_MTYOUT1, RX_MTYOUT2, RX_MTYOUT3, RX_OTN_BIP8_0, RX_OTN_BIP8_1, RX_OTN_BIP8_2, RX_OTN_BIP8_3, RX_OTN_BIP8_4, RX_OTN_DATA_0, RX_OTN_DATA_1, RX_OTN_DATA_2, RX_OTN_DATA_3, RX_OTN_DATA_4, RX_OTN_ENA, RX_OTN_LANE0, RX_OTN_VLMARKER, RX_PREOUT, RX_PTP_PCSLANE_OUT +, RX_PTP_TSTAMP_OUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_CODE, STAT_RX_BAD_FCS, STAT_RX_BAD_PREAMBLE, STAT_RX_BAD_SFD, STAT_RX_BIP_ERR_0, STAT_RX_BIP_ERR_1, STAT_RX_BIP_ERR_10, STAT_RX_BIP_ERR_11, STAT_RX_BIP_ERR_12, STAT_RX_BIP_ERR_13, STAT_RX_BIP_ERR_14, STAT_RX_BIP_ERR_15, STAT_RX_BIP_ERR_16, STAT_RX_BIP_ERR_17 +, STAT_RX_BIP_ERR_18, STAT_RX_BIP_ERR_19, STAT_RX_BIP_ERR_2, STAT_RX_BIP_ERR_3, STAT_RX_BIP_ERR_4, STAT_RX_BIP_ERR_5, STAT_RX_BIP_ERR_6, STAT_RX_BIP_ERR_7, STAT_RX_BIP_ERR_8, STAT_RX_BIP_ERR_9, STAT_RX_BLOCK_LOCK, STAT_RX_BROADCAST, STAT_RX_FRAGMENT, STAT_RX_FRAMING_ERR_0, STAT_RX_FRAMING_ERR_1, STAT_RX_FRAMING_ERR_10, STAT_RX_FRAMING_ERR_11, STAT_RX_FRAMING_ERR_12, STAT_RX_FRAMING_ERR_13, STAT_RX_FRAMING_ERR_14, STAT_RX_FRAMING_ERR_15 +, STAT_RX_FRAMING_ERR_16, STAT_RX_FRAMING_ERR_17, STAT_RX_FRAMING_ERR_18, STAT_RX_FRAMING_ERR_19, STAT_RX_FRAMING_ERR_2, STAT_RX_FRAMING_ERR_3, STAT_RX_FRAMING_ERR_4, STAT_RX_FRAMING_ERR_5, STAT_RX_FRAMING_ERR_6, STAT_RX_FRAMING_ERR_7, STAT_RX_FRAMING_ERR_8, STAT_RX_FRAMING_ERR_9, STAT_RX_FRAMING_ERR_VALID_0, STAT_RX_FRAMING_ERR_VALID_1, STAT_RX_FRAMING_ERR_VALID_10, STAT_RX_FRAMING_ERR_VALID_11, STAT_RX_FRAMING_ERR_VALID_12, STAT_RX_FRAMING_ERR_VALID_13, STAT_RX_FRAMING_ERR_VALID_14, STAT_RX_FRAMING_ERR_VALID_15, STAT_RX_FRAMING_ERR_VALID_16 +, STAT_RX_FRAMING_ERR_VALID_17, STAT_RX_FRAMING_ERR_VALID_18, STAT_RX_FRAMING_ERR_VALID_19, STAT_RX_FRAMING_ERR_VALID_2, STAT_RX_FRAMING_ERR_VALID_3, STAT_RX_FRAMING_ERR_VALID_4, STAT_RX_FRAMING_ERR_VALID_5, STAT_RX_FRAMING_ERR_VALID_6, STAT_RX_FRAMING_ERR_VALID_7, STAT_RX_FRAMING_ERR_VALID_8, STAT_RX_FRAMING_ERR_VALID_9, STAT_RX_GOT_SIGNAL_OS, STAT_RX_HI_BER, STAT_RX_INRANGEERR, STAT_RX_INTERNAL_LOCAL_FAULT, STAT_RX_JABBER, STAT_RX_LANE0_VLM_BIP7, STAT_RX_LANE0_VLM_BIP7_VALID, STAT_RX_LOCAL_FAULT, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR +, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MULTICAST, STAT_RX_OVERSIZE, STAT_RX_PACKET_1024_1518_BYTES, STAT_RX_PACKET_128_255_BYTES, STAT_RX_PACKET_1519_1522_BYTES, STAT_RX_PACKET_1523_1548_BYTES, STAT_RX_PACKET_1549_2047_BYTES, STAT_RX_PACKET_2048_4095_BYTES, STAT_RX_PACKET_256_511_BYTES, STAT_RX_PACKET_4096_8191_BYTES, STAT_RX_PACKET_512_1023_BYTES, STAT_RX_PACKET_64_BYTES, STAT_RX_PACKET_65_127_BYTES, STAT_RX_PACKET_8192_9215_BYTES, STAT_RX_PACKET_BAD_FCS, STAT_RX_PACKET_LARGE, STAT_RX_PACKET_SMALL, STAT_RX_PAUSE, STAT_RX_PAUSE_QUANTA0 +, STAT_RX_PAUSE_QUANTA1, STAT_RX_PAUSE_QUANTA2, STAT_RX_PAUSE_QUANTA3, STAT_RX_PAUSE_QUANTA4, STAT_RX_PAUSE_QUANTA5, STAT_RX_PAUSE_QUANTA6, STAT_RX_PAUSE_QUANTA7, STAT_RX_PAUSE_QUANTA8, STAT_RX_PAUSE_REQ, STAT_RX_PAUSE_VALID, STAT_RX_RECEIVED_LOCAL_FAULT, STAT_RX_REMOTE_FAULT, STAT_RX_RSFEC_AM_LOCK0, STAT_RX_RSFEC_AM_LOCK1, STAT_RX_RSFEC_AM_LOCK2, STAT_RX_RSFEC_AM_LOCK3, STAT_RX_RSFEC_CORRECTED_CW_INC, STAT_RX_RSFEC_CW_INC, STAT_RX_RSFEC_ERR_COUNT0_INC, STAT_RX_RSFEC_ERR_COUNT1_INC, STAT_RX_RSFEC_ERR_COUNT2_INC +, STAT_RX_RSFEC_ERR_COUNT3_INC, STAT_RX_RSFEC_HI_SER, STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS, STAT_RX_RSFEC_LANE_FILL_0, STAT_RX_RSFEC_LANE_FILL_1, STAT_RX_RSFEC_LANE_FILL_2, STAT_RX_RSFEC_LANE_FILL_3, STAT_RX_RSFEC_LANE_MAPPING, STAT_RX_RSFEC_RSVD, STAT_RX_RSFEC_UNCORRECTED_CW_INC, STAT_RX_STATUS, STAT_RX_STOMPED_FCS, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR, STAT_RX_TEST_PATTERN_MISMATCH, STAT_RX_TOOLONG, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_GOOD_BYTES, STAT_RX_TOTAL_GOOD_PACKETS, STAT_RX_TOTAL_PACKETS, STAT_RX_TRUNCATED +, STAT_RX_UNDERSIZE, STAT_RX_UNICAST, STAT_RX_USER_PAUSE, STAT_RX_VLAN, STAT_RX_VL_DEMUXED, STAT_RX_VL_NUMBER_0, STAT_RX_VL_NUMBER_1, STAT_RX_VL_NUMBER_10, STAT_RX_VL_NUMBER_11, STAT_RX_VL_NUMBER_12, STAT_RX_VL_NUMBER_13, STAT_RX_VL_NUMBER_14, STAT_RX_VL_NUMBER_15, STAT_RX_VL_NUMBER_16, STAT_RX_VL_NUMBER_17, STAT_RX_VL_NUMBER_18, STAT_RX_VL_NUMBER_19, STAT_RX_VL_NUMBER_2, STAT_RX_VL_NUMBER_3, STAT_RX_VL_NUMBER_4, STAT_RX_VL_NUMBER_5 +, STAT_RX_VL_NUMBER_6, STAT_RX_VL_NUMBER_7, STAT_RX_VL_NUMBER_8, STAT_RX_VL_NUMBER_9, STAT_TX_BAD_FCS, STAT_TX_BROADCAST, STAT_TX_FRAME_ERROR, STAT_TX_LOCAL_FAULT, STAT_TX_MULTICAST, STAT_TX_PACKET_1024_1518_BYTES, STAT_TX_PACKET_128_255_BYTES, STAT_TX_PACKET_1519_1522_BYTES, STAT_TX_PACKET_1523_1548_BYTES, STAT_TX_PACKET_1549_2047_BYTES, STAT_TX_PACKET_2048_4095_BYTES, STAT_TX_PACKET_256_511_BYTES, STAT_TX_PACKET_4096_8191_BYTES, STAT_TX_PACKET_512_1023_BYTES, STAT_TX_PACKET_64_BYTES, STAT_TX_PACKET_65_127_BYTES, STAT_TX_PACKET_8192_9215_BYTES +, STAT_TX_PACKET_LARGE, STAT_TX_PACKET_SMALL, STAT_TX_PAUSE, STAT_TX_PAUSE_VALID, STAT_TX_PTP_FIFO_READ_ERROR, STAT_TX_PTP_FIFO_WRITE_ERROR, STAT_TX_TOTAL_BYTES, STAT_TX_TOTAL_GOOD_BYTES, STAT_TX_TOTAL_GOOD_PACKETS, STAT_TX_TOTAL_PACKETS, STAT_TX_UNICAST, STAT_TX_USER_PAUSE, STAT_TX_VLAN, TX_OVFOUT, TX_PTP_PCSLANE_OUT, TX_PTP_TSTAMP_OUT, TX_PTP_TSTAMP_TAG_OUT, TX_PTP_TSTAMP_VALID_OUT, TX_RDYOUT, TX_SERDES_ALT_DATA0, TX_SERDES_ALT_DATA1 +, TX_SERDES_ALT_DATA2, TX_SERDES_ALT_DATA3, TX_SERDES_DATA0, TX_SERDES_DATA1, TX_SERDES_DATA2, TX_SERDES_DATA3, TX_SERDES_DATA4, TX_SERDES_DATA5, TX_SERDES_DATA6, TX_SERDES_DATA7, TX_SERDES_DATA8, TX_SERDES_DATA9, TX_UNFOUT, CTL_CAUI4_MODE, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, CTL_RSFEC_IEEE_ERROR_INDICATION_MODE, CTL_RX_CHECK_ETYPE_GCP, CTL_RX_CHECK_ETYPE_GPP, CTL_RX_CHECK_ETYPE_PCP, CTL_RX_CHECK_ETYPE_PPP, CTL_RX_CHECK_MCAST_GCP +, CTL_RX_CHECK_MCAST_GPP, CTL_RX_CHECK_MCAST_PCP, CTL_RX_CHECK_MCAST_PPP, CTL_RX_CHECK_OPCODE_GCP, CTL_RX_CHECK_OPCODE_GPP, CTL_RX_CHECK_OPCODE_PCP, CTL_RX_CHECK_OPCODE_PPP, CTL_RX_CHECK_SA_GCP, CTL_RX_CHECK_SA_GPP, CTL_RX_CHECK_SA_PCP, CTL_RX_CHECK_SA_PPP, CTL_RX_CHECK_UCAST_GCP, CTL_RX_CHECK_UCAST_GPP, CTL_RX_CHECK_UCAST_PCP, CTL_RX_CHECK_UCAST_PPP, CTL_RX_ENABLE, CTL_RX_ENABLE_GCP, CTL_RX_ENABLE_GPP, CTL_RX_ENABLE_PCP, CTL_RX_ENABLE_PPP, CTL_RX_FORCE_RESYNC +, CTL_RX_PAUSE_ACK, CTL_RX_PAUSE_ENABLE, CTL_RX_RSFEC_ENABLE, CTL_RX_RSFEC_ENABLE_CORRECTION, CTL_RX_RSFEC_ENABLE_INDICATION, CTL_RX_SYSTEMTIMERIN, CTL_RX_TEST_PATTERN, CTL_TX_ENABLE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, CTL_TX_PAUSE_ENABLE, CTL_TX_PAUSE_QUANTA0, CTL_TX_PAUSE_QUANTA1, CTL_TX_PAUSE_QUANTA2, CTL_TX_PAUSE_QUANTA3, CTL_TX_PAUSE_QUANTA4, CTL_TX_PAUSE_QUANTA5, CTL_TX_PAUSE_QUANTA6, CTL_TX_PAUSE_QUANTA7, CTL_TX_PAUSE_QUANTA8, CTL_TX_PAUSE_REFRESH_TIMER0 +, CTL_TX_PAUSE_REFRESH_TIMER1, CTL_TX_PAUSE_REFRESH_TIMER2, CTL_TX_PAUSE_REFRESH_TIMER3, CTL_TX_PAUSE_REFRESH_TIMER4, CTL_TX_PAUSE_REFRESH_TIMER5, CTL_TX_PAUSE_REFRESH_TIMER6, CTL_TX_PAUSE_REFRESH_TIMER7, CTL_TX_PAUSE_REFRESH_TIMER8, CTL_TX_PAUSE_REQ, CTL_TX_PTP_VLANE_ADJUST_MODE, CTL_TX_RESEND_PAUSE, CTL_TX_RSFEC_ENABLE, CTL_TX_SEND_IDLE, CTL_TX_SEND_LFI, CTL_TX_SEND_RFI, CTL_TX_SYSTEMTIMERIN, CTL_TX_TEST_PATTERN, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN +, DRP_WE, RSFEC_BYPASS_RX_DIN, RSFEC_BYPASS_RX_DIN_CW_START, RSFEC_BYPASS_TX_DIN, RSFEC_BYPASS_TX_DIN_CW_START, RX_CLK, RX_RESET, RX_SERDES_ALT_DATA0, RX_SERDES_ALT_DATA1, RX_SERDES_ALT_DATA2, RX_SERDES_ALT_DATA3, RX_SERDES_CLK, RX_SERDES_DATA0, RX_SERDES_DATA1, RX_SERDES_DATA2, RX_SERDES_DATA3, RX_SERDES_DATA4, RX_SERDES_DATA5, RX_SERDES_DATA6, RX_SERDES_DATA7, RX_SERDES_DATA8 +, RX_SERDES_DATA9, RX_SERDES_RESET, TX_CLK, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1 +, TX_MTYIN2, TX_MTYIN3, TX_PREIN, TX_PTP_1588OP_IN, TX_PTP_CHKSUM_OFFSET_IN, TX_PTP_RXTSTAMP_IN, TX_PTP_TAG_FIELD_IN, TX_PTP_TSTAMP_OFFSET_IN, TX_PTP_UPD_CHKSUM_IN, TX_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; parameter CTL_RX_CHECK_ACK = "TRUE"; parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; @@ -28033,7 +28493,16 @@ module CMACE4 (...); input TX_SOPIN3; endmodule -module MCB (...); +module MCB(CAS, CKE, DQIOWEN0, DQSIOWEN90N, DQSIOWEN90P, IOIDRPADD, IOIDRPBROADCAST, IOIDRPCLK, IOIDRPCS, IOIDRPSDO, IOIDRPTRAIN, IOIDRPUPDATE, LDMN, LDMP, ODT, P0CMDEMPTY, P0CMDFULL, P0RDEMPTY, P0RDERROR, P0RDFULL, P0RDOVERFLOW +, P0WREMPTY, P0WRERROR, P0WRFULL, P0WRUNDERRUN, P1CMDEMPTY, P1CMDFULL, P1RDEMPTY, P1RDERROR, P1RDFULL, P1RDOVERFLOW, P1WREMPTY, P1WRERROR, P1WRFULL, P1WRUNDERRUN, P2CMDEMPTY, P2CMDFULL, P2EMPTY, P2ERROR, P2FULL, P2RDOVERFLOW, P2WRUNDERRUN +, P3CMDEMPTY, P3CMDFULL, P3EMPTY, P3ERROR, P3FULL, P3RDOVERFLOW, P3WRUNDERRUN, P4CMDEMPTY, P4CMDFULL, P4EMPTY, P4ERROR, P4FULL, P4RDOVERFLOW, P4WRUNDERRUN, P5CMDEMPTY, P5CMDFULL, P5EMPTY, P5ERROR, P5FULL, P5RDOVERFLOW, P5WRUNDERRUN +, RAS, RST, SELFREFRESHMODE, UDMN, UDMP, UOCALSTART, UOCMDREADYIN, UODATAVALID, UODONECAL, UOREFRSHFLAG, UOSDO, WE, ADDR, DQON, DQOP, BA, P0RDDATA, P1RDDATA, P2RDDATA, P3RDDATA, P4RDDATA +, P5RDDATA, STATUS, IOIDRPADDR, P0RDCOUNT, P0WRCOUNT, P1RDCOUNT, P1WRCOUNT, P2COUNT, P3COUNT, P4COUNT, P5COUNT, UODATA, DQSIOIN, DQSIOIP, IOIDRPSDI, P0ARBEN, P0CMDCLK, P0CMDEN, P0RDCLK, P0RDEN, P0WRCLK +, P0WREN, P1ARBEN, P1CMDCLK, P1CMDEN, P1RDCLK, P1RDEN, P1WRCLK, P1WREN, P2ARBEN, P2CLK, P2CMDCLK, P2CMDEN, P2EN, P3ARBEN, P3CLK, P3CMDCLK, P3CMDEN, P3EN, P4ARBEN, P4CLK, P4CMDCLK +, P4CMDEN, P4EN, P5ARBEN, P5CLK, P5CMDCLK, P5CMDEN, P5EN, PLLLOCK, RECAL, SELFREFRESHENTER, SYSRST, UDQSIOIN, UDQSIOIP, UIADD, UIBROADCAST, UICLK, UICMD, UICMDEN, UICMDIN, UICS, UIDONECAL +, UIDQLOWERDEC, UIDQLOWERINC, UIDQUPPERDEC, UIDQUPPERINC, UIDRPUPDATE, UILDQSDEC, UILDQSINC, UIREAD, UISDI, UIUDQSDEC, UIUDQSINC, P0CMDCA, P1CMDCA, P2CMDCA, P3CMDCA, P4CMDCA, P5CMDCA, P0CMDRA, P1CMDRA, P2CMDRA, P3CMDRA +, P4CMDRA, P5CMDRA, DQI, PLLCE, PLLCLK, P0CMDBA, P0CMDINSTR, P1CMDBA, P1CMDINSTR, P2CMDBA, P2CMDINSTR, P3CMDBA, P3CMDINSTR, P4CMDBA, P4CMDINSTR, P5CMDBA, P5CMDINSTR, P0WRDATA, P1WRDATA, P2WRDATA, P3WRDATA +, P4WRDATA, P5WRDATA, P0RWRMASK, P1RWRMASK, P2WRMASK, P3WRMASK, P4WRMASK, P5WRMASK, UIDQCOUNT, UIADDR, P0CMDBL, P1CMDBL, P2CMDBL, P3CMDBL, P4CMDBL, P5CMDBL); parameter integer ARB_NUM_TIME_SLOTS = 12; parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; @@ -28297,12 +28766,12 @@ module MCB (...); endmodule (* keep *) -module HBM_REF_CLK (...); +module HBM_REF_CLK(REF_CLK); input REF_CLK; endmodule (* keep *) -module HBM_SNGLBLI_INTF_APB (...); +module HBM_SNGLBLI_INTF_APB(CATTRIP_PIPE, PRDATA_PIPE, PREADY_PIPE, PSLVERR_PIPE, TEMP_PIPE, PADDR, PCLK, PENABLE, PRESET_N, PSEL, PWDATA, PWRITE); parameter CLK_SEL = "FALSE"; parameter [0:0] IS_PCLK_INVERTED = 1'b0; parameter [0:0] IS_PRESET_N_INVERTED = 1'b0; @@ -28327,7 +28796,9 @@ module HBM_SNGLBLI_INTF_APB (...); endmodule (* keep *) -module HBM_SNGLBLI_INTF_AXI (...); +module HBM_SNGLBLI_INTF_AXI(ARREADY_PIPE, AWREADY_PIPE, BID_PIPE, BRESP_PIPE, BVALID_PIPE, DFI_AW_AERR_N_PIPE, DFI_CLK_BUF, DFI_CTRLUPD_ACK_PIPE, DFI_DBI_BYTE_DISABLE_PIPE, DFI_DW_RDDATA_DBI_PIPE, DFI_DW_RDDATA_DERR_PIPE, DFI_DW_RDDATA_PAR_VALID_PIPE, DFI_DW_RDDATA_VALID_PIPE, DFI_INIT_COMPLETE_PIPE, DFI_PHYUPD_REQ_PIPE, DFI_PHYUPD_TYPE_PIPE, DFI_PHY_LP_STATE_PIPE, DFI_RST_N_BUF, MC_STATUS, PHY_STATUS, RDATA_PARITY_PIPE +, RDATA_PIPE, RID_PIPE, RLAST_PIPE, RRESP_PIPE, RVALID_PIPE, STATUS, WREADY_PIPE, ACLK, ARADDR, ARBURST, ARESET_N, ARID, ARLEN, ARSIZE, ARVALID, AWADDR, AWBURST, AWID, AWLEN, AWSIZE, AWVALID +, BREADY, BSCAN_CK, DFI_LP_PWR_X_REQ, MBIST_EN, RREADY, WDATA, WDATA_PARITY, WLAST, WSTRB, WVALID); parameter CLK_SEL = "FALSE"; parameter integer DATARATE = 1800; parameter [0:0] IS_ACLK_INVERTED = 1'b0; @@ -28395,7 +28866,42 @@ module HBM_SNGLBLI_INTF_AXI (...); endmodule (* keep *) -module HBM_ONE_STACK_INTF (...); +module HBM_ONE_STACK_INTF(APB_0_PRDATA, APB_0_PREADY, APB_0_PSLVERR, AXI_00_ARREADY, AXI_00_AWREADY, AXI_00_BID, AXI_00_BRESP, AXI_00_BVALID, AXI_00_DFI_AW_AERR_N, AXI_00_DFI_CLK_BUF, AXI_00_DFI_DBI_BYTE_DISABLE, AXI_00_DFI_DW_RDDATA_DBI, AXI_00_DFI_DW_RDDATA_DERR, AXI_00_DFI_DW_RDDATA_VALID, AXI_00_DFI_INIT_COMPLETE, AXI_00_DFI_PHYUPD_REQ, AXI_00_DFI_PHY_LP_STATE, AXI_00_DFI_RST_N_BUF, AXI_00_MC_STATUS, AXI_00_PHY_STATUS, AXI_00_RDATA +, AXI_00_RDATA_PARITY, AXI_00_RID, AXI_00_RLAST, AXI_00_RRESP, AXI_00_RVALID, AXI_00_WREADY, AXI_01_ARREADY, AXI_01_AWREADY, AXI_01_BID, AXI_01_BRESP, AXI_01_BVALID, AXI_01_DFI_AW_AERR_N, AXI_01_DFI_CLK_BUF, AXI_01_DFI_DBI_BYTE_DISABLE, AXI_01_DFI_DW_RDDATA_DBI, AXI_01_DFI_DW_RDDATA_DERR, AXI_01_DFI_DW_RDDATA_VALID, AXI_01_DFI_INIT_COMPLETE, AXI_01_DFI_PHYUPD_REQ, AXI_01_DFI_PHY_LP_STATE, AXI_01_DFI_RST_N_BUF +, AXI_01_RDATA, AXI_01_RDATA_PARITY, AXI_01_RID, AXI_01_RLAST, AXI_01_RRESP, AXI_01_RVALID, AXI_01_WREADY, AXI_02_ARREADY, AXI_02_AWREADY, AXI_02_BID, AXI_02_BRESP, AXI_02_BVALID, AXI_02_DFI_AW_AERR_N, AXI_02_DFI_CLK_BUF, AXI_02_DFI_DBI_BYTE_DISABLE, AXI_02_DFI_DW_RDDATA_DBI, AXI_02_DFI_DW_RDDATA_DERR, AXI_02_DFI_DW_RDDATA_VALID, AXI_02_DFI_INIT_COMPLETE, AXI_02_DFI_PHYUPD_REQ, AXI_02_DFI_PHY_LP_STATE +, AXI_02_DFI_RST_N_BUF, AXI_02_MC_STATUS, AXI_02_PHY_STATUS, AXI_02_RDATA, AXI_02_RDATA_PARITY, AXI_02_RID, AXI_02_RLAST, AXI_02_RRESP, AXI_02_RVALID, AXI_02_WREADY, AXI_03_ARREADY, AXI_03_AWREADY, AXI_03_BID, AXI_03_BRESP, AXI_03_BVALID, AXI_03_DFI_AW_AERR_N, AXI_03_DFI_CLK_BUF, AXI_03_DFI_DBI_BYTE_DISABLE, AXI_03_DFI_DW_RDDATA_DBI, AXI_03_DFI_DW_RDDATA_DERR, AXI_03_DFI_DW_RDDATA_VALID +, AXI_03_DFI_INIT_COMPLETE, AXI_03_DFI_PHYUPD_REQ, AXI_03_DFI_PHY_LP_STATE, AXI_03_DFI_RST_N_BUF, AXI_03_RDATA, AXI_03_RDATA_PARITY, AXI_03_RID, AXI_03_RLAST, AXI_03_RRESP, AXI_03_RVALID, AXI_03_WREADY, AXI_04_ARREADY, AXI_04_AWREADY, AXI_04_BID, AXI_04_BRESP, AXI_04_BVALID, AXI_04_DFI_AW_AERR_N, AXI_04_DFI_CLK_BUF, AXI_04_DFI_DBI_BYTE_DISABLE, AXI_04_DFI_DW_RDDATA_DBI, AXI_04_DFI_DW_RDDATA_DERR +, AXI_04_DFI_DW_RDDATA_VALID, AXI_04_DFI_INIT_COMPLETE, AXI_04_DFI_PHYUPD_REQ, AXI_04_DFI_PHY_LP_STATE, AXI_04_DFI_RST_N_BUF, AXI_04_MC_STATUS, AXI_04_PHY_STATUS, AXI_04_RDATA, AXI_04_RDATA_PARITY, AXI_04_RID, AXI_04_RLAST, AXI_04_RRESP, AXI_04_RVALID, AXI_04_WREADY, AXI_05_ARREADY, AXI_05_AWREADY, AXI_05_BID, AXI_05_BRESP, AXI_05_BVALID, AXI_05_DFI_AW_AERR_N, AXI_05_DFI_CLK_BUF +, AXI_05_DFI_DBI_BYTE_DISABLE, AXI_05_DFI_DW_RDDATA_DBI, AXI_05_DFI_DW_RDDATA_DERR, AXI_05_DFI_DW_RDDATA_VALID, AXI_05_DFI_INIT_COMPLETE, AXI_05_DFI_PHYUPD_REQ, AXI_05_DFI_PHY_LP_STATE, AXI_05_DFI_RST_N_BUF, AXI_05_RDATA, AXI_05_RDATA_PARITY, AXI_05_RID, AXI_05_RLAST, AXI_05_RRESP, AXI_05_RVALID, AXI_05_WREADY, AXI_06_ARREADY, AXI_06_AWREADY, AXI_06_BID, AXI_06_BRESP, AXI_06_BVALID, AXI_06_DFI_AW_AERR_N +, AXI_06_DFI_CLK_BUF, AXI_06_DFI_DBI_BYTE_DISABLE, AXI_06_DFI_DW_RDDATA_DBI, AXI_06_DFI_DW_RDDATA_DERR, AXI_06_DFI_DW_RDDATA_VALID, AXI_06_DFI_INIT_COMPLETE, AXI_06_DFI_PHYUPD_REQ, AXI_06_DFI_PHY_LP_STATE, AXI_06_DFI_RST_N_BUF, AXI_06_MC_STATUS, AXI_06_PHY_STATUS, AXI_06_RDATA, AXI_06_RDATA_PARITY, AXI_06_RID, AXI_06_RLAST, AXI_06_RRESP, AXI_06_RVALID, AXI_06_WREADY, AXI_07_ARREADY, AXI_07_AWREADY, AXI_07_BID +, AXI_07_BRESP, AXI_07_BVALID, AXI_07_DFI_AW_AERR_N, AXI_07_DFI_CLK_BUF, AXI_07_DFI_DBI_BYTE_DISABLE, AXI_07_DFI_DW_RDDATA_DBI, AXI_07_DFI_DW_RDDATA_DERR, AXI_07_DFI_DW_RDDATA_VALID, AXI_07_DFI_INIT_COMPLETE, AXI_07_DFI_PHYUPD_REQ, AXI_07_DFI_PHY_LP_STATE, AXI_07_DFI_RST_N_BUF, AXI_07_RDATA, AXI_07_RDATA_PARITY, AXI_07_RID, AXI_07_RLAST, AXI_07_RRESP, AXI_07_RVALID, AXI_07_WREADY, AXI_08_ARREADY, AXI_08_AWREADY +, AXI_08_BID, AXI_08_BRESP, AXI_08_BVALID, AXI_08_DFI_AW_AERR_N, AXI_08_DFI_CLK_BUF, AXI_08_DFI_DBI_BYTE_DISABLE, AXI_08_DFI_DW_RDDATA_DBI, AXI_08_DFI_DW_RDDATA_DERR, AXI_08_DFI_DW_RDDATA_VALID, AXI_08_DFI_INIT_COMPLETE, AXI_08_DFI_PHYUPD_REQ, AXI_08_DFI_PHY_LP_STATE, AXI_08_DFI_RST_N_BUF, AXI_08_MC_STATUS, AXI_08_PHY_STATUS, AXI_08_RDATA, AXI_08_RDATA_PARITY, AXI_08_RID, AXI_08_RLAST, AXI_08_RRESP, AXI_08_RVALID +, AXI_08_WREADY, AXI_09_ARREADY, AXI_09_AWREADY, AXI_09_BID, AXI_09_BRESP, AXI_09_BVALID, AXI_09_DFI_AW_AERR_N, AXI_09_DFI_CLK_BUF, AXI_09_DFI_DBI_BYTE_DISABLE, AXI_09_DFI_DW_RDDATA_DBI, AXI_09_DFI_DW_RDDATA_DERR, AXI_09_DFI_DW_RDDATA_VALID, AXI_09_DFI_INIT_COMPLETE, AXI_09_DFI_PHYUPD_REQ, AXI_09_DFI_PHY_LP_STATE, AXI_09_DFI_RST_N_BUF, AXI_09_RDATA, AXI_09_RDATA_PARITY, AXI_09_RID, AXI_09_RLAST, AXI_09_RRESP +, AXI_09_RVALID, AXI_09_WREADY, AXI_10_ARREADY, AXI_10_AWREADY, AXI_10_BID, AXI_10_BRESP, AXI_10_BVALID, AXI_10_DFI_AW_AERR_N, AXI_10_DFI_CLK_BUF, AXI_10_DFI_DBI_BYTE_DISABLE, AXI_10_DFI_DW_RDDATA_DBI, AXI_10_DFI_DW_RDDATA_DERR, AXI_10_DFI_DW_RDDATA_VALID, AXI_10_DFI_INIT_COMPLETE, AXI_10_DFI_PHYUPD_REQ, AXI_10_DFI_PHY_LP_STATE, AXI_10_DFI_RST_N_BUF, AXI_10_MC_STATUS, AXI_10_PHY_STATUS, AXI_10_RDATA, AXI_10_RDATA_PARITY +, AXI_10_RID, AXI_10_RLAST, AXI_10_RRESP, AXI_10_RVALID, AXI_10_WREADY, AXI_11_ARREADY, AXI_11_AWREADY, AXI_11_BID, AXI_11_BRESP, AXI_11_BVALID, AXI_11_DFI_AW_AERR_N, AXI_11_DFI_CLK_BUF, AXI_11_DFI_DBI_BYTE_DISABLE, AXI_11_DFI_DW_RDDATA_DBI, AXI_11_DFI_DW_RDDATA_DERR, AXI_11_DFI_DW_RDDATA_VALID, AXI_11_DFI_INIT_COMPLETE, AXI_11_DFI_PHYUPD_REQ, AXI_11_DFI_PHY_LP_STATE, AXI_11_DFI_RST_N_BUF, AXI_11_RDATA +, AXI_11_RDATA_PARITY, AXI_11_RID, AXI_11_RLAST, AXI_11_RRESP, AXI_11_RVALID, AXI_11_WREADY, AXI_12_ARREADY, AXI_12_AWREADY, AXI_12_BID, AXI_12_BRESP, AXI_12_BVALID, AXI_12_DFI_AW_AERR_N, AXI_12_DFI_CLK_BUF, AXI_12_DFI_DBI_BYTE_DISABLE, AXI_12_DFI_DW_RDDATA_DBI, AXI_12_DFI_DW_RDDATA_DERR, AXI_12_DFI_DW_RDDATA_VALID, AXI_12_DFI_INIT_COMPLETE, AXI_12_DFI_PHYUPD_REQ, AXI_12_DFI_PHY_LP_STATE, AXI_12_DFI_RST_N_BUF +, AXI_12_MC_STATUS, AXI_12_PHY_STATUS, AXI_12_RDATA, AXI_12_RDATA_PARITY, AXI_12_RID, AXI_12_RLAST, AXI_12_RRESP, AXI_12_RVALID, AXI_12_WREADY, AXI_13_ARREADY, AXI_13_AWREADY, AXI_13_BID, AXI_13_BRESP, AXI_13_BVALID, AXI_13_DFI_AW_AERR_N, AXI_13_DFI_CLK_BUF, AXI_13_DFI_DBI_BYTE_DISABLE, AXI_13_DFI_DW_RDDATA_DBI, AXI_13_DFI_DW_RDDATA_DERR, AXI_13_DFI_DW_RDDATA_VALID, AXI_13_DFI_INIT_COMPLETE +, AXI_13_DFI_PHYUPD_REQ, AXI_13_DFI_PHY_LP_STATE, AXI_13_DFI_RST_N_BUF, AXI_13_RDATA, AXI_13_RDATA_PARITY, AXI_13_RID, AXI_13_RLAST, AXI_13_RRESP, AXI_13_RVALID, AXI_13_WREADY, AXI_14_ARREADY, AXI_14_AWREADY, AXI_14_BID, AXI_14_BRESP, AXI_14_BVALID, AXI_14_DFI_AW_AERR_N, AXI_14_DFI_CLK_BUF, AXI_14_DFI_DBI_BYTE_DISABLE, AXI_14_DFI_DW_RDDATA_DBI, AXI_14_DFI_DW_RDDATA_DERR, AXI_14_DFI_DW_RDDATA_VALID +, AXI_14_DFI_INIT_COMPLETE, AXI_14_DFI_PHYUPD_REQ, AXI_14_DFI_PHY_LP_STATE, AXI_14_DFI_RST_N_BUF, AXI_14_MC_STATUS, AXI_14_PHY_STATUS, AXI_14_RDATA, AXI_14_RDATA_PARITY, AXI_14_RID, AXI_14_RLAST, AXI_14_RRESP, AXI_14_RVALID, AXI_14_WREADY, AXI_15_ARREADY, AXI_15_AWREADY, AXI_15_BID, AXI_15_BRESP, AXI_15_BVALID, AXI_15_DFI_AW_AERR_N, AXI_15_DFI_CLK_BUF, AXI_15_DFI_DBI_BYTE_DISABLE +, AXI_15_DFI_DW_RDDATA_DBI, AXI_15_DFI_DW_RDDATA_DERR, AXI_15_DFI_DW_RDDATA_VALID, AXI_15_DFI_INIT_COMPLETE, AXI_15_DFI_PHYUPD_REQ, AXI_15_DFI_PHY_LP_STATE, AXI_15_DFI_RST_N_BUF, AXI_15_RDATA, AXI_15_RDATA_PARITY, AXI_15_RID, AXI_15_RLAST, AXI_15_RRESP, AXI_15_RVALID, AXI_15_WREADY, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, APB_0_PADDR, APB_0_PCLK, APB_0_PENABLE, APB_0_PRESET_N, APB_0_PSEL +, APB_0_PWDATA, APB_0_PWRITE, AXI_00_ACLK, AXI_00_ARADDR, AXI_00_ARBURST, AXI_00_ARESET_N, AXI_00_ARID, AXI_00_ARLEN, AXI_00_ARSIZE, AXI_00_ARVALID, AXI_00_AWADDR, AXI_00_AWBURST, AXI_00_AWID, AXI_00_AWLEN, AXI_00_AWSIZE, AXI_00_AWVALID, AXI_00_BREADY, AXI_00_DFI_LP_PWR_X_REQ, AXI_00_RREADY, AXI_00_WDATA, AXI_00_WDATA_PARITY +, AXI_00_WLAST, AXI_00_WSTRB, AXI_00_WVALID, AXI_01_ACLK, AXI_01_ARADDR, AXI_01_ARBURST, AXI_01_ARESET_N, AXI_01_ARID, AXI_01_ARLEN, AXI_01_ARSIZE, AXI_01_ARVALID, AXI_01_AWADDR, AXI_01_AWBURST, AXI_01_AWID, AXI_01_AWLEN, AXI_01_AWSIZE, AXI_01_AWVALID, AXI_01_BREADY, AXI_01_DFI_LP_PWR_X_REQ, AXI_01_RREADY, AXI_01_WDATA +, AXI_01_WDATA_PARITY, AXI_01_WLAST, AXI_01_WSTRB, AXI_01_WVALID, AXI_02_ACLK, AXI_02_ARADDR, AXI_02_ARBURST, AXI_02_ARESET_N, AXI_02_ARID, AXI_02_ARLEN, AXI_02_ARSIZE, AXI_02_ARVALID, AXI_02_AWADDR, AXI_02_AWBURST, AXI_02_AWID, AXI_02_AWLEN, AXI_02_AWSIZE, AXI_02_AWVALID, AXI_02_BREADY, AXI_02_DFI_LP_PWR_X_REQ, AXI_02_RREADY +, AXI_02_WDATA, AXI_02_WDATA_PARITY, AXI_02_WLAST, AXI_02_WSTRB, AXI_02_WVALID, AXI_03_ACLK, AXI_03_ARADDR, AXI_03_ARBURST, AXI_03_ARESET_N, AXI_03_ARID, AXI_03_ARLEN, AXI_03_ARSIZE, AXI_03_ARVALID, AXI_03_AWADDR, AXI_03_AWBURST, AXI_03_AWID, AXI_03_AWLEN, AXI_03_AWSIZE, AXI_03_AWVALID, AXI_03_BREADY, AXI_03_DFI_LP_PWR_X_REQ +, AXI_03_RREADY, AXI_03_WDATA, AXI_03_WDATA_PARITY, AXI_03_WLAST, AXI_03_WSTRB, AXI_03_WVALID, AXI_04_ACLK, AXI_04_ARADDR, AXI_04_ARBURST, AXI_04_ARESET_N, AXI_04_ARID, AXI_04_ARLEN, AXI_04_ARSIZE, AXI_04_ARVALID, AXI_04_AWADDR, AXI_04_AWBURST, AXI_04_AWID, AXI_04_AWLEN, AXI_04_AWSIZE, AXI_04_AWVALID, AXI_04_BREADY +, AXI_04_DFI_LP_PWR_X_REQ, AXI_04_RREADY, AXI_04_WDATA, AXI_04_WDATA_PARITY, AXI_04_WLAST, AXI_04_WSTRB, AXI_04_WVALID, AXI_05_ACLK, AXI_05_ARADDR, AXI_05_ARBURST, AXI_05_ARESET_N, AXI_05_ARID, AXI_05_ARLEN, AXI_05_ARSIZE, AXI_05_ARVALID, AXI_05_AWADDR, AXI_05_AWBURST, AXI_05_AWID, AXI_05_AWLEN, AXI_05_AWSIZE, AXI_05_AWVALID +, AXI_05_BREADY, AXI_05_DFI_LP_PWR_X_REQ, AXI_05_RREADY, AXI_05_WDATA, AXI_05_WDATA_PARITY, AXI_05_WLAST, AXI_05_WSTRB, AXI_05_WVALID, AXI_06_ACLK, AXI_06_ARADDR, AXI_06_ARBURST, AXI_06_ARESET_N, AXI_06_ARID, AXI_06_ARLEN, AXI_06_ARSIZE, AXI_06_ARVALID, AXI_06_AWADDR, AXI_06_AWBURST, AXI_06_AWID, AXI_06_AWLEN, AXI_06_AWSIZE +, AXI_06_AWVALID, AXI_06_BREADY, AXI_06_DFI_LP_PWR_X_REQ, AXI_06_RREADY, AXI_06_WDATA, AXI_06_WDATA_PARITY, AXI_06_WLAST, AXI_06_WSTRB, AXI_06_WVALID, AXI_07_ACLK, AXI_07_ARADDR, AXI_07_ARBURST, AXI_07_ARESET_N, AXI_07_ARID, AXI_07_ARLEN, AXI_07_ARSIZE, AXI_07_ARVALID, AXI_07_AWADDR, AXI_07_AWBURST, AXI_07_AWID, AXI_07_AWLEN +, AXI_07_AWSIZE, AXI_07_AWVALID, AXI_07_BREADY, AXI_07_DFI_LP_PWR_X_REQ, AXI_07_RREADY, AXI_07_WDATA, AXI_07_WDATA_PARITY, AXI_07_WLAST, AXI_07_WSTRB, AXI_07_WVALID, AXI_08_ACLK, AXI_08_ARADDR, AXI_08_ARBURST, AXI_08_ARESET_N, AXI_08_ARID, AXI_08_ARLEN, AXI_08_ARSIZE, AXI_08_ARVALID, AXI_08_AWADDR, AXI_08_AWBURST, AXI_08_AWID +, AXI_08_AWLEN, AXI_08_AWSIZE, AXI_08_AWVALID, AXI_08_BREADY, AXI_08_DFI_LP_PWR_X_REQ, AXI_08_RREADY, AXI_08_WDATA, AXI_08_WDATA_PARITY, AXI_08_WLAST, AXI_08_WSTRB, AXI_08_WVALID, AXI_09_ACLK, AXI_09_ARADDR, AXI_09_ARBURST, AXI_09_ARESET_N, AXI_09_ARID, AXI_09_ARLEN, AXI_09_ARSIZE, AXI_09_ARVALID, AXI_09_AWADDR, AXI_09_AWBURST +, AXI_09_AWID, AXI_09_AWLEN, AXI_09_AWSIZE, AXI_09_AWVALID, AXI_09_BREADY, AXI_09_DFI_LP_PWR_X_REQ, AXI_09_RREADY, AXI_09_WDATA, AXI_09_WDATA_PARITY, AXI_09_WLAST, AXI_09_WSTRB, AXI_09_WVALID, AXI_10_ACLK, AXI_10_ARADDR, AXI_10_ARBURST, AXI_10_ARESET_N, AXI_10_ARID, AXI_10_ARLEN, AXI_10_ARSIZE, AXI_10_ARVALID, AXI_10_AWADDR +, AXI_10_AWBURST, AXI_10_AWID, AXI_10_AWLEN, AXI_10_AWSIZE, AXI_10_AWVALID, AXI_10_BREADY, AXI_10_DFI_LP_PWR_X_REQ, AXI_10_RREADY, AXI_10_WDATA, AXI_10_WDATA_PARITY, AXI_10_WLAST, AXI_10_WSTRB, AXI_10_WVALID, AXI_11_ACLK, AXI_11_ARADDR, AXI_11_ARBURST, AXI_11_ARESET_N, AXI_11_ARID, AXI_11_ARLEN, AXI_11_ARSIZE, AXI_11_ARVALID +, AXI_11_AWADDR, AXI_11_AWBURST, AXI_11_AWID, AXI_11_AWLEN, AXI_11_AWSIZE, AXI_11_AWVALID, AXI_11_BREADY, AXI_11_DFI_LP_PWR_X_REQ, AXI_11_RREADY, AXI_11_WDATA, AXI_11_WDATA_PARITY, AXI_11_WLAST, AXI_11_WSTRB, AXI_11_WVALID, AXI_12_ACLK, AXI_12_ARADDR, AXI_12_ARBURST, AXI_12_ARESET_N, AXI_12_ARID, AXI_12_ARLEN, AXI_12_ARSIZE +, AXI_12_ARVALID, AXI_12_AWADDR, AXI_12_AWBURST, AXI_12_AWID, AXI_12_AWLEN, AXI_12_AWSIZE, AXI_12_AWVALID, AXI_12_BREADY, AXI_12_DFI_LP_PWR_X_REQ, AXI_12_RREADY, AXI_12_WDATA, AXI_12_WDATA_PARITY, AXI_12_WLAST, AXI_12_WSTRB, AXI_12_WVALID, AXI_13_ACLK, AXI_13_ARADDR, AXI_13_ARBURST, AXI_13_ARESET_N, AXI_13_ARID, AXI_13_ARLEN +, AXI_13_ARSIZE, AXI_13_ARVALID, AXI_13_AWADDR, AXI_13_AWBURST, AXI_13_AWID, AXI_13_AWLEN, AXI_13_AWSIZE, AXI_13_AWVALID, AXI_13_BREADY, AXI_13_DFI_LP_PWR_X_REQ, AXI_13_RREADY, AXI_13_WDATA, AXI_13_WDATA_PARITY, AXI_13_WLAST, AXI_13_WSTRB, AXI_13_WVALID, AXI_14_ACLK, AXI_14_ARADDR, AXI_14_ARBURST, AXI_14_ARESET_N, AXI_14_ARID +, AXI_14_ARLEN, AXI_14_ARSIZE, AXI_14_ARVALID, AXI_14_AWADDR, AXI_14_AWBURST, AXI_14_AWID, AXI_14_AWLEN, AXI_14_AWSIZE, AXI_14_AWVALID, AXI_14_BREADY, AXI_14_DFI_LP_PWR_X_REQ, AXI_14_RREADY, AXI_14_WDATA, AXI_14_WDATA_PARITY, AXI_14_WLAST, AXI_14_WSTRB, AXI_14_WVALID, AXI_15_ACLK, AXI_15_ARADDR, AXI_15_ARBURST, AXI_15_ARESET_N +, AXI_15_ARID, AXI_15_ARLEN, AXI_15_ARSIZE, AXI_15_ARVALID, AXI_15_AWADDR, AXI_15_AWBURST, AXI_15_AWID, AXI_15_AWLEN, AXI_15_AWSIZE, AXI_15_AWVALID, AXI_15_BREADY, AXI_15_DFI_LP_PWR_X_REQ, AXI_15_RREADY, AXI_15_WDATA, AXI_15_WDATA_PARITY, AXI_15_WLAST, AXI_15_WSTRB, AXI_15_WVALID, BSCAN_DRCK, BSCAN_TCK, HBM_REF_CLK +, MBIST_EN_00, MBIST_EN_01, MBIST_EN_02, MBIST_EN_03, MBIST_EN_04, MBIST_EN_05, MBIST_EN_06, MBIST_EN_07); parameter CLK_SEL_00 = "FALSE"; parameter CLK_SEL_01 = "FALSE"; parameter CLK_SEL_02 = "FALSE"; @@ -29298,7 +29804,77 @@ module HBM_ONE_STACK_INTF (...); endmodule (* keep *) -module HBM_TWO_STACK_INTF (...); +module HBM_TWO_STACK_INTF(APB_0_PRDATA, APB_0_PREADY, APB_0_PSLVERR, APB_1_PRDATA, APB_1_PREADY, APB_1_PSLVERR, AXI_00_ARREADY, AXI_00_AWREADY, AXI_00_BID, AXI_00_BRESP, AXI_00_BVALID, AXI_00_DFI_AW_AERR_N, AXI_00_DFI_CLK_BUF, AXI_00_DFI_DBI_BYTE_DISABLE, AXI_00_DFI_DW_RDDATA_DBI, AXI_00_DFI_DW_RDDATA_DERR, AXI_00_DFI_DW_RDDATA_VALID, AXI_00_DFI_INIT_COMPLETE, AXI_00_DFI_PHYUPD_REQ, AXI_00_DFI_PHY_LP_STATE, AXI_00_DFI_RST_N_BUF +, AXI_00_MC_STATUS, AXI_00_PHY_STATUS, AXI_00_RDATA, AXI_00_RDATA_PARITY, AXI_00_RID, AXI_00_RLAST, AXI_00_RRESP, AXI_00_RVALID, AXI_00_WREADY, AXI_01_ARREADY, AXI_01_AWREADY, AXI_01_BID, AXI_01_BRESP, AXI_01_BVALID, AXI_01_DFI_AW_AERR_N, AXI_01_DFI_CLK_BUF, AXI_01_DFI_DBI_BYTE_DISABLE, AXI_01_DFI_DW_RDDATA_DBI, AXI_01_DFI_DW_RDDATA_DERR, AXI_01_DFI_DW_RDDATA_VALID, AXI_01_DFI_INIT_COMPLETE +, AXI_01_DFI_PHYUPD_REQ, AXI_01_DFI_PHY_LP_STATE, AXI_01_DFI_RST_N_BUF, AXI_01_RDATA, AXI_01_RDATA_PARITY, AXI_01_RID, AXI_01_RLAST, AXI_01_RRESP, AXI_01_RVALID, AXI_01_WREADY, AXI_02_ARREADY, AXI_02_AWREADY, AXI_02_BID, AXI_02_BRESP, AXI_02_BVALID, AXI_02_DFI_AW_AERR_N, AXI_02_DFI_CLK_BUF, AXI_02_DFI_DBI_BYTE_DISABLE, AXI_02_DFI_DW_RDDATA_DBI, AXI_02_DFI_DW_RDDATA_DERR, AXI_02_DFI_DW_RDDATA_VALID +, AXI_02_DFI_INIT_COMPLETE, AXI_02_DFI_PHYUPD_REQ, AXI_02_DFI_PHY_LP_STATE, AXI_02_DFI_RST_N_BUF, AXI_02_MC_STATUS, AXI_02_PHY_STATUS, AXI_02_RDATA, AXI_02_RDATA_PARITY, AXI_02_RID, AXI_02_RLAST, AXI_02_RRESP, AXI_02_RVALID, AXI_02_WREADY, AXI_03_ARREADY, AXI_03_AWREADY, AXI_03_BID, AXI_03_BRESP, AXI_03_BVALID, AXI_03_DFI_AW_AERR_N, AXI_03_DFI_CLK_BUF, AXI_03_DFI_DBI_BYTE_DISABLE +, AXI_03_DFI_DW_RDDATA_DBI, AXI_03_DFI_DW_RDDATA_DERR, AXI_03_DFI_DW_RDDATA_VALID, AXI_03_DFI_INIT_COMPLETE, AXI_03_DFI_PHYUPD_REQ, AXI_03_DFI_PHY_LP_STATE, AXI_03_DFI_RST_N_BUF, AXI_03_RDATA, AXI_03_RDATA_PARITY, AXI_03_RID, AXI_03_RLAST, AXI_03_RRESP, AXI_03_RVALID, AXI_03_WREADY, AXI_04_ARREADY, AXI_04_AWREADY, AXI_04_BID, AXI_04_BRESP, AXI_04_BVALID, AXI_04_DFI_AW_AERR_N, AXI_04_DFI_CLK_BUF +, AXI_04_DFI_DBI_BYTE_DISABLE, AXI_04_DFI_DW_RDDATA_DBI, AXI_04_DFI_DW_RDDATA_DERR, AXI_04_DFI_DW_RDDATA_VALID, AXI_04_DFI_INIT_COMPLETE, AXI_04_DFI_PHYUPD_REQ, AXI_04_DFI_PHY_LP_STATE, AXI_04_DFI_RST_N_BUF, AXI_04_MC_STATUS, AXI_04_PHY_STATUS, AXI_04_RDATA, AXI_04_RDATA_PARITY, AXI_04_RID, AXI_04_RLAST, AXI_04_RRESP, AXI_04_RVALID, AXI_04_WREADY, AXI_05_ARREADY, AXI_05_AWREADY, AXI_05_BID, AXI_05_BRESP +, AXI_05_BVALID, AXI_05_DFI_AW_AERR_N, AXI_05_DFI_CLK_BUF, AXI_05_DFI_DBI_BYTE_DISABLE, AXI_05_DFI_DW_RDDATA_DBI, AXI_05_DFI_DW_RDDATA_DERR, AXI_05_DFI_DW_RDDATA_VALID, AXI_05_DFI_INIT_COMPLETE, AXI_05_DFI_PHYUPD_REQ, AXI_05_DFI_PHY_LP_STATE, AXI_05_DFI_RST_N_BUF, AXI_05_RDATA, AXI_05_RDATA_PARITY, AXI_05_RID, AXI_05_RLAST, AXI_05_RRESP, AXI_05_RVALID, AXI_05_WREADY, AXI_06_ARREADY, AXI_06_AWREADY, AXI_06_BID +, AXI_06_BRESP, AXI_06_BVALID, AXI_06_DFI_AW_AERR_N, AXI_06_DFI_CLK_BUF, AXI_06_DFI_DBI_BYTE_DISABLE, AXI_06_DFI_DW_RDDATA_DBI, AXI_06_DFI_DW_RDDATA_DERR, AXI_06_DFI_DW_RDDATA_VALID, AXI_06_DFI_INIT_COMPLETE, AXI_06_DFI_PHYUPD_REQ, AXI_06_DFI_PHY_LP_STATE, AXI_06_DFI_RST_N_BUF, AXI_06_MC_STATUS, AXI_06_PHY_STATUS, AXI_06_RDATA, AXI_06_RDATA_PARITY, AXI_06_RID, AXI_06_RLAST, AXI_06_RRESP, AXI_06_RVALID, AXI_06_WREADY +, AXI_07_ARREADY, AXI_07_AWREADY, AXI_07_BID, AXI_07_BRESP, AXI_07_BVALID, AXI_07_DFI_AW_AERR_N, AXI_07_DFI_CLK_BUF, AXI_07_DFI_DBI_BYTE_DISABLE, AXI_07_DFI_DW_RDDATA_DBI, AXI_07_DFI_DW_RDDATA_DERR, AXI_07_DFI_DW_RDDATA_VALID, AXI_07_DFI_INIT_COMPLETE, AXI_07_DFI_PHYUPD_REQ, AXI_07_DFI_PHY_LP_STATE, AXI_07_DFI_RST_N_BUF, AXI_07_RDATA, AXI_07_RDATA_PARITY, AXI_07_RID, AXI_07_RLAST, AXI_07_RRESP, AXI_07_RVALID +, AXI_07_WREADY, AXI_08_ARREADY, AXI_08_AWREADY, AXI_08_BID, AXI_08_BRESP, AXI_08_BVALID, AXI_08_DFI_AW_AERR_N, AXI_08_DFI_CLK_BUF, AXI_08_DFI_DBI_BYTE_DISABLE, AXI_08_DFI_DW_RDDATA_DBI, AXI_08_DFI_DW_RDDATA_DERR, AXI_08_DFI_DW_RDDATA_VALID, AXI_08_DFI_INIT_COMPLETE, AXI_08_DFI_PHYUPD_REQ, AXI_08_DFI_PHY_LP_STATE, AXI_08_DFI_RST_N_BUF, AXI_08_MC_STATUS, AXI_08_PHY_STATUS, AXI_08_RDATA, AXI_08_RDATA_PARITY, AXI_08_RID +, AXI_08_RLAST, AXI_08_RRESP, AXI_08_RVALID, AXI_08_WREADY, AXI_09_ARREADY, AXI_09_AWREADY, AXI_09_BID, AXI_09_BRESP, AXI_09_BVALID, AXI_09_DFI_AW_AERR_N, AXI_09_DFI_CLK_BUF, AXI_09_DFI_DBI_BYTE_DISABLE, AXI_09_DFI_DW_RDDATA_DBI, AXI_09_DFI_DW_RDDATA_DERR, AXI_09_DFI_DW_RDDATA_VALID, AXI_09_DFI_INIT_COMPLETE, AXI_09_DFI_PHYUPD_REQ, AXI_09_DFI_PHY_LP_STATE, AXI_09_DFI_RST_N_BUF, AXI_09_RDATA, AXI_09_RDATA_PARITY +, AXI_09_RID, AXI_09_RLAST, AXI_09_RRESP, AXI_09_RVALID, AXI_09_WREADY, AXI_10_ARREADY, AXI_10_AWREADY, AXI_10_BID, AXI_10_BRESP, AXI_10_BVALID, AXI_10_DFI_AW_AERR_N, AXI_10_DFI_CLK_BUF, AXI_10_DFI_DBI_BYTE_DISABLE, AXI_10_DFI_DW_RDDATA_DBI, AXI_10_DFI_DW_RDDATA_DERR, AXI_10_DFI_DW_RDDATA_VALID, AXI_10_DFI_INIT_COMPLETE, AXI_10_DFI_PHYUPD_REQ, AXI_10_DFI_PHY_LP_STATE, AXI_10_DFI_RST_N_BUF, AXI_10_MC_STATUS +, AXI_10_PHY_STATUS, AXI_10_RDATA, AXI_10_RDATA_PARITY, AXI_10_RID, AXI_10_RLAST, AXI_10_RRESP, AXI_10_RVALID, AXI_10_WREADY, AXI_11_ARREADY, AXI_11_AWREADY, AXI_11_BID, AXI_11_BRESP, AXI_11_BVALID, AXI_11_DFI_AW_AERR_N, AXI_11_DFI_CLK_BUF, AXI_11_DFI_DBI_BYTE_DISABLE, AXI_11_DFI_DW_RDDATA_DBI, AXI_11_DFI_DW_RDDATA_DERR, AXI_11_DFI_DW_RDDATA_VALID, AXI_11_DFI_INIT_COMPLETE, AXI_11_DFI_PHYUPD_REQ +, AXI_11_DFI_PHY_LP_STATE, AXI_11_DFI_RST_N_BUF, AXI_11_RDATA, AXI_11_RDATA_PARITY, AXI_11_RID, AXI_11_RLAST, AXI_11_RRESP, AXI_11_RVALID, AXI_11_WREADY, AXI_12_ARREADY, AXI_12_AWREADY, AXI_12_BID, AXI_12_BRESP, AXI_12_BVALID, AXI_12_DFI_AW_AERR_N, AXI_12_DFI_CLK_BUF, AXI_12_DFI_DBI_BYTE_DISABLE, AXI_12_DFI_DW_RDDATA_DBI, AXI_12_DFI_DW_RDDATA_DERR, AXI_12_DFI_DW_RDDATA_VALID, AXI_12_DFI_INIT_COMPLETE +, AXI_12_DFI_PHYUPD_REQ, AXI_12_DFI_PHY_LP_STATE, AXI_12_DFI_RST_N_BUF, AXI_12_MC_STATUS, AXI_12_PHY_STATUS, AXI_12_RDATA, AXI_12_RDATA_PARITY, AXI_12_RID, AXI_12_RLAST, AXI_12_RRESP, AXI_12_RVALID, AXI_12_WREADY, AXI_13_ARREADY, AXI_13_AWREADY, AXI_13_BID, AXI_13_BRESP, AXI_13_BVALID, AXI_13_DFI_AW_AERR_N, AXI_13_DFI_CLK_BUF, AXI_13_DFI_DBI_BYTE_DISABLE, AXI_13_DFI_DW_RDDATA_DBI +, AXI_13_DFI_DW_RDDATA_DERR, AXI_13_DFI_DW_RDDATA_VALID, AXI_13_DFI_INIT_COMPLETE, AXI_13_DFI_PHYUPD_REQ, AXI_13_DFI_PHY_LP_STATE, AXI_13_DFI_RST_N_BUF, AXI_13_RDATA, AXI_13_RDATA_PARITY, AXI_13_RID, AXI_13_RLAST, AXI_13_RRESP, AXI_13_RVALID, AXI_13_WREADY, AXI_14_ARREADY, AXI_14_AWREADY, AXI_14_BID, AXI_14_BRESP, AXI_14_BVALID, AXI_14_DFI_AW_AERR_N, AXI_14_DFI_CLK_BUF, AXI_14_DFI_DBI_BYTE_DISABLE +, AXI_14_DFI_DW_RDDATA_DBI, AXI_14_DFI_DW_RDDATA_DERR, AXI_14_DFI_DW_RDDATA_VALID, AXI_14_DFI_INIT_COMPLETE, AXI_14_DFI_PHYUPD_REQ, AXI_14_DFI_PHY_LP_STATE, AXI_14_DFI_RST_N_BUF, AXI_14_MC_STATUS, AXI_14_PHY_STATUS, AXI_14_RDATA, AXI_14_RDATA_PARITY, AXI_14_RID, AXI_14_RLAST, AXI_14_RRESP, AXI_14_RVALID, AXI_14_WREADY, AXI_15_ARREADY, AXI_15_AWREADY, AXI_15_BID, AXI_15_BRESP, AXI_15_BVALID +, AXI_15_DFI_AW_AERR_N, AXI_15_DFI_CLK_BUF, AXI_15_DFI_DBI_BYTE_DISABLE, AXI_15_DFI_DW_RDDATA_DBI, AXI_15_DFI_DW_RDDATA_DERR, AXI_15_DFI_DW_RDDATA_VALID, AXI_15_DFI_INIT_COMPLETE, AXI_15_DFI_PHYUPD_REQ, AXI_15_DFI_PHY_LP_STATE, AXI_15_DFI_RST_N_BUF, AXI_15_RDATA, AXI_15_RDATA_PARITY, AXI_15_RID, AXI_15_RLAST, AXI_15_RRESP, AXI_15_RVALID, AXI_15_WREADY, AXI_16_ARREADY, AXI_16_AWREADY, AXI_16_BID, AXI_16_BRESP +, AXI_16_BVALID, AXI_16_DFI_AW_AERR_N, AXI_16_DFI_CLK_BUF, AXI_16_DFI_DBI_BYTE_DISABLE, AXI_16_DFI_DW_RDDATA_DBI, AXI_16_DFI_DW_RDDATA_DERR, AXI_16_DFI_DW_RDDATA_VALID, AXI_16_DFI_INIT_COMPLETE, AXI_16_DFI_PHYUPD_REQ, AXI_16_DFI_PHY_LP_STATE, AXI_16_DFI_RST_N_BUF, AXI_16_MC_STATUS, AXI_16_PHY_STATUS, AXI_16_RDATA, AXI_16_RDATA_PARITY, AXI_16_RID, AXI_16_RLAST, AXI_16_RRESP, AXI_16_RVALID, AXI_16_WREADY, AXI_17_ARREADY +, AXI_17_AWREADY, AXI_17_BID, AXI_17_BRESP, AXI_17_BVALID, AXI_17_DFI_AW_AERR_N, AXI_17_DFI_CLK_BUF, AXI_17_DFI_DBI_BYTE_DISABLE, AXI_17_DFI_DW_RDDATA_DBI, AXI_17_DFI_DW_RDDATA_DERR, AXI_17_DFI_DW_RDDATA_VALID, AXI_17_DFI_INIT_COMPLETE, AXI_17_DFI_PHYUPD_REQ, AXI_17_DFI_PHY_LP_STATE, AXI_17_DFI_RST_N_BUF, AXI_17_RDATA, AXI_17_RDATA_PARITY, AXI_17_RID, AXI_17_RLAST, AXI_17_RRESP, AXI_17_RVALID, AXI_17_WREADY +, AXI_18_ARREADY, AXI_18_AWREADY, AXI_18_BID, AXI_18_BRESP, AXI_18_BVALID, AXI_18_DFI_AW_AERR_N, AXI_18_DFI_CLK_BUF, AXI_18_DFI_DBI_BYTE_DISABLE, AXI_18_DFI_DW_RDDATA_DBI, AXI_18_DFI_DW_RDDATA_DERR, AXI_18_DFI_DW_RDDATA_VALID, AXI_18_DFI_INIT_COMPLETE, AXI_18_DFI_PHYUPD_REQ, AXI_18_DFI_PHY_LP_STATE, AXI_18_DFI_RST_N_BUF, AXI_18_MC_STATUS, AXI_18_PHY_STATUS, AXI_18_RDATA, AXI_18_RDATA_PARITY, AXI_18_RID, AXI_18_RLAST +, AXI_18_RRESP, AXI_18_RVALID, AXI_18_WREADY, AXI_19_ARREADY, AXI_19_AWREADY, AXI_19_BID, AXI_19_BRESP, AXI_19_BVALID, AXI_19_DFI_AW_AERR_N, AXI_19_DFI_CLK_BUF, AXI_19_DFI_DBI_BYTE_DISABLE, AXI_19_DFI_DW_RDDATA_DBI, AXI_19_DFI_DW_RDDATA_DERR, AXI_19_DFI_DW_RDDATA_VALID, AXI_19_DFI_INIT_COMPLETE, AXI_19_DFI_PHYUPD_REQ, AXI_19_DFI_PHY_LP_STATE, AXI_19_DFI_RST_N_BUF, AXI_19_RDATA, AXI_19_RDATA_PARITY, AXI_19_RID +, AXI_19_RLAST, AXI_19_RRESP, AXI_19_RVALID, AXI_19_WREADY, AXI_20_ARREADY, AXI_20_AWREADY, AXI_20_BID, AXI_20_BRESP, AXI_20_BVALID, AXI_20_DFI_AW_AERR_N, AXI_20_DFI_CLK_BUF, AXI_20_DFI_DBI_BYTE_DISABLE, AXI_20_DFI_DW_RDDATA_DBI, AXI_20_DFI_DW_RDDATA_DERR, AXI_20_DFI_DW_RDDATA_VALID, AXI_20_DFI_INIT_COMPLETE, AXI_20_DFI_PHYUPD_REQ, AXI_20_DFI_PHY_LP_STATE, AXI_20_DFI_RST_N_BUF, AXI_20_MC_STATUS, AXI_20_PHY_STATUS +, AXI_20_RDATA, AXI_20_RDATA_PARITY, AXI_20_RID, AXI_20_RLAST, AXI_20_RRESP, AXI_20_RVALID, AXI_20_WREADY, AXI_21_ARREADY, AXI_21_AWREADY, AXI_21_BID, AXI_21_BRESP, AXI_21_BVALID, AXI_21_DFI_AW_AERR_N, AXI_21_DFI_CLK_BUF, AXI_21_DFI_DBI_BYTE_DISABLE, AXI_21_DFI_DW_RDDATA_DBI, AXI_21_DFI_DW_RDDATA_DERR, AXI_21_DFI_DW_RDDATA_VALID, AXI_21_DFI_INIT_COMPLETE, AXI_21_DFI_PHYUPD_REQ, AXI_21_DFI_PHY_LP_STATE +, AXI_21_DFI_RST_N_BUF, AXI_21_RDATA, AXI_21_RDATA_PARITY, AXI_21_RID, AXI_21_RLAST, AXI_21_RRESP, AXI_21_RVALID, AXI_21_WREADY, AXI_22_ARREADY, AXI_22_AWREADY, AXI_22_BID, AXI_22_BRESP, AXI_22_BVALID, AXI_22_DFI_AW_AERR_N, AXI_22_DFI_CLK_BUF, AXI_22_DFI_DBI_BYTE_DISABLE, AXI_22_DFI_DW_RDDATA_DBI, AXI_22_DFI_DW_RDDATA_DERR, AXI_22_DFI_DW_RDDATA_VALID, AXI_22_DFI_INIT_COMPLETE, AXI_22_DFI_PHYUPD_REQ +, AXI_22_DFI_PHY_LP_STATE, AXI_22_DFI_RST_N_BUF, AXI_22_MC_STATUS, AXI_22_PHY_STATUS, AXI_22_RDATA, AXI_22_RDATA_PARITY, AXI_22_RID, AXI_22_RLAST, AXI_22_RRESP, AXI_22_RVALID, AXI_22_WREADY, AXI_23_ARREADY, AXI_23_AWREADY, AXI_23_BID, AXI_23_BRESP, AXI_23_BVALID, AXI_23_DFI_AW_AERR_N, AXI_23_DFI_CLK_BUF, AXI_23_DFI_DBI_BYTE_DISABLE, AXI_23_DFI_DW_RDDATA_DBI, AXI_23_DFI_DW_RDDATA_DERR +, AXI_23_DFI_DW_RDDATA_VALID, AXI_23_DFI_INIT_COMPLETE, AXI_23_DFI_PHYUPD_REQ, AXI_23_DFI_PHY_LP_STATE, AXI_23_DFI_RST_N_BUF, AXI_23_RDATA, AXI_23_RDATA_PARITY, AXI_23_RID, AXI_23_RLAST, AXI_23_RRESP, AXI_23_RVALID, AXI_23_WREADY, AXI_24_ARREADY, AXI_24_AWREADY, AXI_24_BID, AXI_24_BRESP, AXI_24_BVALID, AXI_24_DFI_AW_AERR_N, AXI_24_DFI_CLK_BUF, AXI_24_DFI_DBI_BYTE_DISABLE, AXI_24_DFI_DW_RDDATA_DBI +, AXI_24_DFI_DW_RDDATA_DERR, AXI_24_DFI_DW_RDDATA_VALID, AXI_24_DFI_INIT_COMPLETE, AXI_24_DFI_PHYUPD_REQ, AXI_24_DFI_PHY_LP_STATE, AXI_24_DFI_RST_N_BUF, AXI_24_MC_STATUS, AXI_24_PHY_STATUS, AXI_24_RDATA, AXI_24_RDATA_PARITY, AXI_24_RID, AXI_24_RLAST, AXI_24_RRESP, AXI_24_RVALID, AXI_24_WREADY, AXI_25_ARREADY, AXI_25_AWREADY, AXI_25_BID, AXI_25_BRESP, AXI_25_BVALID, AXI_25_DFI_AW_AERR_N +, AXI_25_DFI_CLK_BUF, AXI_25_DFI_DBI_BYTE_DISABLE, AXI_25_DFI_DW_RDDATA_DBI, AXI_25_DFI_DW_RDDATA_DERR, AXI_25_DFI_DW_RDDATA_VALID, AXI_25_DFI_INIT_COMPLETE, AXI_25_DFI_PHYUPD_REQ, AXI_25_DFI_PHY_LP_STATE, AXI_25_DFI_RST_N_BUF, AXI_25_RDATA, AXI_25_RDATA_PARITY, AXI_25_RID, AXI_25_RLAST, AXI_25_RRESP, AXI_25_RVALID, AXI_25_WREADY, AXI_26_ARREADY, AXI_26_AWREADY, AXI_26_BID, AXI_26_BRESP, AXI_26_BVALID +, AXI_26_DFI_AW_AERR_N, AXI_26_DFI_CLK_BUF, AXI_26_DFI_DBI_BYTE_DISABLE, AXI_26_DFI_DW_RDDATA_DBI, AXI_26_DFI_DW_RDDATA_DERR, AXI_26_DFI_DW_RDDATA_VALID, AXI_26_DFI_INIT_COMPLETE, AXI_26_DFI_PHYUPD_REQ, AXI_26_DFI_PHY_LP_STATE, AXI_26_DFI_RST_N_BUF, AXI_26_MC_STATUS, AXI_26_PHY_STATUS, AXI_26_RDATA, AXI_26_RDATA_PARITY, AXI_26_RID, AXI_26_RLAST, AXI_26_RRESP, AXI_26_RVALID, AXI_26_WREADY, AXI_27_ARREADY, AXI_27_AWREADY +, AXI_27_BID, AXI_27_BRESP, AXI_27_BVALID, AXI_27_DFI_AW_AERR_N, AXI_27_DFI_CLK_BUF, AXI_27_DFI_DBI_BYTE_DISABLE, AXI_27_DFI_DW_RDDATA_DBI, AXI_27_DFI_DW_RDDATA_DERR, AXI_27_DFI_DW_RDDATA_VALID, AXI_27_DFI_INIT_COMPLETE, AXI_27_DFI_PHYUPD_REQ, AXI_27_DFI_PHY_LP_STATE, AXI_27_DFI_RST_N_BUF, AXI_27_RDATA, AXI_27_RDATA_PARITY, AXI_27_RID, AXI_27_RLAST, AXI_27_RRESP, AXI_27_RVALID, AXI_27_WREADY, AXI_28_ARREADY +, AXI_28_AWREADY, AXI_28_BID, AXI_28_BRESP, AXI_28_BVALID, AXI_28_DFI_AW_AERR_N, AXI_28_DFI_CLK_BUF, AXI_28_DFI_DBI_BYTE_DISABLE, AXI_28_DFI_DW_RDDATA_DBI, AXI_28_DFI_DW_RDDATA_DERR, AXI_28_DFI_DW_RDDATA_VALID, AXI_28_DFI_INIT_COMPLETE, AXI_28_DFI_PHYUPD_REQ, AXI_28_DFI_PHY_LP_STATE, AXI_28_DFI_RST_N_BUF, AXI_28_MC_STATUS, AXI_28_PHY_STATUS, AXI_28_RDATA, AXI_28_RDATA_PARITY, AXI_28_RID, AXI_28_RLAST, AXI_28_RRESP +, AXI_28_RVALID, AXI_28_WREADY, AXI_29_ARREADY, AXI_29_AWREADY, AXI_29_BID, AXI_29_BRESP, AXI_29_BVALID, AXI_29_DFI_AW_AERR_N, AXI_29_DFI_CLK_BUF, AXI_29_DFI_DBI_BYTE_DISABLE, AXI_29_DFI_DW_RDDATA_DBI, AXI_29_DFI_DW_RDDATA_DERR, AXI_29_DFI_DW_RDDATA_VALID, AXI_29_DFI_INIT_COMPLETE, AXI_29_DFI_PHYUPD_REQ, AXI_29_DFI_PHY_LP_STATE, AXI_29_DFI_RST_N_BUF, AXI_29_RDATA, AXI_29_RDATA_PARITY, AXI_29_RID, AXI_29_RLAST +, AXI_29_RRESP, AXI_29_RVALID, AXI_29_WREADY, AXI_30_ARREADY, AXI_30_AWREADY, AXI_30_BID, AXI_30_BRESP, AXI_30_BVALID, AXI_30_DFI_AW_AERR_N, AXI_30_DFI_CLK_BUF, AXI_30_DFI_DBI_BYTE_DISABLE, AXI_30_DFI_DW_RDDATA_DBI, AXI_30_DFI_DW_RDDATA_DERR, AXI_30_DFI_DW_RDDATA_VALID, AXI_30_DFI_INIT_COMPLETE, AXI_30_DFI_PHYUPD_REQ, AXI_30_DFI_PHY_LP_STATE, AXI_30_DFI_RST_N_BUF, AXI_30_MC_STATUS, AXI_30_PHY_STATUS, AXI_30_RDATA +, AXI_30_RDATA_PARITY, AXI_30_RID, AXI_30_RLAST, AXI_30_RRESP, AXI_30_RVALID, AXI_30_WREADY, AXI_31_ARREADY, AXI_31_AWREADY, AXI_31_BID, AXI_31_BRESP, AXI_31_BVALID, AXI_31_DFI_AW_AERR_N, AXI_31_DFI_CLK_BUF, AXI_31_DFI_DBI_BYTE_DISABLE, AXI_31_DFI_DW_RDDATA_DBI, AXI_31_DFI_DW_RDDATA_DERR, AXI_31_DFI_DW_RDDATA_VALID, AXI_31_DFI_INIT_COMPLETE, AXI_31_DFI_PHYUPD_REQ, AXI_31_DFI_PHY_LP_STATE, AXI_31_DFI_RST_N_BUF +, AXI_31_RDATA, AXI_31_RDATA_PARITY, AXI_31_RID, AXI_31_RLAST, AXI_31_RRESP, AXI_31_RVALID, AXI_31_WREADY, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, DRAM_1_STAT_CATTRIP, DRAM_1_STAT_TEMP, APB_0_PADDR, APB_0_PCLK, APB_0_PENABLE, APB_0_PRESET_N, APB_0_PSEL, APB_0_PWDATA, APB_0_PWRITE, APB_1_PADDR, APB_1_PCLK, APB_1_PENABLE +, APB_1_PRESET_N, APB_1_PSEL, APB_1_PWDATA, APB_1_PWRITE, AXI_00_ACLK, AXI_00_ARADDR, AXI_00_ARBURST, AXI_00_ARESET_N, AXI_00_ARID, AXI_00_ARLEN, AXI_00_ARSIZE, AXI_00_ARVALID, AXI_00_AWADDR, AXI_00_AWBURST, AXI_00_AWID, AXI_00_AWLEN, AXI_00_AWSIZE, AXI_00_AWVALID, AXI_00_BREADY, AXI_00_DFI_LP_PWR_X_REQ, AXI_00_RREADY +, AXI_00_WDATA, AXI_00_WDATA_PARITY, AXI_00_WLAST, AXI_00_WSTRB, AXI_00_WVALID, AXI_01_ACLK, AXI_01_ARADDR, AXI_01_ARBURST, AXI_01_ARESET_N, AXI_01_ARID, AXI_01_ARLEN, AXI_01_ARSIZE, AXI_01_ARVALID, AXI_01_AWADDR, AXI_01_AWBURST, AXI_01_AWID, AXI_01_AWLEN, AXI_01_AWSIZE, AXI_01_AWVALID, AXI_01_BREADY, AXI_01_DFI_LP_PWR_X_REQ +, AXI_01_RREADY, AXI_01_WDATA, AXI_01_WDATA_PARITY, AXI_01_WLAST, AXI_01_WSTRB, AXI_01_WVALID, AXI_02_ACLK, AXI_02_ARADDR, AXI_02_ARBURST, AXI_02_ARESET_N, AXI_02_ARID, AXI_02_ARLEN, AXI_02_ARSIZE, AXI_02_ARVALID, AXI_02_AWADDR, AXI_02_AWBURST, AXI_02_AWID, AXI_02_AWLEN, AXI_02_AWSIZE, AXI_02_AWVALID, AXI_02_BREADY +, AXI_02_DFI_LP_PWR_X_REQ, AXI_02_RREADY, AXI_02_WDATA, AXI_02_WDATA_PARITY, AXI_02_WLAST, AXI_02_WSTRB, AXI_02_WVALID, AXI_03_ACLK, AXI_03_ARADDR, AXI_03_ARBURST, AXI_03_ARESET_N, AXI_03_ARID, AXI_03_ARLEN, AXI_03_ARSIZE, AXI_03_ARVALID, AXI_03_AWADDR, AXI_03_AWBURST, AXI_03_AWID, AXI_03_AWLEN, AXI_03_AWSIZE, AXI_03_AWVALID +, AXI_03_BREADY, AXI_03_DFI_LP_PWR_X_REQ, AXI_03_RREADY, AXI_03_WDATA, AXI_03_WDATA_PARITY, AXI_03_WLAST, AXI_03_WSTRB, AXI_03_WVALID, AXI_04_ACLK, AXI_04_ARADDR, AXI_04_ARBURST, AXI_04_ARESET_N, AXI_04_ARID, AXI_04_ARLEN, AXI_04_ARSIZE, AXI_04_ARVALID, AXI_04_AWADDR, AXI_04_AWBURST, AXI_04_AWID, AXI_04_AWLEN, AXI_04_AWSIZE +, AXI_04_AWVALID, AXI_04_BREADY, AXI_04_DFI_LP_PWR_X_REQ, AXI_04_RREADY, AXI_04_WDATA, AXI_04_WDATA_PARITY, AXI_04_WLAST, AXI_04_WSTRB, AXI_04_WVALID, AXI_05_ACLK, AXI_05_ARADDR, AXI_05_ARBURST, AXI_05_ARESET_N, AXI_05_ARID, AXI_05_ARLEN, AXI_05_ARSIZE, AXI_05_ARVALID, AXI_05_AWADDR, AXI_05_AWBURST, AXI_05_AWID, AXI_05_AWLEN +, AXI_05_AWSIZE, AXI_05_AWVALID, AXI_05_BREADY, AXI_05_DFI_LP_PWR_X_REQ, AXI_05_RREADY, AXI_05_WDATA, AXI_05_WDATA_PARITY, AXI_05_WLAST, AXI_05_WSTRB, AXI_05_WVALID, AXI_06_ACLK, AXI_06_ARADDR, AXI_06_ARBURST, AXI_06_ARESET_N, AXI_06_ARID, AXI_06_ARLEN, AXI_06_ARSIZE, AXI_06_ARVALID, AXI_06_AWADDR, AXI_06_AWBURST, AXI_06_AWID +, AXI_06_AWLEN, AXI_06_AWSIZE, AXI_06_AWVALID, AXI_06_BREADY, AXI_06_DFI_LP_PWR_X_REQ, AXI_06_RREADY, AXI_06_WDATA, AXI_06_WDATA_PARITY, AXI_06_WLAST, AXI_06_WSTRB, AXI_06_WVALID, AXI_07_ACLK, AXI_07_ARADDR, AXI_07_ARBURST, AXI_07_ARESET_N, AXI_07_ARID, AXI_07_ARLEN, AXI_07_ARSIZE, AXI_07_ARVALID, AXI_07_AWADDR, AXI_07_AWBURST +, AXI_07_AWID, AXI_07_AWLEN, AXI_07_AWSIZE, AXI_07_AWVALID, AXI_07_BREADY, AXI_07_DFI_LP_PWR_X_REQ, AXI_07_RREADY, AXI_07_WDATA, AXI_07_WDATA_PARITY, AXI_07_WLAST, AXI_07_WSTRB, AXI_07_WVALID, AXI_08_ACLK, AXI_08_ARADDR, AXI_08_ARBURST, AXI_08_ARESET_N, AXI_08_ARID, AXI_08_ARLEN, AXI_08_ARSIZE, AXI_08_ARVALID, AXI_08_AWADDR +, AXI_08_AWBURST, AXI_08_AWID, AXI_08_AWLEN, AXI_08_AWSIZE, AXI_08_AWVALID, AXI_08_BREADY, AXI_08_DFI_LP_PWR_X_REQ, AXI_08_RREADY, AXI_08_WDATA, AXI_08_WDATA_PARITY, AXI_08_WLAST, AXI_08_WSTRB, AXI_08_WVALID, AXI_09_ACLK, AXI_09_ARADDR, AXI_09_ARBURST, AXI_09_ARESET_N, AXI_09_ARID, AXI_09_ARLEN, AXI_09_ARSIZE, AXI_09_ARVALID +, AXI_09_AWADDR, AXI_09_AWBURST, AXI_09_AWID, AXI_09_AWLEN, AXI_09_AWSIZE, AXI_09_AWVALID, AXI_09_BREADY, AXI_09_DFI_LP_PWR_X_REQ, AXI_09_RREADY, AXI_09_WDATA, AXI_09_WDATA_PARITY, AXI_09_WLAST, AXI_09_WSTRB, AXI_09_WVALID, AXI_10_ACLK, AXI_10_ARADDR, AXI_10_ARBURST, AXI_10_ARESET_N, AXI_10_ARID, AXI_10_ARLEN, AXI_10_ARSIZE +, AXI_10_ARVALID, AXI_10_AWADDR, AXI_10_AWBURST, AXI_10_AWID, AXI_10_AWLEN, AXI_10_AWSIZE, AXI_10_AWVALID, AXI_10_BREADY, AXI_10_DFI_LP_PWR_X_REQ, AXI_10_RREADY, AXI_10_WDATA, AXI_10_WDATA_PARITY, AXI_10_WLAST, AXI_10_WSTRB, AXI_10_WVALID, AXI_11_ACLK, AXI_11_ARADDR, AXI_11_ARBURST, AXI_11_ARESET_N, AXI_11_ARID, AXI_11_ARLEN +, AXI_11_ARSIZE, AXI_11_ARVALID, AXI_11_AWADDR, AXI_11_AWBURST, AXI_11_AWID, AXI_11_AWLEN, AXI_11_AWSIZE, AXI_11_AWVALID, AXI_11_BREADY, AXI_11_DFI_LP_PWR_X_REQ, AXI_11_RREADY, AXI_11_WDATA, AXI_11_WDATA_PARITY, AXI_11_WLAST, AXI_11_WSTRB, AXI_11_WVALID, AXI_12_ACLK, AXI_12_ARADDR, AXI_12_ARBURST, AXI_12_ARESET_N, AXI_12_ARID +, AXI_12_ARLEN, AXI_12_ARSIZE, AXI_12_ARVALID, AXI_12_AWADDR, AXI_12_AWBURST, AXI_12_AWID, AXI_12_AWLEN, AXI_12_AWSIZE, AXI_12_AWVALID, AXI_12_BREADY, AXI_12_DFI_LP_PWR_X_REQ, AXI_12_RREADY, AXI_12_WDATA, AXI_12_WDATA_PARITY, AXI_12_WLAST, AXI_12_WSTRB, AXI_12_WVALID, AXI_13_ACLK, AXI_13_ARADDR, AXI_13_ARBURST, AXI_13_ARESET_N +, AXI_13_ARID, AXI_13_ARLEN, AXI_13_ARSIZE, AXI_13_ARVALID, AXI_13_AWADDR, AXI_13_AWBURST, AXI_13_AWID, AXI_13_AWLEN, AXI_13_AWSIZE, AXI_13_AWVALID, AXI_13_BREADY, AXI_13_DFI_LP_PWR_X_REQ, AXI_13_RREADY, AXI_13_WDATA, AXI_13_WDATA_PARITY, AXI_13_WLAST, AXI_13_WSTRB, AXI_13_WVALID, AXI_14_ACLK, AXI_14_ARADDR, AXI_14_ARBURST +, AXI_14_ARESET_N, AXI_14_ARID, AXI_14_ARLEN, AXI_14_ARSIZE, AXI_14_ARVALID, AXI_14_AWADDR, AXI_14_AWBURST, AXI_14_AWID, AXI_14_AWLEN, AXI_14_AWSIZE, AXI_14_AWVALID, AXI_14_BREADY, AXI_14_DFI_LP_PWR_X_REQ, AXI_14_RREADY, AXI_14_WDATA, AXI_14_WDATA_PARITY, AXI_14_WLAST, AXI_14_WSTRB, AXI_14_WVALID, AXI_15_ACLK, AXI_15_ARADDR +, AXI_15_ARBURST, AXI_15_ARESET_N, AXI_15_ARID, AXI_15_ARLEN, AXI_15_ARSIZE, AXI_15_ARVALID, AXI_15_AWADDR, AXI_15_AWBURST, AXI_15_AWID, AXI_15_AWLEN, AXI_15_AWSIZE, AXI_15_AWVALID, AXI_15_BREADY, AXI_15_DFI_LP_PWR_X_REQ, AXI_15_RREADY, AXI_15_WDATA, AXI_15_WDATA_PARITY, AXI_15_WLAST, AXI_15_WSTRB, AXI_15_WVALID, AXI_16_ACLK +, AXI_16_ARADDR, AXI_16_ARBURST, AXI_16_ARESET_N, AXI_16_ARID, AXI_16_ARLEN, AXI_16_ARSIZE, AXI_16_ARVALID, AXI_16_AWADDR, AXI_16_AWBURST, AXI_16_AWID, AXI_16_AWLEN, AXI_16_AWSIZE, AXI_16_AWVALID, AXI_16_BREADY, AXI_16_DFI_LP_PWR_X_REQ, AXI_16_RREADY, AXI_16_WDATA, AXI_16_WDATA_PARITY, AXI_16_WLAST, AXI_16_WSTRB, AXI_16_WVALID +, AXI_17_ACLK, AXI_17_ARADDR, AXI_17_ARBURST, AXI_17_ARESET_N, AXI_17_ARID, AXI_17_ARLEN, AXI_17_ARSIZE, AXI_17_ARVALID, AXI_17_AWADDR, AXI_17_AWBURST, AXI_17_AWID, AXI_17_AWLEN, AXI_17_AWSIZE, AXI_17_AWVALID, AXI_17_BREADY, AXI_17_DFI_LP_PWR_X_REQ, AXI_17_RREADY, AXI_17_WDATA, AXI_17_WDATA_PARITY, AXI_17_WLAST, AXI_17_WSTRB +, AXI_17_WVALID, AXI_18_ACLK, AXI_18_ARADDR, AXI_18_ARBURST, AXI_18_ARESET_N, AXI_18_ARID, AXI_18_ARLEN, AXI_18_ARSIZE, AXI_18_ARVALID, AXI_18_AWADDR, AXI_18_AWBURST, AXI_18_AWID, AXI_18_AWLEN, AXI_18_AWSIZE, AXI_18_AWVALID, AXI_18_BREADY, AXI_18_DFI_LP_PWR_X_REQ, AXI_18_RREADY, AXI_18_WDATA, AXI_18_WDATA_PARITY, AXI_18_WLAST +, AXI_18_WSTRB, AXI_18_WVALID, AXI_19_ACLK, AXI_19_ARADDR, AXI_19_ARBURST, AXI_19_ARESET_N, AXI_19_ARID, AXI_19_ARLEN, AXI_19_ARSIZE, AXI_19_ARVALID, AXI_19_AWADDR, AXI_19_AWBURST, AXI_19_AWID, AXI_19_AWLEN, AXI_19_AWSIZE, AXI_19_AWVALID, AXI_19_BREADY, AXI_19_DFI_LP_PWR_X_REQ, AXI_19_RREADY, AXI_19_WDATA, AXI_19_WDATA_PARITY +, AXI_19_WLAST, AXI_19_WSTRB, AXI_19_WVALID, AXI_20_ACLK, AXI_20_ARADDR, AXI_20_ARBURST, AXI_20_ARESET_N, AXI_20_ARID, AXI_20_ARLEN, AXI_20_ARSIZE, AXI_20_ARVALID, AXI_20_AWADDR, AXI_20_AWBURST, AXI_20_AWID, AXI_20_AWLEN, AXI_20_AWSIZE, AXI_20_AWVALID, AXI_20_BREADY, AXI_20_DFI_LP_PWR_X_REQ, AXI_20_RREADY, AXI_20_WDATA +, AXI_20_WDATA_PARITY, AXI_20_WLAST, AXI_20_WSTRB, AXI_20_WVALID, AXI_21_ACLK, AXI_21_ARADDR, AXI_21_ARBURST, AXI_21_ARESET_N, AXI_21_ARID, AXI_21_ARLEN, AXI_21_ARSIZE, AXI_21_ARVALID, AXI_21_AWADDR, AXI_21_AWBURST, AXI_21_AWID, AXI_21_AWLEN, AXI_21_AWSIZE, AXI_21_AWVALID, AXI_21_BREADY, AXI_21_DFI_LP_PWR_X_REQ, AXI_21_RREADY +, AXI_21_WDATA, AXI_21_WDATA_PARITY, AXI_21_WLAST, AXI_21_WSTRB, AXI_21_WVALID, AXI_22_ACLK, AXI_22_ARADDR, AXI_22_ARBURST, AXI_22_ARESET_N, AXI_22_ARID, AXI_22_ARLEN, AXI_22_ARSIZE, AXI_22_ARVALID, AXI_22_AWADDR, AXI_22_AWBURST, AXI_22_AWID, AXI_22_AWLEN, AXI_22_AWSIZE, AXI_22_AWVALID, AXI_22_BREADY, AXI_22_DFI_LP_PWR_X_REQ +, AXI_22_RREADY, AXI_22_WDATA, AXI_22_WDATA_PARITY, AXI_22_WLAST, AXI_22_WSTRB, AXI_22_WVALID, AXI_23_ACLK, AXI_23_ARADDR, AXI_23_ARBURST, AXI_23_ARESET_N, AXI_23_ARID, AXI_23_ARLEN, AXI_23_ARSIZE, AXI_23_ARVALID, AXI_23_AWADDR, AXI_23_AWBURST, AXI_23_AWID, AXI_23_AWLEN, AXI_23_AWSIZE, AXI_23_AWVALID, AXI_23_BREADY +, AXI_23_DFI_LP_PWR_X_REQ, AXI_23_RREADY, AXI_23_WDATA, AXI_23_WDATA_PARITY, AXI_23_WLAST, AXI_23_WSTRB, AXI_23_WVALID, AXI_24_ACLK, AXI_24_ARADDR, AXI_24_ARBURST, AXI_24_ARESET_N, AXI_24_ARID, AXI_24_ARLEN, AXI_24_ARSIZE, AXI_24_ARVALID, AXI_24_AWADDR, AXI_24_AWBURST, AXI_24_AWID, AXI_24_AWLEN, AXI_24_AWSIZE, AXI_24_AWVALID +, AXI_24_BREADY, AXI_24_DFI_LP_PWR_X_REQ, AXI_24_RREADY, AXI_24_WDATA, AXI_24_WDATA_PARITY, AXI_24_WLAST, AXI_24_WSTRB, AXI_24_WVALID, AXI_25_ACLK, AXI_25_ARADDR, AXI_25_ARBURST, AXI_25_ARESET_N, AXI_25_ARID, AXI_25_ARLEN, AXI_25_ARSIZE, AXI_25_ARVALID, AXI_25_AWADDR, AXI_25_AWBURST, AXI_25_AWID, AXI_25_AWLEN, AXI_25_AWSIZE +, AXI_25_AWVALID, AXI_25_BREADY, AXI_25_DFI_LP_PWR_X_REQ, AXI_25_RREADY, AXI_25_WDATA, AXI_25_WDATA_PARITY, AXI_25_WLAST, AXI_25_WSTRB, AXI_25_WVALID, AXI_26_ACLK, AXI_26_ARADDR, AXI_26_ARBURST, AXI_26_ARESET_N, AXI_26_ARID, AXI_26_ARLEN, AXI_26_ARSIZE, AXI_26_ARVALID, AXI_26_AWADDR, AXI_26_AWBURST, AXI_26_AWID, AXI_26_AWLEN +, AXI_26_AWSIZE, AXI_26_AWVALID, AXI_26_BREADY, AXI_26_DFI_LP_PWR_X_REQ, AXI_26_RREADY, AXI_26_WDATA, AXI_26_WDATA_PARITY, AXI_26_WLAST, AXI_26_WSTRB, AXI_26_WVALID, AXI_27_ACLK, AXI_27_ARADDR, AXI_27_ARBURST, AXI_27_ARESET_N, AXI_27_ARID, AXI_27_ARLEN, AXI_27_ARSIZE, AXI_27_ARVALID, AXI_27_AWADDR, AXI_27_AWBURST, AXI_27_AWID +, AXI_27_AWLEN, AXI_27_AWSIZE, AXI_27_AWVALID, AXI_27_BREADY, AXI_27_DFI_LP_PWR_X_REQ, AXI_27_RREADY, AXI_27_WDATA, AXI_27_WDATA_PARITY, AXI_27_WLAST, AXI_27_WSTRB, AXI_27_WVALID, AXI_28_ACLK, AXI_28_ARADDR, AXI_28_ARBURST, AXI_28_ARESET_N, AXI_28_ARID, AXI_28_ARLEN, AXI_28_ARSIZE, AXI_28_ARVALID, AXI_28_AWADDR, AXI_28_AWBURST +, AXI_28_AWID, AXI_28_AWLEN, AXI_28_AWSIZE, AXI_28_AWVALID, AXI_28_BREADY, AXI_28_DFI_LP_PWR_X_REQ, AXI_28_RREADY, AXI_28_WDATA, AXI_28_WDATA_PARITY, AXI_28_WLAST, AXI_28_WSTRB, AXI_28_WVALID, AXI_29_ACLK, AXI_29_ARADDR, AXI_29_ARBURST, AXI_29_ARESET_N, AXI_29_ARID, AXI_29_ARLEN, AXI_29_ARSIZE, AXI_29_ARVALID, AXI_29_AWADDR +, AXI_29_AWBURST, AXI_29_AWID, AXI_29_AWLEN, AXI_29_AWSIZE, AXI_29_AWVALID, AXI_29_BREADY, AXI_29_DFI_LP_PWR_X_REQ, AXI_29_RREADY, AXI_29_WDATA, AXI_29_WDATA_PARITY, AXI_29_WLAST, AXI_29_WSTRB, AXI_29_WVALID, AXI_30_ACLK, AXI_30_ARADDR, AXI_30_ARBURST, AXI_30_ARESET_N, AXI_30_ARID, AXI_30_ARLEN, AXI_30_ARSIZE, AXI_30_ARVALID +, AXI_30_AWADDR, AXI_30_AWBURST, AXI_30_AWID, AXI_30_AWLEN, AXI_30_AWSIZE, AXI_30_AWVALID, AXI_30_BREADY, AXI_30_DFI_LP_PWR_X_REQ, AXI_30_RREADY, AXI_30_WDATA, AXI_30_WDATA_PARITY, AXI_30_WLAST, AXI_30_WSTRB, AXI_30_WVALID, AXI_31_ACLK, AXI_31_ARADDR, AXI_31_ARBURST, AXI_31_ARESET_N, AXI_31_ARID, AXI_31_ARLEN, AXI_31_ARSIZE +, AXI_31_ARVALID, AXI_31_AWADDR, AXI_31_AWBURST, AXI_31_AWID, AXI_31_AWLEN, AXI_31_AWSIZE, AXI_31_AWVALID, AXI_31_BREADY, AXI_31_DFI_LP_PWR_X_REQ, AXI_31_RREADY, AXI_31_WDATA, AXI_31_WDATA_PARITY, AXI_31_WLAST, AXI_31_WSTRB, AXI_31_WVALID, BSCAN_DRCK_0, BSCAN_DRCK_1, BSCAN_TCK_0, BSCAN_TCK_1, HBM_REF_CLK_0, HBM_REF_CLK_1 +, MBIST_EN_00, MBIST_EN_01, MBIST_EN_02, MBIST_EN_03, MBIST_EN_04, MBIST_EN_05, MBIST_EN_06, MBIST_EN_07, MBIST_EN_08, MBIST_EN_09, MBIST_EN_10, MBIST_EN_11, MBIST_EN_12, MBIST_EN_13, MBIST_EN_14, MBIST_EN_15); parameter CLK_SEL_00 = "FALSE"; parameter CLK_SEL_01 = "FALSE"; parameter CLK_SEL_02 = "FALSE"; @@ -31096,7 +31672,16 @@ module HBM_TWO_STACK_INTF (...); input MBIST_EN_15; endmodule -module PPC405_ADV (...); +module PPC405_ADV(APUFCMDECODED, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMLOADDVALID, APUFCMOPERANDVALID, APUFCMWRITEBACKOK, APUFCMXERCA, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGLOADDATAONAPUDBUS, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405JTGCAPTUREDR, C405JTGEXTEST +, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUCACHEABLE, C405PLBICUREQUEST, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE +, C405TRCTRIGGEREVENTOUT, C405XXXMACHINECHECK, DCREMACCLK, DCREMACENABLER, DCREMACREAD, DCREMACWRITE, DSOCMBRAMEN, DSOCMBUSY, DSOCMRDADDRVALID, DSOCMWRADDRVALID, EXTDCRREAD, EXTDCRWRITE, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMDCRBRAMEVENEN, ISOCMDCRBRAMODDEN, ISOCMDCRBRAMRDSELECT, C405TRCTRIGGEREVENTTYPE, C405PLBDCUPRIORITY, C405PLBICUPRIORITY +, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405DBGWBIAR, C405PLBICUABUS, APUFCMDECUDI, APUFCMINSTRUCTION, APUFCMLOADDATA, APUFCMRADATA, APUFCMRBDATA, C405PLBDCUABUS, DCREMACDBUS, DSOCMBRAMWRDBUS, EXTDCRDBUSOUT, ISOCMBRAMWRDBUS, APUFCMLOADBYTEEN, C405TRCTRACESTATUS, DSOCMBRAMBYTEWRITE, C405PLBDCUWRDBUS, C405PLBDCUBE, EXTDCRABUS, C405PLBICUSIZE +, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, DSOCMBRAMABUS, DCREMACABUS, BRAMDSOCMCLK, BRAMISOCMCLK, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405SYNCBYPASS, CPMC405TIMERCLKEN, CPMC405TIMERTICK, CPMDCRCLK, CPMFCMCLK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DSOCMRWCOMPLETE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ +, EMACDCRACK, EXTDCRACK, FCMAPUDCDCREN, FCMAPUDCDFORCEALIGN, FCMAPUDCDFORCEBESTEERING, FCMAPUDCDFPUOP, FCMAPUDCDGPRWRITE, FCMAPUDCDLDSTBYTE, FCMAPUDCDLDSTDW, FCMAPUDCDLDSTHW, FCMAPUDCDLDSTQW, FCMAPUDCDLDSTWD, FCMAPUDCDLOAD, FCMAPUDCDPRIVOP, FCMAPUDCDRAEN, FCMAPUDCDRBEN, FCMAPUDCDSTORE, FCMAPUDCDTRAPBE, FCMAPUDCDTRAPLE, FCMAPUDCDUPDATE, FCMAPUDCDXERCAEN +, FCMAPUDCDXEROVEN, FCMAPUDECODEBUSY, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUEXEBLOCKINGMCO, FCMAPUEXENONBLOCKINGMCO, FCMAPUINSTRACK, FCMAPULOADWAIT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUXERCA, FCMAPUXEROV, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST +, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEPVRBIT10, TIEPVRBIT11, TIEPVRBIT28 +, TIEPVRBIT29, TIEPVRBIT30, TIEPVRBIT31, TIEPVRBIT8, TIEPVRBIT9, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN, TIEAPUCONTROL, TIEAPUUDI1, TIEAPUUDI2, TIEAPUUDI3, TIEAPUUDI4, TIEAPUUDI5, TIEAPUUDI6, TIEAPUUDI7, TIEAPUUDI8, FCMAPUEXECRFIELD, BRAMDSOCMRDDBUS, BRAMISOCMDCRRDDBUS, EMACDCRDBUS, EXTDCRDBUSIN +, FCMAPURESULT, FCMAPUCR, TIEDCRADDR, BRAMISOCMRDDBUS, PLBC405DCURDDBUS, PLBC405ICURDDBUS, DSARCVALUE, DSCNTLVALUE, ISARCVALUE, ISCNTLVALUE, PLBC405DCURDWDADDR, PLBC405ICURDWDADDR); parameter in_delay=100; parameter out_delay=100; output APUFCMDECODED; @@ -31302,7 +31887,22 @@ module PPC405_ADV (...); input [1:3] PLBC405ICURDWDADDR; endmodule -module PPC440 (...); +module PPC440(APUFCMDECFPUOP, APUFCMDECLOAD, APUFCMDECNONAUTON, APUFCMDECSTORE, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMLOADDVALID, APUFCMMSRFE0, APUFCMMSRFE1, APUFCMNEXTINSTRREADY, APUFCMOPERANDVALID, APUFCMWRITEBACKOK, C440CPMCORESLEEPREQ, C440CPMDECIRPTREQ, C440CPMFITIRPTREQ, C440CPMMSRCE, C440CPMMSREE, C440CPMTIMERRESETREQ, C440CPMWDIRPTREQ +, C440JTGTDO, C440JTGTDOEN, C440MACHINECHECK, C440RSTCHIPRESETREQ, C440RSTCORERESETREQ, C440RSTSYSTEMRESETREQ, C440TRCCYCLE, C440TRCTRIGGEREVENTOUT, DMA0LLRSTENGINEACK, DMA0LLRXDSTRDYN, DMA0LLTXEOFN, DMA0LLTXEOPN, DMA0LLTXSOFN, DMA0LLTXSOPN, DMA0LLTXSRCRDYN, DMA0RXIRQ, DMA0TXIRQ, DMA1LLRSTENGINEACK, DMA1LLRXDSTRDYN, DMA1LLTXEOFN, DMA1LLTXEOPN +, DMA1LLTXSOFN, DMA1LLTXSOPN, DMA1LLTXSRCRDYN, DMA1RXIRQ, DMA1TXIRQ, DMA2LLRSTENGINEACK, DMA2LLRXDSTRDYN, DMA2LLTXEOFN, DMA2LLTXEOPN, DMA2LLTXSOFN, DMA2LLTXSOPN, DMA2LLTXSRCRDYN, DMA2RXIRQ, DMA2TXIRQ, DMA3LLRSTENGINEACK, DMA3LLRXDSTRDYN, DMA3LLTXEOFN, DMA3LLTXEOPN, DMA3LLTXSOFN, DMA3LLTXSOPN, DMA3LLTXSRCRDYN +, DMA3RXIRQ, DMA3TXIRQ, MIMCADDRESSVALID, MIMCBANKCONFLICT, MIMCREADNOTWRITE, MIMCROWCONFLICT, MIMCWRITEDATAVALID, PPCCPMINTERCONNECTBUSY, PPCDMDCRREAD, PPCDMDCRWRITE, PPCDSDCRACK, PPCDSDCRTIMEOUTWAIT, PPCEICINTERCONNECTIRQ, PPCMPLBABORT, PPCMPLBBUSLOCK, PPCMPLBLOCKERR, PPCMPLBRDBURST, PPCMPLBREQUEST, PPCMPLBRNW, PPCMPLBWRBURST, PPCS0PLBADDRACK +, PPCS0PLBRDBTERM, PPCS0PLBRDCOMP, PPCS0PLBRDDACK, PPCS0PLBREARBITRATE, PPCS0PLBWAIT, PPCS0PLBWRBTERM, PPCS0PLBWRCOMP, PPCS0PLBWRDACK, PPCS1PLBADDRACK, PPCS1PLBRDBTERM, PPCS1PLBRDCOMP, PPCS1PLBRDDACK, PPCS1PLBREARBITRATE, PPCS1PLBWAIT, PPCS1PLBWRBTERM, PPCS1PLBWRCOMP, PPCS1PLBWRDACK, APUFCMLOADDATA, MIMCWRITEDATA, PPCMPLBWRDBUS, PPCS0PLBRDDBUS +, PPCS1PLBRDDBUS, C440TRCTRIGGEREVENTTYPE, MIMCBYTEENABLE, PPCMPLBBE, PPCMPLBTATTRIBUTE, PPCMPLBPRIORITY, PPCS0PLBSSIZE, PPCS1PLBSSIZE, APUFCMDECLDSTXFERSIZE, C440TRCBRANCHSTATUS, PPCMPLBTYPE, APUFCMINSTRUCTION, APUFCMRADATA, APUFCMRBDATA, DMA0LLTXD, DMA1LLTXD, DMA2LLTXD, DMA3LLTXD, PPCDMDCRDBUSOUT, PPCDSDCRDBUSIN, PPCMPLBABUS +, MIMCADDRESS, APUFCMDECUDI, APUFCMLOADBYTEADDR, DMA0LLTXREM, DMA1LLTXREM, DMA2LLTXREM, DMA3LLTXREM, PPCMPLBSIZE, PPCS0PLBMBUSY, PPCS0PLBMIRQ, PPCS0PLBMRDERR, PPCS0PLBMWRERR, PPCS0PLBRDWDADDR, PPCS1PLBMBUSY, PPCS1PLBMIRQ, PPCS1PLBMRDERR, PPCS1PLBMWRERR, PPCS1PLBRDWDADDR, C440TRCEXECUTIONSTATUS, C440TRCTRACESTATUS, C440DBGSYSTEMCONTROL +, PPCDMDCRABUS, PPCDMDCRUABUS, PPCMPLBUABUS, CPMC440CLK, CPMC440CLKEN, CPMC440CORECLOCKINACTIVE, CPMC440TIMERCLOCK, CPMDCRCLK, CPMDMA0LLCLK, CPMDMA1LLCLK, CPMDMA2LLCLK, CPMDMA3LLCLK, CPMFCMCLK, CPMINTERCONNECTCLK, CPMINTERCONNECTCLKEN, CPMINTERCONNECTCLKNTO1, CPMMCCLK, CPMPPCMPLBCLK, CPMPPCS0PLBCLK, CPMPPCS1PLBCLK, DBGC440DEBUGHALT +, DBGC440UNCONDDEBUGEVENT, DCRPPCDMACK, DCRPPCDMTIMEOUTWAIT, DCRPPCDSREAD, DCRPPCDSWRITE, EICC440CRITIRQ, EICC440EXTIRQ, FCMAPUCONFIRMINSTR, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUFPSCRFEX, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, JTGC440TCK, JTGC440TDI, JTGC440TMS, JTGC440TRSTNEG, LLDMA0RSTENGINEREQ, LLDMA0RXEOFN, LLDMA0RXEOPN, LLDMA0RXSOFN +, LLDMA0RXSOPN, LLDMA0RXSRCRDYN, LLDMA0TXDSTRDYN, LLDMA1RSTENGINEREQ, LLDMA1RXEOFN, LLDMA1RXEOPN, LLDMA1RXSOFN, LLDMA1RXSOPN, LLDMA1RXSRCRDYN, LLDMA1TXDSTRDYN, LLDMA2RSTENGINEREQ, LLDMA2RXEOFN, LLDMA2RXEOPN, LLDMA2RXSOFN, LLDMA2RXSOPN, LLDMA2RXSRCRDYN, LLDMA2TXDSTRDYN, LLDMA3RSTENGINEREQ, LLDMA3RXEOFN, LLDMA3RXEOPN, LLDMA3RXSOFN +, LLDMA3RXSOPN, LLDMA3RXSRCRDYN, LLDMA3TXDSTRDYN, MCMIADDRREADYTOACCEPT, MCMIREADDATAERR, MCMIREADDATAVALID, PLBPPCMADDRACK, PLBPPCMMBUSY, PLBPPCMMIRQ, PLBPPCMMRDERR, PLBPPCMMWRERR, PLBPPCMRDBTERM, PLBPPCMRDDACK, PLBPPCMRDPENDREQ, PLBPPCMREARBITRATE, PLBPPCMTIMEOUT, PLBPPCMWRBTERM, PLBPPCMWRDACK, PLBPPCMWRPENDREQ, PLBPPCS0ABORT, PLBPPCS0BUSLOCK +, PLBPPCS0LOCKERR, PLBPPCS0PAVALID, PLBPPCS0RDBURST, PLBPPCS0RDPENDREQ, PLBPPCS0RDPRIM, PLBPPCS0RNW, PLBPPCS0SAVALID, PLBPPCS0WRBURST, PLBPPCS0WRPENDREQ, PLBPPCS0WRPRIM, PLBPPCS1ABORT, PLBPPCS1BUSLOCK, PLBPPCS1LOCKERR, PLBPPCS1PAVALID, PLBPPCS1RDBURST, PLBPPCS1RDPENDREQ, PLBPPCS1RDPRIM, PLBPPCS1RNW, PLBPPCS1SAVALID, PLBPPCS1WRBURST, PLBPPCS1WRPENDREQ +, PLBPPCS1WRPRIM, RSTC440RESETCHIP, RSTC440RESETCORE, RSTC440RESETSYSTEM, TIEC440ENDIANRESET, TRCC440TRACEDISABLE, TRCC440TRIGGEREVENTIN, FCMAPUSTOREDATA, MCMIREADDATA, PLBPPCMRDDBUS, PLBPPCS0WRDBUS, PLBPPCS1WRDBUS, PLBPPCS0BE, PLBPPCS0TATTRIBUTE, PLBPPCS1BE, PLBPPCS1TATTRIBUTE, PLBPPCMRDPENDPRI, PLBPPCMREQPRI, PLBPPCMSSIZE, PLBPPCMWRPENDPRI, PLBPPCS0MASTERID +, PLBPPCS0MSIZE, PLBPPCS0RDPENDPRI, PLBPPCS0REQPRI, PLBPPCS0WRPENDPRI, PLBPPCS1MASTERID, PLBPPCS1MSIZE, PLBPPCS1RDPENDPRI, PLBPPCS1REQPRI, PLBPPCS1WRPENDPRI, TIEC440DCURDLDCACHEPLBPRIO, TIEC440DCURDNONCACHEPLBPRIO, TIEC440DCURDTOUCHPLBPRIO, TIEC440DCURDURGENTPLBPRIO, TIEC440DCUWRFLUSHPLBPRIO, TIEC440DCUWRSTOREPLBPRIO, TIEC440DCUWRURGENTPLBPRIO, TIEC440ICURDFETCHPLBPRIO, TIEC440ICURDSPECPLBPRIO, TIEC440ICURDTOUCHPLBPRIO, TIEDCRBASEADDR, PLBPPCS0TYPE +, PLBPPCS1TYPE, DCRPPCDMDBUSIN, DCRPPCDSDBUSOUT, FCMAPURESULT, LLDMA0RXD, LLDMA1RXD, LLDMA2RXD, LLDMA3RXD, PLBPPCS0ABUS, PLBPPCS1ABUS, FCMAPUCR, LLDMA0RXREM, LLDMA1RXREM, LLDMA2RXREM, LLDMA3RXREM, PLBPPCMRDWDADDR, PLBPPCS0SIZE, PLBPPCS1SIZE, TIEC440ERPNRESET, TIEC440USERRESET, DBGC440SYSTEMSTATUS +, DCRPPCDSABUS, PLBPPCS0UABUS, PLBPPCS1UABUS, TIEC440PIR, TIEC440PVR); parameter CLOCK_DELAY = "FALSE"; parameter DCR_AUTOLOCK_ENABLE = "TRUE"; parameter PPCDM_ASYNCMODE = "FALSE"; @@ -31692,7 +32292,36 @@ module PPC440 (...); endmodule (* keep *) -module PS7 (...); +module PS7(DMA0DAVALID, DMA0DRREADY, DMA0RSTN, DMA1DAVALID, DMA1DRREADY, DMA1RSTN, DMA2DAVALID, DMA2DRREADY, DMA2RSTN, DMA3DAVALID, DMA3DRREADY, DMA3RSTN, EMIOCAN0PHYTX, EMIOCAN1PHYTX, EMIOENET0GMIITXEN, EMIOENET0GMIITXER, EMIOENET0MDIOMDC, EMIOENET0MDIOO, EMIOENET0MDIOTN, EMIOENET0PTPDELAYREQRX, EMIOENET0PTPDELAYREQTX +, EMIOENET0PTPPDELAYREQRX, EMIOENET0PTPPDELAYREQTX, EMIOENET0PTPPDELAYRESPRX, EMIOENET0PTPPDELAYRESPTX, EMIOENET0PTPSYNCFRAMERX, EMIOENET0PTPSYNCFRAMETX, EMIOENET0SOFRX, EMIOENET0SOFTX, EMIOENET1GMIITXEN, EMIOENET1GMIITXER, EMIOENET1MDIOMDC, EMIOENET1MDIOO, EMIOENET1MDIOTN, EMIOENET1PTPDELAYREQRX, EMIOENET1PTPDELAYREQTX, EMIOENET1PTPPDELAYREQRX, EMIOENET1PTPPDELAYREQTX, EMIOENET1PTPPDELAYRESPRX, EMIOENET1PTPPDELAYRESPTX, EMIOENET1PTPSYNCFRAMERX, EMIOENET1PTPSYNCFRAMETX +, EMIOENET1SOFRX, EMIOENET1SOFTX, EMIOI2C0SCLO, EMIOI2C0SCLTN, EMIOI2C0SDAO, EMIOI2C0SDATN, EMIOI2C1SCLO, EMIOI2C1SCLTN, EMIOI2C1SDAO, EMIOI2C1SDATN, EMIOPJTAGTDO, EMIOPJTAGTDTN, EMIOSDIO0BUSPOW, EMIOSDIO0CLK, EMIOSDIO0CMDO, EMIOSDIO0CMDTN, EMIOSDIO0LED, EMIOSDIO1BUSPOW, EMIOSDIO1CLK, EMIOSDIO1CMDO, EMIOSDIO1CMDTN +, EMIOSDIO1LED, EMIOSPI0MO, EMIOSPI0MOTN, EMIOSPI0SCLKO, EMIOSPI0SCLKTN, EMIOSPI0SO, EMIOSPI0SSNTN, EMIOSPI0STN, EMIOSPI1MO, EMIOSPI1MOTN, EMIOSPI1SCLKO, EMIOSPI1SCLKTN, EMIOSPI1SO, EMIOSPI1SSNTN, EMIOSPI1STN, EMIOTRACECTL, EMIOUART0DTRN, EMIOUART0RTSN, EMIOUART0TX, EMIOUART1DTRN, EMIOUART1RTSN +, EMIOUART1TX, EMIOUSB0VBUSPWRSELECT, EMIOUSB1VBUSPWRSELECT, EMIOWDTRSTO, EVENTEVENTO, MAXIGP0ARESETN, MAXIGP0ARVALID, MAXIGP0AWVALID, MAXIGP0BREADY, MAXIGP0RREADY, MAXIGP0WLAST, MAXIGP0WVALID, MAXIGP1ARESETN, MAXIGP1ARVALID, MAXIGP1AWVALID, MAXIGP1BREADY, MAXIGP1RREADY, MAXIGP1WLAST, MAXIGP1WVALID, SAXIACPARESETN, SAXIACPARREADY +, SAXIACPAWREADY, SAXIACPBVALID, SAXIACPRLAST, SAXIACPRVALID, SAXIACPWREADY, SAXIGP0ARESETN, SAXIGP0ARREADY, SAXIGP0AWREADY, SAXIGP0BVALID, SAXIGP0RLAST, SAXIGP0RVALID, SAXIGP0WREADY, SAXIGP1ARESETN, SAXIGP1ARREADY, SAXIGP1AWREADY, SAXIGP1BVALID, SAXIGP1RLAST, SAXIGP1RVALID, SAXIGP1WREADY, SAXIHP0ARESETN, SAXIHP0ARREADY +, SAXIHP0AWREADY, SAXIHP0BVALID, SAXIHP0RLAST, SAXIHP0RVALID, SAXIHP0WREADY, SAXIHP1ARESETN, SAXIHP1ARREADY, SAXIHP1AWREADY, SAXIHP1BVALID, SAXIHP1RLAST, SAXIHP1RVALID, SAXIHP1WREADY, SAXIHP2ARESETN, SAXIHP2ARREADY, SAXIHP2AWREADY, SAXIHP2BVALID, SAXIHP2RLAST, SAXIHP2RVALID, SAXIHP2WREADY, SAXIHP3ARESETN, SAXIHP3ARREADY +, SAXIHP3AWREADY, SAXIHP3BVALID, SAXIHP3RLAST, SAXIHP3RVALID, SAXIHP3WREADY, MAXIGP0ARID, MAXIGP0AWID, MAXIGP0WID, MAXIGP1ARID, MAXIGP1AWID, MAXIGP1WID, DMA0DATYPE, DMA1DATYPE, DMA2DATYPE, DMA3DATYPE, EMIOUSB0PORTINDCTL, EMIOUSB1PORTINDCTL, EVENTSTANDBYWFE, EVENTSTANDBYWFI, MAXIGP0ARBURST, MAXIGP0ARLOCK +, MAXIGP0ARSIZE, MAXIGP0AWBURST, MAXIGP0AWLOCK, MAXIGP0AWSIZE, MAXIGP1ARBURST, MAXIGP1ARLOCK, MAXIGP1ARSIZE, MAXIGP1AWBURST, MAXIGP1AWLOCK, MAXIGP1AWSIZE, SAXIACPBRESP, SAXIACPRRESP, SAXIGP0BRESP, SAXIGP0RRESP, SAXIGP1BRESP, SAXIGP1RRESP, SAXIHP0BRESP, SAXIHP0RRESP, SAXIHP1BRESP, SAXIHP1RRESP, SAXIHP2BRESP +, SAXIHP2RRESP, SAXIHP3BRESP, SAXIHP3RRESP, IRQP2F, EMIOSDIO0BUSVOLT, EMIOSDIO1BUSVOLT, EMIOSPI0SSON, EMIOSPI1SSON, EMIOTTC0WAVEO, EMIOTTC1WAVEO, MAXIGP0ARPROT, MAXIGP0AWPROT, MAXIGP1ARPROT, MAXIGP1AWPROT, SAXIACPBID, SAXIACPRID, SAXIHP0RACOUNT, SAXIHP1RACOUNT, SAXIHP2RACOUNT, SAXIHP3RACOUNT, EMIOTRACEDATA +, FTMTP2FDEBUG, MAXIGP0ARADDR, MAXIGP0AWADDR, MAXIGP0WDATA, MAXIGP1ARADDR, MAXIGP1AWADDR, MAXIGP1WDATA, SAXIGP0RDATA, SAXIGP1RDATA, EMIOSDIO0DATAO, EMIOSDIO0DATATN, EMIOSDIO1DATAO, EMIOSDIO1DATATN, FCLKCLK, FCLKRESETN, FTMTF2PTRIGACK, FTMTP2FTRIG, MAXIGP0ARCACHE, MAXIGP0ARLEN, MAXIGP0ARQOS, MAXIGP0AWCACHE +, MAXIGP0AWLEN, MAXIGP0AWQOS, MAXIGP0WSTRB, MAXIGP1ARCACHE, MAXIGP1ARLEN, MAXIGP1ARQOS, MAXIGP1AWCACHE, MAXIGP1AWLEN, MAXIGP1AWQOS, MAXIGP1WSTRB, SAXIGP0BID, SAXIGP0RID, SAXIGP1BID, SAXIGP1RID, SAXIHP0BID, SAXIHP0RID, SAXIHP0WACOUNT, SAXIHP1BID, SAXIHP1RID, SAXIHP1WACOUNT, SAXIHP2BID +, SAXIHP2RID, SAXIHP2WACOUNT, SAXIHP3BID, SAXIHP3RID, SAXIHP3WACOUNT, EMIOGPIOO, EMIOGPIOTN, SAXIACPRDATA, SAXIHP0RDATA, SAXIHP1RDATA, SAXIHP2RDATA, SAXIHP3RDATA, EMIOENET0GMIITXD, EMIOENET1GMIITXD, SAXIHP0RCOUNT, SAXIHP0WCOUNT, SAXIHP1RCOUNT, SAXIHP1WCOUNT, SAXIHP2RCOUNT, SAXIHP2WCOUNT, SAXIHP3RCOUNT +, SAXIHP3WCOUNT, DDRCASB, DDRCKE, DDRCKN, DDRCKP, DDRCSB, DDRDRSTB, DDRODT, DDRRASB, DDRVRN, DDRVRP, DDRWEB, PSCLK, PSPORB, PSSRSTB, DDRA, DDRBA, DDRDQ, DDRDM, DDRDQSN, DDRDQSP +, MIO, DMA0ACLK, DMA0DAREADY, DMA0DRLAST, DMA0DRVALID, DMA1ACLK, DMA1DAREADY, DMA1DRLAST, DMA1DRVALID, DMA2ACLK, DMA2DAREADY, DMA2DRLAST, DMA2DRVALID, DMA3ACLK, DMA3DAREADY, DMA3DRLAST, DMA3DRVALID, EMIOCAN0PHYRX, EMIOCAN1PHYRX, EMIOENET0EXTINTIN, EMIOENET0GMIICOL +, EMIOENET0GMIICRS, EMIOENET0GMIIRXCLK, EMIOENET0GMIIRXDV, EMIOENET0GMIIRXER, EMIOENET0GMIITXCLK, EMIOENET0MDIOI, EMIOENET1EXTINTIN, EMIOENET1GMIICOL, EMIOENET1GMIICRS, EMIOENET1GMIIRXCLK, EMIOENET1GMIIRXDV, EMIOENET1GMIIRXER, EMIOENET1GMIITXCLK, EMIOENET1MDIOI, EMIOI2C0SCLI, EMIOI2C0SDAI, EMIOI2C1SCLI, EMIOI2C1SDAI, EMIOPJTAGTCK, EMIOPJTAGTDI, EMIOPJTAGTMS +, EMIOSDIO0CDN, EMIOSDIO0CLKFB, EMIOSDIO0CMDI, EMIOSDIO0WP, EMIOSDIO1CDN, EMIOSDIO1CLKFB, EMIOSDIO1CMDI, EMIOSDIO1WP, EMIOSPI0MI, EMIOSPI0SCLKI, EMIOSPI0SI, EMIOSPI0SSIN, EMIOSPI1MI, EMIOSPI1SCLKI, EMIOSPI1SI, EMIOSPI1SSIN, EMIOSRAMINTIN, EMIOTRACECLK, EMIOUART0CTSN, EMIOUART0DCDN, EMIOUART0DSRN +, EMIOUART0RIN, EMIOUART0RX, EMIOUART1CTSN, EMIOUART1DCDN, EMIOUART1DSRN, EMIOUART1RIN, EMIOUART1RX, EMIOUSB0VBUSPWRFAULT, EMIOUSB1VBUSPWRFAULT, EMIOWDTCLKI, EVENTEVENTI, FPGAIDLEN, FTMDTRACEINCLOCK, FTMDTRACEINVALID, MAXIGP0ACLK, MAXIGP0ARREADY, MAXIGP0AWREADY, MAXIGP0BVALID, MAXIGP0RLAST, MAXIGP0RVALID, MAXIGP0WREADY +, MAXIGP1ACLK, MAXIGP1ARREADY, MAXIGP1AWREADY, MAXIGP1BVALID, MAXIGP1RLAST, MAXIGP1RVALID, MAXIGP1WREADY, SAXIACPACLK, SAXIACPARVALID, SAXIACPAWVALID, SAXIACPBREADY, SAXIACPRREADY, SAXIACPWLAST, SAXIACPWVALID, SAXIGP0ACLK, SAXIGP0ARVALID, SAXIGP0AWVALID, SAXIGP0BREADY, SAXIGP0RREADY, SAXIGP0WLAST, SAXIGP0WVALID +, SAXIGP1ACLK, SAXIGP1ARVALID, SAXIGP1AWVALID, SAXIGP1BREADY, SAXIGP1RREADY, SAXIGP1WLAST, SAXIGP1WVALID, SAXIHP0ACLK, SAXIHP0ARVALID, SAXIHP0AWVALID, SAXIHP0BREADY, SAXIHP0RDISSUECAP1EN, SAXIHP0RREADY, SAXIHP0WLAST, SAXIHP0WRISSUECAP1EN, SAXIHP0WVALID, SAXIHP1ACLK, SAXIHP1ARVALID, SAXIHP1AWVALID, SAXIHP1BREADY, SAXIHP1RDISSUECAP1EN +, SAXIHP1RREADY, SAXIHP1WLAST, SAXIHP1WRISSUECAP1EN, SAXIHP1WVALID, SAXIHP2ACLK, SAXIHP2ARVALID, SAXIHP2AWVALID, SAXIHP2BREADY, SAXIHP2RDISSUECAP1EN, SAXIHP2RREADY, SAXIHP2WLAST, SAXIHP2WRISSUECAP1EN, SAXIHP2WVALID, SAXIHP3ACLK, SAXIHP3ARVALID, SAXIHP3AWVALID, SAXIHP3BREADY, SAXIHP3RDISSUECAP1EN, SAXIHP3RREADY, SAXIHP3WLAST, SAXIHP3WRISSUECAP1EN +, SAXIHP3WVALID, MAXIGP0BID, MAXIGP0RID, MAXIGP1BID, MAXIGP1RID, IRQF2P, DMA0DRTYPE, DMA1DRTYPE, DMA2DRTYPE, DMA3DRTYPE, MAXIGP0BRESP, MAXIGP0RRESP, MAXIGP1BRESP, MAXIGP1RRESP, SAXIACPARBURST, SAXIACPARLOCK, SAXIACPARSIZE, SAXIACPAWBURST, SAXIACPAWLOCK, SAXIACPAWSIZE, SAXIGP0ARBURST +, SAXIGP0ARLOCK, SAXIGP0ARSIZE, SAXIGP0AWBURST, SAXIGP0AWLOCK, SAXIGP0AWSIZE, SAXIGP1ARBURST, SAXIGP1ARLOCK, SAXIGP1ARSIZE, SAXIGP1AWBURST, SAXIGP1AWLOCK, SAXIGP1AWSIZE, SAXIHP0ARBURST, SAXIHP0ARLOCK, SAXIHP0ARSIZE, SAXIHP0AWBURST, SAXIHP0AWLOCK, SAXIHP0AWSIZE, SAXIHP1ARBURST, SAXIHP1ARLOCK, SAXIHP1ARSIZE, SAXIHP1AWBURST +, SAXIHP1AWLOCK, SAXIHP1AWSIZE, SAXIHP2ARBURST, SAXIHP2ARLOCK, SAXIHP2ARSIZE, SAXIHP2AWBURST, SAXIHP2AWLOCK, SAXIHP2AWSIZE, SAXIHP3ARBURST, SAXIHP3ARLOCK, SAXIHP3ARSIZE, SAXIHP3AWBURST, SAXIHP3AWLOCK, SAXIHP3AWSIZE, EMIOTTC0CLKI, EMIOTTC1CLKI, SAXIACPARID, SAXIACPARPROT, SAXIACPAWID, SAXIACPAWPROT, SAXIACPWID +, SAXIGP0ARPROT, SAXIGP0AWPROT, SAXIGP1ARPROT, SAXIGP1AWPROT, SAXIHP0ARPROT, SAXIHP0AWPROT, SAXIHP1ARPROT, SAXIHP1AWPROT, SAXIHP2ARPROT, SAXIHP2AWPROT, SAXIHP3ARPROT, SAXIHP3AWPROT, FTMDTRACEINDATA, FTMTF2PDEBUG, MAXIGP0RDATA, MAXIGP1RDATA, SAXIACPARADDR, SAXIACPAWADDR, SAXIGP0ARADDR, SAXIGP0AWADDR, SAXIGP0WDATA +, SAXIGP1ARADDR, SAXIGP1AWADDR, SAXIGP1WDATA, SAXIHP0ARADDR, SAXIHP0AWADDR, SAXIHP1ARADDR, SAXIHP1AWADDR, SAXIHP2ARADDR, SAXIHP2AWADDR, SAXIHP3ARADDR, SAXIHP3AWADDR, DDRARB, EMIOSDIO0DATAI, EMIOSDIO1DATAI, FCLKCLKTRIGN, FTMDTRACEINATID, FTMTF2PTRIG, FTMTP2FTRIGACK, SAXIACPARCACHE, SAXIACPARLEN, SAXIACPARQOS +, SAXIACPAWCACHE, SAXIACPAWLEN, SAXIACPAWQOS, SAXIGP0ARCACHE, SAXIGP0ARLEN, SAXIGP0ARQOS, SAXIGP0AWCACHE, SAXIGP0AWLEN, SAXIGP0AWQOS, SAXIGP0WSTRB, SAXIGP1ARCACHE, SAXIGP1ARLEN, SAXIGP1ARQOS, SAXIGP1AWCACHE, SAXIGP1AWLEN, SAXIGP1AWQOS, SAXIGP1WSTRB, SAXIHP0ARCACHE, SAXIHP0ARLEN, SAXIHP0ARQOS, SAXIHP0AWCACHE +, SAXIHP0AWLEN, SAXIHP0AWQOS, SAXIHP1ARCACHE, SAXIHP1ARLEN, SAXIHP1ARQOS, SAXIHP1AWCACHE, SAXIHP1AWLEN, SAXIHP1AWQOS, SAXIHP2ARCACHE, SAXIHP2ARLEN, SAXIHP2ARQOS, SAXIHP2AWCACHE, SAXIHP2AWLEN, SAXIHP2AWQOS, SAXIHP3ARCACHE, SAXIHP3ARLEN, SAXIHP3ARQOS, SAXIHP3AWCACHE, SAXIHP3AWLEN, SAXIHP3AWQOS, SAXIACPARUSER +, SAXIACPAWUSER, SAXIGP0ARID, SAXIGP0AWID, SAXIGP0WID, SAXIGP1ARID, SAXIGP1AWID, SAXIGP1WID, SAXIHP0ARID, SAXIHP0AWID, SAXIHP0WID, SAXIHP1ARID, SAXIHP1AWID, SAXIHP1WID, SAXIHP2ARID, SAXIHP2AWID, SAXIHP2WID, SAXIHP3ARID, SAXIHP3AWID, SAXIHP3WID, EMIOGPIOI, SAXIACPWDATA +, SAXIHP0WDATA, SAXIHP1WDATA, SAXIHP2WDATA, SAXIHP3WDATA, EMIOENET0GMIIRXD, EMIOENET1GMIIRXD, SAXIACPWSTRB, SAXIHP0WSTRB, SAXIHP1WSTRB, SAXIHP2WSTRB, SAXIHP3WSTRB); output DMA0DAVALID; output DMA0DRREADY; output DMA0RSTN; @@ -32316,7 +32945,55 @@ module PS7 (...); endmodule (* keep *) -module PS8 (...); +module PS8(ADMA2PLCACK, ADMA2PLTVLD, DPAUDIOREFCLK, DPAUXDATAOEN, DPAUXDATAOUT, DPLIVEVIDEODEOUT, DPMAXISMIXEDAUDIOTDATA, DPMAXISMIXEDAUDIOTID, DPMAXISMIXEDAUDIOTVALID, DPSAXISAUDIOTREADY, DPVIDEOOUTHSYNC, DPVIDEOOUTPIXEL1, DPVIDEOOUTVSYNC, DPVIDEOREFCLK, EMIOCAN0PHYTX, EMIOCAN1PHYTX, EMIOENET0DMABUSWIDTH, EMIOENET0DMATXENDTOG, EMIOENET0GEMTSUTIMERCNT, EMIOENET0GMIITXD, EMIOENET0GMIITXEN +, EMIOENET0GMIITXER, EMIOENET0MDIOMDC, EMIOENET0MDIOO, EMIOENET0MDIOTN, EMIOENET0RXWDATA, EMIOENET0RXWEOP, EMIOENET0RXWERR, EMIOENET0RXWFLUSH, EMIOENET0RXWSOP, EMIOENET0RXWSTATUS, EMIOENET0RXWWR, EMIOENET0SPEEDMODE, EMIOENET0TXRRD, EMIOENET0TXRSTATUS, EMIOENET1DMABUSWIDTH, EMIOENET1DMATXENDTOG, EMIOENET1GMIITXD, EMIOENET1GMIITXEN, EMIOENET1GMIITXER, EMIOENET1MDIOMDC, EMIOENET1MDIOO +, EMIOENET1MDIOTN, EMIOENET1RXWDATA, EMIOENET1RXWEOP, EMIOENET1RXWERR, EMIOENET1RXWFLUSH, EMIOENET1RXWSOP, EMIOENET1RXWSTATUS, EMIOENET1RXWWR, EMIOENET1SPEEDMODE, EMIOENET1TXRRD, EMIOENET1TXRSTATUS, EMIOENET2DMABUSWIDTH, EMIOENET2DMATXENDTOG, EMIOENET2GMIITXD, EMIOENET2GMIITXEN, EMIOENET2GMIITXER, EMIOENET2MDIOMDC, EMIOENET2MDIOO, EMIOENET2MDIOTN, EMIOENET2RXWDATA, EMIOENET2RXWEOP +, EMIOENET2RXWERR, EMIOENET2RXWFLUSH, EMIOENET2RXWSOP, EMIOENET2RXWSTATUS, EMIOENET2RXWWR, EMIOENET2SPEEDMODE, EMIOENET2TXRRD, EMIOENET2TXRSTATUS, EMIOENET3DMABUSWIDTH, EMIOENET3DMATXENDTOG, EMIOENET3GMIITXD, EMIOENET3GMIITXEN, EMIOENET3GMIITXER, EMIOENET3MDIOMDC, EMIOENET3MDIOO, EMIOENET3MDIOTN, EMIOENET3RXWDATA, EMIOENET3RXWEOP, EMIOENET3RXWERR, EMIOENET3RXWFLUSH, EMIOENET3RXWSOP +, EMIOENET3RXWSTATUS, EMIOENET3RXWWR, EMIOENET3SPEEDMODE, EMIOENET3TXRRD, EMIOENET3TXRSTATUS, EMIOGEM0DELAYREQRX, EMIOGEM0DELAYREQTX, EMIOGEM0PDELAYREQRX, EMIOGEM0PDELAYREQTX, EMIOGEM0PDELAYRESPRX, EMIOGEM0PDELAYRESPTX, EMIOGEM0RXSOF, EMIOGEM0SYNCFRAMERX, EMIOGEM0SYNCFRAMETX, EMIOGEM0TSUTIMERCMPVAL, EMIOGEM0TXRFIXEDLAT, EMIOGEM0TXSOF, EMIOGEM1DELAYREQRX, EMIOGEM1DELAYREQTX, EMIOGEM1PDELAYREQRX, EMIOGEM1PDELAYREQTX +, EMIOGEM1PDELAYRESPRX, EMIOGEM1PDELAYRESPTX, EMIOGEM1RXSOF, EMIOGEM1SYNCFRAMERX, EMIOGEM1SYNCFRAMETX, EMIOGEM1TSUTIMERCMPVAL, EMIOGEM1TXRFIXEDLAT, EMIOGEM1TXSOF, EMIOGEM2DELAYREQRX, EMIOGEM2DELAYREQTX, EMIOGEM2PDELAYREQRX, EMIOGEM2PDELAYREQTX, EMIOGEM2PDELAYRESPRX, EMIOGEM2PDELAYRESPTX, EMIOGEM2RXSOF, EMIOGEM2SYNCFRAMERX, EMIOGEM2SYNCFRAMETX, EMIOGEM2TSUTIMERCMPVAL, EMIOGEM2TXRFIXEDLAT, EMIOGEM2TXSOF, EMIOGEM3DELAYREQRX +, EMIOGEM3DELAYREQTX, EMIOGEM3PDELAYREQRX, EMIOGEM3PDELAYREQTX, EMIOGEM3PDELAYRESPRX, EMIOGEM3PDELAYRESPTX, EMIOGEM3RXSOF, EMIOGEM3SYNCFRAMERX, EMIOGEM3SYNCFRAMETX, EMIOGEM3TSUTIMERCMPVAL, EMIOGEM3TXRFIXEDLAT, EMIOGEM3TXSOF, EMIOGPIOO, EMIOGPIOTN, EMIOI2C0SCLO, EMIOI2C0SCLTN, EMIOI2C0SDAO, EMIOI2C0SDATN, EMIOI2C1SCLO, EMIOI2C1SCLTN, EMIOI2C1SDAO, EMIOI2C1SDATN +, EMIOSDIO0BUSPOWER, EMIOSDIO0BUSVOLT, EMIOSDIO0CLKOUT, EMIOSDIO0CMDENA, EMIOSDIO0CMDOUT, EMIOSDIO0DATAENA, EMIOSDIO0DATAOUT, EMIOSDIO0LEDCONTROL, EMIOSDIO1BUSPOWER, EMIOSDIO1BUSVOLT, EMIOSDIO1CLKOUT, EMIOSDIO1CMDENA, EMIOSDIO1CMDOUT, EMIOSDIO1DATAENA, EMIOSDIO1DATAOUT, EMIOSDIO1LEDCONTROL, EMIOSPI0MO, EMIOSPI0MOTN, EMIOSPI0SCLKO, EMIOSPI0SCLKTN, EMIOSPI0SO +, EMIOSPI0SSNTN, EMIOSPI0SSON, EMIOSPI0STN, EMIOSPI1MO, EMIOSPI1MOTN, EMIOSPI1SCLKO, EMIOSPI1SCLKTN, EMIOSPI1SO, EMIOSPI1SSNTN, EMIOSPI1SSON, EMIOSPI1STN, EMIOTTC0WAVEO, EMIOTTC1WAVEO, EMIOTTC2WAVEO, EMIOTTC3WAVEO, EMIOU2DSPORTVBUSCTRLUSB30, EMIOU2DSPORTVBUSCTRLUSB31, EMIOU3DSPORTVBUSCTRLUSB30, EMIOU3DSPORTVBUSCTRLUSB31, EMIOUART0DTRN, EMIOUART0RTSN +, EMIOUART0TX, EMIOUART1DTRN, EMIOUART1RTSN, EMIOUART1TX, EMIOWDT0RSTO, EMIOWDT1RSTO, FMIOGEM0FIFORXCLKTOPLBUFG, FMIOGEM0FIFOTXCLKTOPLBUFG, FMIOGEM1FIFORXCLKTOPLBUFG, FMIOGEM1FIFOTXCLKTOPLBUFG, FMIOGEM2FIFORXCLKTOPLBUFG, FMIOGEM2FIFOTXCLKTOPLBUFG, FMIOGEM3FIFORXCLKTOPLBUFG, FMIOGEM3FIFOTXCLKTOPLBUFG, FMIOGEMTSUCLKTOPLBUFG, FTMGPO, GDMA2PLCACK, GDMA2PLTVLD, MAXIGP0ARADDR, MAXIGP0ARBURST, MAXIGP0ARCACHE +, MAXIGP0ARID, MAXIGP0ARLEN, MAXIGP0ARLOCK, MAXIGP0ARPROT, MAXIGP0ARQOS, MAXIGP0ARSIZE, MAXIGP0ARUSER, MAXIGP0ARVALID, MAXIGP0AWADDR, MAXIGP0AWBURST, MAXIGP0AWCACHE, MAXIGP0AWID, MAXIGP0AWLEN, MAXIGP0AWLOCK, MAXIGP0AWPROT, MAXIGP0AWQOS, MAXIGP0AWSIZE, MAXIGP0AWUSER, MAXIGP0AWVALID, MAXIGP0BREADY, MAXIGP0RREADY +, MAXIGP0WDATA, MAXIGP0WLAST, MAXIGP0WSTRB, MAXIGP0WVALID, MAXIGP1ARADDR, MAXIGP1ARBURST, MAXIGP1ARCACHE, MAXIGP1ARID, MAXIGP1ARLEN, MAXIGP1ARLOCK, MAXIGP1ARPROT, MAXIGP1ARQOS, MAXIGP1ARSIZE, MAXIGP1ARUSER, MAXIGP1ARVALID, MAXIGP1AWADDR, MAXIGP1AWBURST, MAXIGP1AWCACHE, MAXIGP1AWID, MAXIGP1AWLEN, MAXIGP1AWLOCK +, MAXIGP1AWPROT, MAXIGP1AWQOS, MAXIGP1AWSIZE, MAXIGP1AWUSER, MAXIGP1AWVALID, MAXIGP1BREADY, MAXIGP1RREADY, MAXIGP1WDATA, MAXIGP1WLAST, MAXIGP1WSTRB, MAXIGP1WVALID, MAXIGP2ARADDR, MAXIGP2ARBURST, MAXIGP2ARCACHE, MAXIGP2ARID, MAXIGP2ARLEN, MAXIGP2ARLOCK, MAXIGP2ARPROT, MAXIGP2ARQOS, MAXIGP2ARSIZE, MAXIGP2ARUSER +, MAXIGP2ARVALID, MAXIGP2AWADDR, MAXIGP2AWBURST, MAXIGP2AWCACHE, MAXIGP2AWID, MAXIGP2AWLEN, MAXIGP2AWLOCK, MAXIGP2AWPROT, MAXIGP2AWQOS, MAXIGP2AWSIZE, MAXIGP2AWUSER, MAXIGP2AWVALID, MAXIGP2BREADY, MAXIGP2RREADY, MAXIGP2WDATA, MAXIGP2WLAST, MAXIGP2WSTRB, MAXIGP2WVALID, OSCRTCCLK, PLCLK, PMUAIBAFIFMFPDREQ +, PMUAIBAFIFMLPDREQ, PMUERRORTOPL, PMUPLGPO, PSPLEVENTO, PSPLIRQFPD, PSPLIRQLPD, PSPLSTANDBYWFE, PSPLSTANDBYWFI, PSPLTRACECTL, PSPLTRACEDATA, PSPLTRIGACK, PSPLTRIGGER, PSS_ALTO_CORE_PAD_MGTTXN0OUT, PSS_ALTO_CORE_PAD_MGTTXN1OUT, PSS_ALTO_CORE_PAD_MGTTXN2OUT, PSS_ALTO_CORE_PAD_MGTTXN3OUT, PSS_ALTO_CORE_PAD_MGTTXP0OUT, PSS_ALTO_CORE_PAD_MGTTXP1OUT, PSS_ALTO_CORE_PAD_MGTTXP2OUT, PSS_ALTO_CORE_PAD_MGTTXP3OUT, PSS_ALTO_CORE_PAD_PADO +, RPUEVENTO0, RPUEVENTO1, SACEFPDACADDR, SACEFPDACPROT, SACEFPDACSNOOP, SACEFPDACVALID, SACEFPDARREADY, SACEFPDAWREADY, SACEFPDBID, SACEFPDBRESP, SACEFPDBUSER, SACEFPDBVALID, SACEFPDCDREADY, SACEFPDCRREADY, SACEFPDRDATA, SACEFPDRID, SACEFPDRLAST, SACEFPDRRESP, SACEFPDRUSER, SACEFPDRVALID, SACEFPDWREADY +, SAXIACPARREADY, SAXIACPAWREADY, SAXIACPBID, SAXIACPBRESP, SAXIACPBVALID, SAXIACPRDATA, SAXIACPRID, SAXIACPRLAST, SAXIACPRRESP, SAXIACPRVALID, SAXIACPWREADY, SAXIGP0ARREADY, SAXIGP0AWREADY, SAXIGP0BID, SAXIGP0BRESP, SAXIGP0BVALID, SAXIGP0RACOUNT, SAXIGP0RCOUNT, SAXIGP0RDATA, SAXIGP0RID, SAXIGP0RLAST +, SAXIGP0RRESP, SAXIGP0RVALID, SAXIGP0WACOUNT, SAXIGP0WCOUNT, SAXIGP0WREADY, SAXIGP1ARREADY, SAXIGP1AWREADY, SAXIGP1BID, SAXIGP1BRESP, SAXIGP1BVALID, SAXIGP1RACOUNT, SAXIGP1RCOUNT, SAXIGP1RDATA, SAXIGP1RID, SAXIGP1RLAST, SAXIGP1RRESP, SAXIGP1RVALID, SAXIGP1WACOUNT, SAXIGP1WCOUNT, SAXIGP1WREADY, SAXIGP2ARREADY +, SAXIGP2AWREADY, SAXIGP2BID, SAXIGP2BRESP, SAXIGP2BVALID, SAXIGP2RACOUNT, SAXIGP2RCOUNT, SAXIGP2RDATA, SAXIGP2RID, SAXIGP2RLAST, SAXIGP2RRESP, SAXIGP2RVALID, SAXIGP2WACOUNT, SAXIGP2WCOUNT, SAXIGP2WREADY, SAXIGP3ARREADY, SAXIGP3AWREADY, SAXIGP3BID, SAXIGP3BRESP, SAXIGP3BVALID, SAXIGP3RACOUNT, SAXIGP3RCOUNT +, SAXIGP3RDATA, SAXIGP3RID, SAXIGP3RLAST, SAXIGP3RRESP, SAXIGP3RVALID, SAXIGP3WACOUNT, SAXIGP3WCOUNT, SAXIGP3WREADY, SAXIGP4ARREADY, SAXIGP4AWREADY, SAXIGP4BID, SAXIGP4BRESP, SAXIGP4BVALID, SAXIGP4RACOUNT, SAXIGP4RCOUNT, SAXIGP4RDATA, SAXIGP4RID, SAXIGP4RLAST, SAXIGP4RRESP, SAXIGP4RVALID, SAXIGP4WACOUNT +, SAXIGP4WCOUNT, SAXIGP4WREADY, SAXIGP5ARREADY, SAXIGP5AWREADY, SAXIGP5BID, SAXIGP5BRESP, SAXIGP5BVALID, SAXIGP5RACOUNT, SAXIGP5RCOUNT, SAXIGP5RDATA, SAXIGP5RID, SAXIGP5RLAST, SAXIGP5RRESP, SAXIGP5RVALID, SAXIGP5WACOUNT, SAXIGP5WCOUNT, SAXIGP5WREADY, SAXIGP6ARREADY, SAXIGP6AWREADY, SAXIGP6BID, SAXIGP6BRESP +, SAXIGP6BVALID, SAXIGP6RACOUNT, SAXIGP6RCOUNT, SAXIGP6RDATA, SAXIGP6RID, SAXIGP6RLAST, SAXIGP6RRESP, SAXIGP6RVALID, SAXIGP6WACOUNT, SAXIGP6WCOUNT, SAXIGP6WREADY, PSS_ALTO_CORE_PAD_BOOTMODE, PSS_ALTO_CORE_PAD_CLK, PSS_ALTO_CORE_PAD_DONEB, PSS_ALTO_CORE_PAD_DRAMA, PSS_ALTO_CORE_PAD_DRAMACTN, PSS_ALTO_CORE_PAD_DRAMALERTN, PSS_ALTO_CORE_PAD_DRAMBA, PSS_ALTO_CORE_PAD_DRAMBG, PSS_ALTO_CORE_PAD_DRAMCK, PSS_ALTO_CORE_PAD_DRAMCKE +, PSS_ALTO_CORE_PAD_DRAMCKN, PSS_ALTO_CORE_PAD_DRAMCSN, PSS_ALTO_CORE_PAD_DRAMDM, PSS_ALTO_CORE_PAD_DRAMDQ, PSS_ALTO_CORE_PAD_DRAMDQS, PSS_ALTO_CORE_PAD_DRAMDQSN, PSS_ALTO_CORE_PAD_DRAMODT, PSS_ALTO_CORE_PAD_DRAMPARITY, PSS_ALTO_CORE_PAD_DRAMRAMRSTN, PSS_ALTO_CORE_PAD_ERROROUT, PSS_ALTO_CORE_PAD_ERRORSTATUS, PSS_ALTO_CORE_PAD_INITB, PSS_ALTO_CORE_PAD_JTAGTCK, PSS_ALTO_CORE_PAD_JTAGTDI, PSS_ALTO_CORE_PAD_JTAGTDO, PSS_ALTO_CORE_PAD_JTAGTMS, PSS_ALTO_CORE_PAD_MIO, PSS_ALTO_CORE_PAD_PORB, PSS_ALTO_CORE_PAD_PROGB, PSS_ALTO_CORE_PAD_RCALIBINOUT, PSS_ALTO_CORE_PAD_SRSTB +, PSS_ALTO_CORE_PAD_ZQ, ADMAFCICLK, AIBPMUAFIFMFPDACK, AIBPMUAFIFMLPDACK, DDRCEXTREFRESHRANK0REQ, DDRCEXTREFRESHRANK1REQ, DDRCREFRESHPLCLK, DPAUXDATAIN, DPEXTERNALCUSTOMEVENT1, DPEXTERNALCUSTOMEVENT2, DPEXTERNALVSYNCEVENT, DPHOTPLUGDETECT, DPLIVEGFXALPHAIN, DPLIVEGFXPIXEL1IN, DPLIVEVIDEOINDE, DPLIVEVIDEOINHSYNC, DPLIVEVIDEOINPIXEL1, DPLIVEVIDEOINVSYNC, DPMAXISMIXEDAUDIOTREADY, DPSAXISAUDIOCLK, DPSAXISAUDIOTDATA +, DPSAXISAUDIOTID, DPSAXISAUDIOTVALID, DPVIDEOINCLK, EMIOCAN0PHYRX, EMIOCAN1PHYRX, EMIOENET0DMATXSTATUSTOG, EMIOENET0EXTINTIN, EMIOENET0GMIICOL, EMIOENET0GMIICRS, EMIOENET0GMIIRXCLK, EMIOENET0GMIIRXD, EMIOENET0GMIIRXDV, EMIOENET0GMIIRXER, EMIOENET0GMIITXCLK, EMIOENET0MDIOI, EMIOENET0RXWOVERFLOW, EMIOENET0TXRCONTROL, EMIOENET0TXRDATA, EMIOENET0TXRDATARDY, EMIOENET0TXREOP, EMIOENET0TXRERR +, EMIOENET0TXRFLUSHED, EMIOENET0TXRSOP, EMIOENET0TXRUNDERFLOW, EMIOENET0TXRVALID, EMIOENET1DMATXSTATUSTOG, EMIOENET1EXTINTIN, EMIOENET1GMIICOL, EMIOENET1GMIICRS, EMIOENET1GMIIRXCLK, EMIOENET1GMIIRXD, EMIOENET1GMIIRXDV, EMIOENET1GMIIRXER, EMIOENET1GMIITXCLK, EMIOENET1MDIOI, EMIOENET1RXWOVERFLOW, EMIOENET1TXRCONTROL, EMIOENET1TXRDATA, EMIOENET1TXRDATARDY, EMIOENET1TXREOP, EMIOENET1TXRERR, EMIOENET1TXRFLUSHED +, EMIOENET1TXRSOP, EMIOENET1TXRUNDERFLOW, EMIOENET1TXRVALID, EMIOENET2DMATXSTATUSTOG, EMIOENET2EXTINTIN, EMIOENET2GMIICOL, EMIOENET2GMIICRS, EMIOENET2GMIIRXCLK, EMIOENET2GMIIRXD, EMIOENET2GMIIRXDV, EMIOENET2GMIIRXER, EMIOENET2GMIITXCLK, EMIOENET2MDIOI, EMIOENET2RXWOVERFLOW, EMIOENET2TXRCONTROL, EMIOENET2TXRDATA, EMIOENET2TXRDATARDY, EMIOENET2TXREOP, EMIOENET2TXRERR, EMIOENET2TXRFLUSHED, EMIOENET2TXRSOP +, EMIOENET2TXRUNDERFLOW, EMIOENET2TXRVALID, EMIOENET3DMATXSTATUSTOG, EMIOENET3EXTINTIN, EMIOENET3GMIICOL, EMIOENET3GMIICRS, EMIOENET3GMIIRXCLK, EMIOENET3GMIIRXD, EMIOENET3GMIIRXDV, EMIOENET3GMIIRXER, EMIOENET3GMIITXCLK, EMIOENET3MDIOI, EMIOENET3RXWOVERFLOW, EMIOENET3TXRCONTROL, EMIOENET3TXRDATA, EMIOENET3TXRDATARDY, EMIOENET3TXREOP, EMIOENET3TXRERR, EMIOENET3TXRFLUSHED, EMIOENET3TXRSOP, EMIOENET3TXRUNDERFLOW +, EMIOENET3TXRVALID, EMIOENETTSUCLK, EMIOGEM0TSUINCCTRL, EMIOGEM1TSUINCCTRL, EMIOGEM2TSUINCCTRL, EMIOGEM3TSUINCCTRL, EMIOGPIOI, EMIOHUBPORTOVERCRNTUSB20, EMIOHUBPORTOVERCRNTUSB21, EMIOHUBPORTOVERCRNTUSB30, EMIOHUBPORTOVERCRNTUSB31, EMIOI2C0SCLI, EMIOI2C0SDAI, EMIOI2C1SCLI, EMIOI2C1SDAI, EMIOSDIO0CDN, EMIOSDIO0CMDIN, EMIOSDIO0DATAIN, EMIOSDIO0FBCLKIN, EMIOSDIO0WP, EMIOSDIO1CDN +, EMIOSDIO1CMDIN, EMIOSDIO1DATAIN, EMIOSDIO1FBCLKIN, EMIOSDIO1WP, EMIOSPI0MI, EMIOSPI0SCLKI, EMIOSPI0SI, EMIOSPI0SSIN, EMIOSPI1MI, EMIOSPI1SCLKI, EMIOSPI1SI, EMIOSPI1SSIN, EMIOTTC0CLKI, EMIOTTC1CLKI, EMIOTTC2CLKI, EMIOTTC3CLKI, EMIOUART0CTSN, EMIOUART0DCDN, EMIOUART0DSRN, EMIOUART0RIN, EMIOUART0RX +, EMIOUART1CTSN, EMIOUART1DCDN, EMIOUART1DSRN, EMIOUART1RIN, EMIOUART1RX, EMIOWDT0CLKI, EMIOWDT1CLKI, FMIOGEM0FIFORXCLKFROMPL, FMIOGEM0FIFOTXCLKFROMPL, FMIOGEM0SIGNALDETECT, FMIOGEM1FIFORXCLKFROMPL, FMIOGEM1FIFOTXCLKFROMPL, FMIOGEM1SIGNALDETECT, FMIOGEM2FIFORXCLKFROMPL, FMIOGEM2FIFOTXCLKFROMPL, FMIOGEM2SIGNALDETECT, FMIOGEM3FIFORXCLKFROMPL, FMIOGEM3FIFOTXCLKFROMPL, FMIOGEM3SIGNALDETECT, FMIOGEMTSUCLKFROMPL, FTMGPI +, GDMAFCICLK, MAXIGP0ACLK, MAXIGP0ARREADY, MAXIGP0AWREADY, MAXIGP0BID, MAXIGP0BRESP, MAXIGP0BVALID, MAXIGP0RDATA, MAXIGP0RID, MAXIGP0RLAST, MAXIGP0RRESP, MAXIGP0RVALID, MAXIGP0WREADY, MAXIGP1ACLK, MAXIGP1ARREADY, MAXIGP1AWREADY, MAXIGP1BID, MAXIGP1BRESP, MAXIGP1BVALID, MAXIGP1RDATA, MAXIGP1RID +, MAXIGP1RLAST, MAXIGP1RRESP, MAXIGP1RVALID, MAXIGP1WREADY, MAXIGP2ACLK, MAXIGP2ARREADY, MAXIGP2AWREADY, MAXIGP2BID, MAXIGP2BRESP, MAXIGP2BVALID, MAXIGP2RDATA, MAXIGP2RID, MAXIGP2RLAST, MAXIGP2RRESP, MAXIGP2RVALID, MAXIGP2WREADY, NFIQ0LPDRPU, NFIQ1LPDRPU, NIRQ0LPDRPU, NIRQ1LPDRPU, PL2ADMACVLD +, PL2ADMATACK, PL2GDMACVLD, PL2GDMATACK, PLACECLK, PLACPINACT, PLFPGASTOP, PLLAUXREFCLKFPD, PLLAUXREFCLKLPD, PLPMUGPI, PLPSAPUGICFIQ, PLPSAPUGICIRQ, PLPSEVENTI, PLPSIRQ0, PLPSIRQ1, PLPSTRACECLK, PLPSTRIGACK, PLPSTRIGGER, PMUERRORFROMPL, PSS_ALTO_CORE_PAD_MGTRXN0IN, PSS_ALTO_CORE_PAD_MGTRXN1IN, PSS_ALTO_CORE_PAD_MGTRXN2IN +, PSS_ALTO_CORE_PAD_MGTRXN3IN, PSS_ALTO_CORE_PAD_MGTRXP0IN, PSS_ALTO_CORE_PAD_MGTRXP1IN, PSS_ALTO_CORE_PAD_MGTRXP2IN, PSS_ALTO_CORE_PAD_MGTRXP3IN, PSS_ALTO_CORE_PAD_PADI, PSS_ALTO_CORE_PAD_REFN0IN, PSS_ALTO_CORE_PAD_REFN1IN, PSS_ALTO_CORE_PAD_REFN2IN, PSS_ALTO_CORE_PAD_REFN3IN, PSS_ALTO_CORE_PAD_REFP0IN, PSS_ALTO_CORE_PAD_REFP1IN, PSS_ALTO_CORE_PAD_REFP2IN, PSS_ALTO_CORE_PAD_REFP3IN, RPUEVENTI0, RPUEVENTI1, SACEFPDACREADY, SACEFPDARADDR, SACEFPDARBAR, SACEFPDARBURST, SACEFPDARCACHE +, SACEFPDARDOMAIN, SACEFPDARID, SACEFPDARLEN, SACEFPDARLOCK, SACEFPDARPROT, SACEFPDARQOS, SACEFPDARREGION, SACEFPDARSIZE, SACEFPDARSNOOP, SACEFPDARUSER, SACEFPDARVALID, SACEFPDAWADDR, SACEFPDAWBAR, SACEFPDAWBURST, SACEFPDAWCACHE, SACEFPDAWDOMAIN, SACEFPDAWID, SACEFPDAWLEN, SACEFPDAWLOCK, SACEFPDAWPROT, SACEFPDAWQOS +, SACEFPDAWREGION, SACEFPDAWSIZE, SACEFPDAWSNOOP, SACEFPDAWUSER, SACEFPDAWVALID, SACEFPDBREADY, SACEFPDCDDATA, SACEFPDCDLAST, SACEFPDCDVALID, SACEFPDCRRESP, SACEFPDCRVALID, SACEFPDRACK, SACEFPDRREADY, SACEFPDWACK, SACEFPDWDATA, SACEFPDWLAST, SACEFPDWSTRB, SACEFPDWUSER, SACEFPDWVALID, SAXIACPACLK, SAXIACPARADDR +, SAXIACPARBURST, SAXIACPARCACHE, SAXIACPARID, SAXIACPARLEN, SAXIACPARLOCK, SAXIACPARPROT, SAXIACPARQOS, SAXIACPARSIZE, SAXIACPARUSER, SAXIACPARVALID, SAXIACPAWADDR, SAXIACPAWBURST, SAXIACPAWCACHE, SAXIACPAWID, SAXIACPAWLEN, SAXIACPAWLOCK, SAXIACPAWPROT, SAXIACPAWQOS, SAXIACPAWSIZE, SAXIACPAWUSER, SAXIACPAWVALID +, SAXIACPBREADY, SAXIACPRREADY, SAXIACPWDATA, SAXIACPWLAST, SAXIACPWSTRB, SAXIACPWVALID, SAXIGP0ARADDR, SAXIGP0ARBURST, SAXIGP0ARCACHE, SAXIGP0ARID, SAXIGP0ARLEN, SAXIGP0ARLOCK, SAXIGP0ARPROT, SAXIGP0ARQOS, SAXIGP0ARSIZE, SAXIGP0ARUSER, SAXIGP0ARVALID, SAXIGP0AWADDR, SAXIGP0AWBURST, SAXIGP0AWCACHE, SAXIGP0AWID +, SAXIGP0AWLEN, SAXIGP0AWLOCK, SAXIGP0AWPROT, SAXIGP0AWQOS, SAXIGP0AWSIZE, SAXIGP0AWUSER, SAXIGP0AWVALID, SAXIGP0BREADY, SAXIGP0RCLK, SAXIGP0RREADY, SAXIGP0WCLK, SAXIGP0WDATA, SAXIGP0WLAST, SAXIGP0WSTRB, SAXIGP0WVALID, SAXIGP1ARADDR, SAXIGP1ARBURST, SAXIGP1ARCACHE, SAXIGP1ARID, SAXIGP1ARLEN, SAXIGP1ARLOCK +, SAXIGP1ARPROT, SAXIGP1ARQOS, SAXIGP1ARSIZE, SAXIGP1ARUSER, SAXIGP1ARVALID, SAXIGP1AWADDR, SAXIGP1AWBURST, SAXIGP1AWCACHE, SAXIGP1AWID, SAXIGP1AWLEN, SAXIGP1AWLOCK, SAXIGP1AWPROT, SAXIGP1AWQOS, SAXIGP1AWSIZE, SAXIGP1AWUSER, SAXIGP1AWVALID, SAXIGP1BREADY, SAXIGP1RCLK, SAXIGP1RREADY, SAXIGP1WCLK, SAXIGP1WDATA +, SAXIGP1WLAST, SAXIGP1WSTRB, SAXIGP1WVALID, SAXIGP2ARADDR, SAXIGP2ARBURST, SAXIGP2ARCACHE, SAXIGP2ARID, SAXIGP2ARLEN, SAXIGP2ARLOCK, SAXIGP2ARPROT, SAXIGP2ARQOS, SAXIGP2ARSIZE, SAXIGP2ARUSER, SAXIGP2ARVALID, SAXIGP2AWADDR, SAXIGP2AWBURST, SAXIGP2AWCACHE, SAXIGP2AWID, SAXIGP2AWLEN, SAXIGP2AWLOCK, SAXIGP2AWPROT +, SAXIGP2AWQOS, SAXIGP2AWSIZE, SAXIGP2AWUSER, SAXIGP2AWVALID, SAXIGP2BREADY, SAXIGP2RCLK, SAXIGP2RREADY, SAXIGP2WCLK, SAXIGP2WDATA, SAXIGP2WLAST, SAXIGP2WSTRB, SAXIGP2WVALID, SAXIGP3ARADDR, SAXIGP3ARBURST, SAXIGP3ARCACHE, SAXIGP3ARID, SAXIGP3ARLEN, SAXIGP3ARLOCK, SAXIGP3ARPROT, SAXIGP3ARQOS, SAXIGP3ARSIZE +, SAXIGP3ARUSER, SAXIGP3ARVALID, SAXIGP3AWADDR, SAXIGP3AWBURST, SAXIGP3AWCACHE, SAXIGP3AWID, SAXIGP3AWLEN, SAXIGP3AWLOCK, SAXIGP3AWPROT, SAXIGP3AWQOS, SAXIGP3AWSIZE, SAXIGP3AWUSER, SAXIGP3AWVALID, SAXIGP3BREADY, SAXIGP3RCLK, SAXIGP3RREADY, SAXIGP3WCLK, SAXIGP3WDATA, SAXIGP3WLAST, SAXIGP3WSTRB, SAXIGP3WVALID +, SAXIGP4ARADDR, SAXIGP4ARBURST, SAXIGP4ARCACHE, SAXIGP4ARID, SAXIGP4ARLEN, SAXIGP4ARLOCK, SAXIGP4ARPROT, SAXIGP4ARQOS, SAXIGP4ARSIZE, SAXIGP4ARUSER, SAXIGP4ARVALID, SAXIGP4AWADDR, SAXIGP4AWBURST, SAXIGP4AWCACHE, SAXIGP4AWID, SAXIGP4AWLEN, SAXIGP4AWLOCK, SAXIGP4AWPROT, SAXIGP4AWQOS, SAXIGP4AWSIZE, SAXIGP4AWUSER +, SAXIGP4AWVALID, SAXIGP4BREADY, SAXIGP4RCLK, SAXIGP4RREADY, SAXIGP4WCLK, SAXIGP4WDATA, SAXIGP4WLAST, SAXIGP4WSTRB, SAXIGP4WVALID, SAXIGP5ARADDR, SAXIGP5ARBURST, SAXIGP5ARCACHE, SAXIGP5ARID, SAXIGP5ARLEN, SAXIGP5ARLOCK, SAXIGP5ARPROT, SAXIGP5ARQOS, SAXIGP5ARSIZE, SAXIGP5ARUSER, SAXIGP5ARVALID, SAXIGP5AWADDR +, SAXIGP5AWBURST, SAXIGP5AWCACHE, SAXIGP5AWID, SAXIGP5AWLEN, SAXIGP5AWLOCK, SAXIGP5AWPROT, SAXIGP5AWQOS, SAXIGP5AWSIZE, SAXIGP5AWUSER, SAXIGP5AWVALID, SAXIGP5BREADY, SAXIGP5RCLK, SAXIGP5RREADY, SAXIGP5WCLK, SAXIGP5WDATA, SAXIGP5WLAST, SAXIGP5WSTRB, SAXIGP5WVALID, SAXIGP6ARADDR, SAXIGP6ARBURST, SAXIGP6ARCACHE +, SAXIGP6ARID, SAXIGP6ARLEN, SAXIGP6ARLOCK, SAXIGP6ARPROT, SAXIGP6ARQOS, SAXIGP6ARSIZE, SAXIGP6ARUSER, SAXIGP6ARVALID, SAXIGP6AWADDR, SAXIGP6AWBURST, SAXIGP6AWCACHE, SAXIGP6AWID, SAXIGP6AWLEN, SAXIGP6AWLOCK, SAXIGP6AWPROT, SAXIGP6AWQOS, SAXIGP6AWSIZE, SAXIGP6AWUSER, SAXIGP6AWVALID, SAXIGP6BREADY, SAXIGP6RCLK +, SAXIGP6RREADY, SAXIGP6WCLK, SAXIGP6WDATA, SAXIGP6WLAST, SAXIGP6WSTRB, SAXIGP6WVALID, STMEVENT); output [7:0] ADMA2PLCACK; output [7:0] ADMA2PLTVLD; output DPAUDIOREFCLK; @@ -33334,7 +34011,17 @@ module PS8 (...); input [59:0] STMEVENT; endmodule -module ILKN (...); +module ILKN(DRP_DO, DRP_RDY, RX_BYPASS_DATAOUT00, RX_BYPASS_DATAOUT01, RX_BYPASS_DATAOUT02, RX_BYPASS_DATAOUT03, RX_BYPASS_DATAOUT04, RX_BYPASS_DATAOUT05, RX_BYPASS_DATAOUT06, RX_BYPASS_DATAOUT07, RX_BYPASS_DATAOUT08, RX_BYPASS_DATAOUT09, RX_BYPASS_DATAOUT10, RX_BYPASS_DATAOUT11, RX_BYPASS_ENAOUT, RX_BYPASS_IS_AVAILOUT, RX_BYPASS_IS_BADLYFRAMEDOUT, RX_BYPASS_IS_OVERFLOWOUT, RX_BYPASS_IS_SYNCEDOUT, RX_BYPASS_IS_SYNCWORDOUT, RX_CHANOUT0 +, RX_CHANOUT1, RX_CHANOUT2, RX_CHANOUT3, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_MTYOUT0, RX_MTYOUT1 +, RX_MTYOUT2, RX_MTYOUT3, RX_OVFOUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_TYPE_ERR, STAT_RX_BURSTMAX_ERR, STAT_RX_BURST_ERR, STAT_RX_CRC24_ERR, STAT_RX_CRC32_ERR, STAT_RX_CRC32_VALID, STAT_RX_DESCRAM_ERR, STAT_RX_DIAGWORD_INTFSTAT, STAT_RX_DIAGWORD_LANESTAT, STAT_RX_FC_STAT, STAT_RX_FRAMING_ERR, STAT_RX_MEOP_ERR +, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MSOP_ERR, STAT_RX_MUBITS, STAT_RX_MUBITS_UPDATED, STAT_RX_OVERFLOW_ERR, STAT_RX_RETRANS_CRC24_ERR, STAT_RX_RETRANS_DISC, STAT_RX_RETRANS_LATENCY, STAT_RX_RETRANS_REQ, STAT_RX_RETRANS_RETRY_ERR, STAT_RX_RETRANS_SEQ, STAT_RX_RETRANS_SEQ_UPDATED, STAT_RX_RETRANS_STATE, STAT_RX_RETRANS_SUBSEQ, STAT_RX_RETRANS_WDOG_ERR, STAT_RX_RETRANS_WRAP_ERR, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR +, STAT_RX_WORD_SYNC, STAT_TX_BURST_ERR, STAT_TX_ERRINJ_BITERR_DONE, STAT_TX_OVERFLOW_ERR, STAT_TX_RETRANS_BURST_ERR, STAT_TX_RETRANS_BUSY, STAT_TX_RETRANS_RAM_PERROUT, STAT_TX_RETRANS_RAM_RADDR, STAT_TX_RETRANS_RAM_RD_B0, STAT_TX_RETRANS_RAM_RD_B1, STAT_TX_RETRANS_RAM_RD_B2, STAT_TX_RETRANS_RAM_RD_B3, STAT_TX_RETRANS_RAM_RSEL, STAT_TX_RETRANS_RAM_WADDR, STAT_TX_RETRANS_RAM_WDATA, STAT_TX_RETRANS_RAM_WE_B0, STAT_TX_RETRANS_RAM_WE_B1, STAT_TX_RETRANS_RAM_WE_B2, STAT_TX_RETRANS_RAM_WE_B3, STAT_TX_UNDERFLOW_ERR, TX_OVFOUT +, TX_RDYOUT, TX_SERDES_DATA00, TX_SERDES_DATA01, TX_SERDES_DATA02, TX_SERDES_DATA03, TX_SERDES_DATA04, TX_SERDES_DATA05, TX_SERDES_DATA06, TX_SERDES_DATA07, TX_SERDES_DATA08, TX_SERDES_DATA09, TX_SERDES_DATA10, TX_SERDES_DATA11, CORE_CLK, CTL_RX_FORCE_RESYNC, CTL_RX_RETRANS_ACK, CTL_RX_RETRANS_ENABLE, CTL_RX_RETRANS_ERRIN, CTL_RX_RETRANS_FORCE_REQ, CTL_RX_RETRANS_RESET, CTL_RX_RETRANS_RESET_MODE +, CTL_TX_DIAGWORD_INTFSTAT, CTL_TX_DIAGWORD_LANESTAT, CTL_TX_ENABLE, CTL_TX_ERRINJ_BITERR_GO, CTL_TX_ERRINJ_BITERR_LANE, CTL_TX_FC_STAT, CTL_TX_MUBITS, CTL_TX_RETRANS_ENABLE, CTL_TX_RETRANS_RAM_PERRIN, CTL_TX_RETRANS_RAM_RDATA, CTL_TX_RETRANS_REQ, CTL_TX_RETRANS_REQ_VALID, CTL_TX_RLIM_DELTA, CTL_TX_RLIM_ENABLE, CTL_TX_RLIM_INTV, CTL_TX_RLIM_MAX, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE +, LBUS_CLK, RX_BYPASS_FORCE_REALIGNIN, RX_BYPASS_RDIN, RX_RESET, RX_SERDES_CLK, RX_SERDES_DATA00, RX_SERDES_DATA01, RX_SERDES_DATA02, RX_SERDES_DATA03, RX_SERDES_DATA04, RX_SERDES_DATA05, RX_SERDES_DATA06, RX_SERDES_DATA07, RX_SERDES_DATA08, RX_SERDES_DATA09, RX_SERDES_DATA10, RX_SERDES_DATA11, RX_SERDES_RESET, TX_BCTLIN0, TX_BCTLIN1, TX_BCTLIN2 +, TX_BCTLIN3, TX_BYPASS_CTRLIN, TX_BYPASS_DATAIN00, TX_BYPASS_DATAIN01, TX_BYPASS_DATAIN02, TX_BYPASS_DATAIN03, TX_BYPASS_DATAIN04, TX_BYPASS_DATAIN05, TX_BYPASS_DATAIN06, TX_BYPASS_DATAIN07, TX_BYPASS_DATAIN08, TX_BYPASS_DATAIN09, TX_BYPASS_DATAIN10, TX_BYPASS_DATAIN11, TX_BYPASS_ENAIN, TX_BYPASS_GEARBOX_SEQIN, TX_BYPASS_MFRAMER_STATEIN, TX_CHANIN0, TX_CHANIN1, TX_CHANIN2, TX_CHANIN3 +, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_RESET +, TX_SERDES_REFCLK, TX_SERDES_REFCLK_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter BYPASS = "FALSE"; parameter [1:0] CTL_RX_BURSTMAX = 2'h3; parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; @@ -33579,7 +34266,17 @@ module ILKN (...); input TX_SOPIN3; endmodule -module ILKNE4 (...); +module ILKNE4(DRP_DO, DRP_RDY, RX_BYPASS_DATAOUT00, RX_BYPASS_DATAOUT01, RX_BYPASS_DATAOUT02, RX_BYPASS_DATAOUT03, RX_BYPASS_DATAOUT04, RX_BYPASS_DATAOUT05, RX_BYPASS_DATAOUT06, RX_BYPASS_DATAOUT07, RX_BYPASS_DATAOUT08, RX_BYPASS_DATAOUT09, RX_BYPASS_DATAOUT10, RX_BYPASS_DATAOUT11, RX_BYPASS_ENAOUT, RX_BYPASS_IS_AVAILOUT, RX_BYPASS_IS_BADLYFRAMEDOUT, RX_BYPASS_IS_OVERFLOWOUT, RX_BYPASS_IS_SYNCEDOUT, RX_BYPASS_IS_SYNCWORDOUT, RX_CHANOUT0 +, RX_CHANOUT1, RX_CHANOUT2, RX_CHANOUT3, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_MTYOUT0, RX_MTYOUT1 +, RX_MTYOUT2, RX_MTYOUT3, RX_OVFOUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_TYPE_ERR, STAT_RX_BURSTMAX_ERR, STAT_RX_BURST_ERR, STAT_RX_CRC24_ERR, STAT_RX_CRC32_ERR, STAT_RX_CRC32_VALID, STAT_RX_DESCRAM_ERR, STAT_RX_DIAGWORD_INTFSTAT, STAT_RX_DIAGWORD_LANESTAT, STAT_RX_FC_STAT, STAT_RX_FRAMING_ERR, STAT_RX_MEOP_ERR +, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MSOP_ERR, STAT_RX_MUBITS, STAT_RX_MUBITS_UPDATED, STAT_RX_OVERFLOW_ERR, STAT_RX_RETRANS_CRC24_ERR, STAT_RX_RETRANS_DISC, STAT_RX_RETRANS_LATENCY, STAT_RX_RETRANS_REQ, STAT_RX_RETRANS_RETRY_ERR, STAT_RX_RETRANS_SEQ, STAT_RX_RETRANS_SEQ_UPDATED, STAT_RX_RETRANS_STATE, STAT_RX_RETRANS_SUBSEQ, STAT_RX_RETRANS_WDOG_ERR, STAT_RX_RETRANS_WRAP_ERR, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR +, STAT_RX_WORD_SYNC, STAT_TX_BURST_ERR, STAT_TX_ERRINJ_BITERR_DONE, STAT_TX_OVERFLOW_ERR, STAT_TX_RETRANS_BURST_ERR, STAT_TX_RETRANS_BUSY, STAT_TX_RETRANS_RAM_PERROUT, STAT_TX_RETRANS_RAM_RADDR, STAT_TX_RETRANS_RAM_RD_B0, STAT_TX_RETRANS_RAM_RD_B1, STAT_TX_RETRANS_RAM_RD_B2, STAT_TX_RETRANS_RAM_RD_B3, STAT_TX_RETRANS_RAM_RSEL, STAT_TX_RETRANS_RAM_WADDR, STAT_TX_RETRANS_RAM_WDATA, STAT_TX_RETRANS_RAM_WE_B0, STAT_TX_RETRANS_RAM_WE_B1, STAT_TX_RETRANS_RAM_WE_B2, STAT_TX_RETRANS_RAM_WE_B3, STAT_TX_UNDERFLOW_ERR, TX_OVFOUT +, TX_RDYOUT, TX_SERDES_DATA00, TX_SERDES_DATA01, TX_SERDES_DATA02, TX_SERDES_DATA03, TX_SERDES_DATA04, TX_SERDES_DATA05, TX_SERDES_DATA06, TX_SERDES_DATA07, TX_SERDES_DATA08, TX_SERDES_DATA09, TX_SERDES_DATA10, TX_SERDES_DATA11, CORE_CLK, CTL_RX_FORCE_RESYNC, CTL_RX_RETRANS_ACK, CTL_RX_RETRANS_ENABLE, CTL_RX_RETRANS_ERRIN, CTL_RX_RETRANS_FORCE_REQ, CTL_RX_RETRANS_RESET, CTL_RX_RETRANS_RESET_MODE +, CTL_TX_DIAGWORD_INTFSTAT, CTL_TX_DIAGWORD_LANESTAT, CTL_TX_ENABLE, CTL_TX_ERRINJ_BITERR_GO, CTL_TX_ERRINJ_BITERR_LANE, CTL_TX_FC_STAT, CTL_TX_MUBITS, CTL_TX_RETRANS_ENABLE, CTL_TX_RETRANS_RAM_PERRIN, CTL_TX_RETRANS_RAM_RDATA, CTL_TX_RETRANS_REQ, CTL_TX_RETRANS_REQ_VALID, CTL_TX_RLIM_DELTA, CTL_TX_RLIM_ENABLE, CTL_TX_RLIM_INTV, CTL_TX_RLIM_MAX, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE +, LBUS_CLK, RX_BYPASS_FORCE_REALIGNIN, RX_BYPASS_RDIN, RX_RESET, RX_SERDES_CLK, RX_SERDES_DATA00, RX_SERDES_DATA01, RX_SERDES_DATA02, RX_SERDES_DATA03, RX_SERDES_DATA04, RX_SERDES_DATA05, RX_SERDES_DATA06, RX_SERDES_DATA07, RX_SERDES_DATA08, RX_SERDES_DATA09, RX_SERDES_DATA10, RX_SERDES_DATA11, RX_SERDES_RESET, TX_BCTLIN0, TX_BCTLIN1, TX_BCTLIN2 +, TX_BCTLIN3, TX_BYPASS_CTRLIN, TX_BYPASS_DATAIN00, TX_BYPASS_DATAIN01, TX_BYPASS_DATAIN02, TX_BYPASS_DATAIN03, TX_BYPASS_DATAIN04, TX_BYPASS_DATAIN05, TX_BYPASS_DATAIN06, TX_BYPASS_DATAIN07, TX_BYPASS_DATAIN08, TX_BYPASS_DATAIN09, TX_BYPASS_DATAIN10, TX_BYPASS_DATAIN11, TX_BYPASS_ENAIN, TX_BYPASS_GEARBOX_SEQIN, TX_BYPASS_MFRAMER_STATEIN, TX_CHANIN0, TX_CHANIN1, TX_CHANIN2, TX_CHANIN3 +, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_RESET +, TX_SERDES_REFCLK, TX_SERDES_REFCLK_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3); parameter BYPASS = "FALSE"; parameter [1:0] CTL_RX_BURSTMAX = 2'h3; parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; @@ -33825,7 +34522,17 @@ module ILKNE4 (...); endmodule (* keep *) -module VCU (...); +module VCU(VCUPLARREADYAXILITEAPB, VCUPLAWREADYAXILITEAPB, VCUPLBRESPAXILITEAPB, VCUPLBVALIDAXILITEAPB, VCUPLCORESTATUSCLKPLL, VCUPLDECARADDR0, VCUPLDECARADDR1, VCUPLDECARBURST0, VCUPLDECARBURST1, VCUPLDECARCACHE0, VCUPLDECARCACHE1, VCUPLDECARID0, VCUPLDECARID1, VCUPLDECARLEN0, VCUPLDECARLEN1, VCUPLDECARPROT0, VCUPLDECARPROT1, VCUPLDECARQOS0, VCUPLDECARQOS1, VCUPLDECARSIZE0, VCUPLDECARSIZE1 +, VCUPLDECARVALID0, VCUPLDECARVALID1, VCUPLDECAWADDR0, VCUPLDECAWADDR1, VCUPLDECAWBURST0, VCUPLDECAWBURST1, VCUPLDECAWCACHE0, VCUPLDECAWCACHE1, VCUPLDECAWID0, VCUPLDECAWID1, VCUPLDECAWLEN0, VCUPLDECAWLEN1, VCUPLDECAWPROT0, VCUPLDECAWPROT1, VCUPLDECAWQOS0, VCUPLDECAWQOS1, VCUPLDECAWSIZE0, VCUPLDECAWSIZE1, VCUPLDECAWVALID0, VCUPLDECAWVALID1, VCUPLDECBREADY0 +, VCUPLDECBREADY1, VCUPLDECRREADY0, VCUPLDECRREADY1, VCUPLDECWDATA0, VCUPLDECWDATA1, VCUPLDECWLAST0, VCUPLDECWLAST1, VCUPLDECWVALID0, VCUPLDECWVALID1, VCUPLENCALL2CADDR, VCUPLENCALL2CRVALID, VCUPLENCALL2CWDATA, VCUPLENCALL2CWVALID, VCUPLENCARADDR0, VCUPLENCARADDR1, VCUPLENCARBURST0, VCUPLENCARBURST1, VCUPLENCARCACHE0, VCUPLENCARCACHE1, VCUPLENCARID0, VCUPLENCARID1 +, VCUPLENCARLEN0, VCUPLENCARLEN1, VCUPLENCARPROT0, VCUPLENCARPROT1, VCUPLENCARQOS0, VCUPLENCARQOS1, VCUPLENCARSIZE0, VCUPLENCARSIZE1, VCUPLENCARVALID0, VCUPLENCARVALID1, VCUPLENCAWADDR0, VCUPLENCAWADDR1, VCUPLENCAWBURST0, VCUPLENCAWBURST1, VCUPLENCAWCACHE0, VCUPLENCAWCACHE1, VCUPLENCAWID0, VCUPLENCAWID1, VCUPLENCAWLEN0, VCUPLENCAWLEN1, VCUPLENCAWPROT0 +, VCUPLENCAWPROT1, VCUPLENCAWQOS0, VCUPLENCAWQOS1, VCUPLENCAWSIZE0, VCUPLENCAWSIZE1, VCUPLENCAWVALID0, VCUPLENCAWVALID1, VCUPLENCBREADY0, VCUPLENCBREADY1, VCUPLENCRREADY0, VCUPLENCRREADY1, VCUPLENCWDATA0, VCUPLENCWDATA1, VCUPLENCWLAST0, VCUPLENCWLAST1, VCUPLENCWVALID0, VCUPLENCWVALID1, VCUPLMCUMAXIICDCARADDR, VCUPLMCUMAXIICDCARBURST, VCUPLMCUMAXIICDCARCACHE, VCUPLMCUMAXIICDCARID +, VCUPLMCUMAXIICDCARLEN, VCUPLMCUMAXIICDCARLOCK, VCUPLMCUMAXIICDCARPROT, VCUPLMCUMAXIICDCARQOS, VCUPLMCUMAXIICDCARSIZE, VCUPLMCUMAXIICDCARVALID, VCUPLMCUMAXIICDCAWADDR, VCUPLMCUMAXIICDCAWBURST, VCUPLMCUMAXIICDCAWCACHE, VCUPLMCUMAXIICDCAWID, VCUPLMCUMAXIICDCAWLEN, VCUPLMCUMAXIICDCAWLOCK, VCUPLMCUMAXIICDCAWPROT, VCUPLMCUMAXIICDCAWQOS, VCUPLMCUMAXIICDCAWSIZE, VCUPLMCUMAXIICDCAWVALID, VCUPLMCUMAXIICDCBREADY, VCUPLMCUMAXIICDCRREADY, VCUPLMCUMAXIICDCWDATA, VCUPLMCUMAXIICDCWLAST, VCUPLMCUMAXIICDCWSTRB +, VCUPLMCUMAXIICDCWVALID, VCUPLMCUSTATUSCLKPLL, VCUPLPINTREQ, VCUPLPLLSTATUSPLLLOCK, VCUPLPWRSUPPLYSTATUSVCCAUX, VCUPLPWRSUPPLYSTATUSVCUINT, VCUPLRDATAAXILITEAPB, VCUPLRRESPAXILITEAPB, VCUPLRVALIDAXILITEAPB, VCUPLWREADYAXILITEAPB, INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD, PLVCUARADDRAXILITEAPB, PLVCUARPROTAXILITEAPB, PLVCUARVALIDAXILITEAPB, PLVCUAWADDRAXILITEAPB, PLVCUAWPROTAXILITEAPB, PLVCUAWVALIDAXILITEAPB, PLVCUAXIDECCLK, PLVCUAXIENCCLK, PLVCUAXILITECLK, PLVCUAXIMCUCLK +, PLVCUBREADYAXILITEAPB, PLVCUCORECLK, PLVCUDECARREADY0, PLVCUDECARREADY1, PLVCUDECAWREADY0, PLVCUDECAWREADY1, PLVCUDECBID0, PLVCUDECBID1, PLVCUDECBRESP0, PLVCUDECBRESP1, PLVCUDECBVALID0, PLVCUDECBVALID1, PLVCUDECRDATA0, PLVCUDECRDATA1, PLVCUDECRID0, PLVCUDECRID1, PLVCUDECRLAST0, PLVCUDECRLAST1, PLVCUDECRRESP0, PLVCUDECRRESP1, PLVCUDECRVALID0 +, PLVCUDECRVALID1, PLVCUDECWREADY0, PLVCUDECWREADY1, PLVCUENCALL2CRDATA, PLVCUENCALL2CRREADY, PLVCUENCARREADY0, PLVCUENCARREADY1, PLVCUENCAWREADY0, PLVCUENCAWREADY1, PLVCUENCBID0, PLVCUENCBID1, PLVCUENCBRESP0, PLVCUENCBRESP1, PLVCUENCBVALID0, PLVCUENCBVALID1, PLVCUENCL2CCLK, PLVCUENCRDATA0, PLVCUENCRDATA1, PLVCUENCRID0, PLVCUENCRID1, PLVCUENCRLAST0 +, PLVCUENCRLAST1, PLVCUENCRRESP0, PLVCUENCRRESP1, PLVCUENCRVALID0, PLVCUENCRVALID1, PLVCUENCWREADY0, PLVCUENCWREADY1, PLVCUMCUCLK, PLVCUMCUMAXIICDCARREADY, PLVCUMCUMAXIICDCAWREADY, PLVCUMCUMAXIICDCBID, PLVCUMCUMAXIICDCBRESP, PLVCUMCUMAXIICDCBVALID, PLVCUMCUMAXIICDCRDATA, PLVCUMCUMAXIICDCRID, PLVCUMCUMAXIICDCRLAST, PLVCUMCUMAXIICDCRRESP, PLVCUMCUMAXIICDCRVALID, PLVCUMCUMAXIICDCWREADY, PLVCUPLLREFCLKPL, PLVCURAWRSTN +, PLVCURREADYAXILITEAPB, PLVCUWDATAAXILITEAPB, PLVCUWSTRBAXILITEAPB, PLVCUWVALIDAXILITEAPB); parameter integer CORECLKREQ = 667; parameter integer DECHORRESOLUTION = 3840; parameter DECODERCHROMAFORMAT = "4_2_2"; @@ -34057,7 +34764,9 @@ module VCU (...); input PLVCUWVALIDAXILITEAPB; endmodule -module FE (...); +module FE(DEBUG_DOUT, DEBUG_PHASE, INTERRUPT, M_AXIS_DOUT_TDATA, M_AXIS_DOUT_TLAST, M_AXIS_DOUT_TVALID, M_AXIS_STATUS_TDATA, M_AXIS_STATUS_TVALID, SPARE_OUT, S_AXIS_CTRL_TREADY, S_AXIS_DIN_TREADY, S_AXIS_DIN_WORDS_TREADY, S_AXIS_DOUT_WORDS_TREADY, S_AXI_ARREADY, S_AXI_AWREADY, S_AXI_BVALID, S_AXI_RDATA, S_AXI_RVALID, S_AXI_WREADY, CORE_CLK, DEBUG_CLK_EN +, DEBUG_EN, DEBUG_SEL_IN, M_AXIS_DOUT_ACLK, M_AXIS_DOUT_TREADY, M_AXIS_STATUS_ACLK, M_AXIS_STATUS_TREADY, RESET_N, SPARE_IN, S_AXIS_CTRL_ACLK, S_AXIS_CTRL_TDATA, S_AXIS_CTRL_TVALID, S_AXIS_DIN_ACLK, S_AXIS_DIN_TDATA, S_AXIS_DIN_TLAST, S_AXIS_DIN_TVALID, S_AXIS_DIN_WORDS_ACLK, S_AXIS_DIN_WORDS_TDATA, S_AXIS_DIN_WORDS_TLAST, S_AXIS_DIN_WORDS_TVALID, S_AXIS_DOUT_WORDS_ACLK, S_AXIS_DOUT_WORDS_TDATA +, S_AXIS_DOUT_WORDS_TLAST, S_AXIS_DOUT_WORDS_TVALID, S_AXI_ACLK, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_BREADY, S_AXI_RREADY, S_AXI_WDATA, S_AXI_WVALID); parameter MODE = "TURBO_DECODE"; parameter real PHYSICAL_UTILIZATION = 100.00; parameter SIM_DEVICE = "ULTRASCALE_PLUS"; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 46b30573c..c487206db 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -386,6 +386,8 @@ struct SynthXilinxPass : public ScriptPass run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')"); run("clean", " (skip if '-nosrl' and '-widemux=0')"); } + + run("sort"); } if (check_label("map_dsp", "(skip if '-nodsp')")) { diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index 22e6bce5b..194b9ac10 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -263,6 +263,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp)); log_debug("preAdd: %s\n", log_id(st.preAdd, "--")); + log_debug("preSub: %s\n", log_id(st.preSub, "--")); log_debug("ffAD: %s\n", log_id(st.ffAD, "--")); log_debug("ffA2: %s\n", log_id(st.ffA2, "--")); log_debug("ffA1: %s\n", log_id(st.ffA1, "--")); @@ -278,17 +279,22 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) Cell *cell = st.dsp; - if (st.preAdd) { - log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type)); - bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool(); - bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool(); - if (st.sigA == st.preAdd->getPort(ID::B)) + if (st.preAdd || st.preSub) { + Cell* preAdder = st.preAdd ? st.preAdd : st.preSub; + + log(" preadder %s (%s)\n", log_id(preAdder), log_id(preAdder->type)); + bool A_SIGNED = preAdder->getParam(ID::A_SIGNED).as_bool(); + bool D_SIGNED = preAdder->getParam(ID::B_SIGNED).as_bool(); + if (st.sigA == preAdder->getPort(ID::B)) std::swap(A_SIGNED, D_SIGNED); st.sigA.extend_u0(30, A_SIGNED); st.sigD.extend_u0(25, D_SIGNED); cell->setPort(ID::A, st.sigA); cell->setPort(ID::D, st.sigD); - cell->setPort(ID(INMODE), Const::from_string("00100")); + if (preAdder->type == ID($add)) + cell->setPort(ID(INMODE), Const::from_string("00100")); + else + cell->setPort(ID(INMODE), Const::from_string("01100")); if (st.ffAD) { if (st.ffAD->type.in(ID($dffe), ID($sdffe))) { @@ -303,7 +309,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(USE_DPORT), Const("TRUE")); - pm.autoremove(st.preAdd); + pm.autoremove(preAdder); } if (st.postAdd) { log(" postadder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); diff --git a/techlibs/xilinx/xilinx_dsp.pmg b/techlibs/xilinx/xilinx_dsp.pmg index ef0157621..6ec891290 100644 --- a/techlibs/xilinx/xilinx_dsp.pmg +++ b/techlibs/xilinx/xilinx_dsp.pmg @@ -6,6 +6,8 @@ // If ADREG matched, treat 'A' input as input of ADREG // ( 3) Match the driver of the 'A' and 'D' inputs for a possible $add cell // (pre-adder) +// (3.1) Match the driver of the 'A' and 'D' inputs for a possible $sub cell +// (pre-adder) // ( 4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // If A2REG, then match 'A' input for A1REG @@ -152,13 +154,41 @@ code sigA sigD } endcode +// (3.1) Match the driver of the 'A' and 'D' inputs for a possible $sub cell +// (pre-adder) +match preSub + if sigD.empty() || sigD.is_fully_zero() + // Ensure that preAdder not already used + if param(dsp, \USE_DPORT).decode_string() == "FALSE" + if port(dsp, \INMODE, Const(0, 5)).is_fully_zero() + + select preSub->type.in($sub) + // Output has to be 25 bits or less + select GetSize(port(preSub, \Y)) <= 25 + select nusers(port(preSub, \Y)) == 2 + // D port has to be 25 bits or less + select GetSize(port(preSub, \A)) <= 25 + // A port has to be 30 bits or less + select GetSize(port(preSub, \B)) <= 30 + index port(preSub, \Y) === sigA + + optional +endmatch + +code sigA sigD + if (preSub) { + sigD = port(preSub, \A); + sigA = port(preSub, \B); + } +endcode + // (4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // Then match 'A' input for A1REG code argQ ffAD sigA clock ffA2 ffA1 // Only search for ffA2 if there was a pre-adder // (otherwise ffA2 would have been matched as ffAD) - if (preAdd) { + if (preAdd || preSub) { if (param(dsp, \AREG).as_int() == 0) { argQ = sigA; subpattern(in_dffe); diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore index 4bb3e67f6..ef347c9d3 100644 --- a/tests/aiger/.gitignore +++ b/tests/aiger/.gitignore @@ -1,2 +1,3 @@ /*_ref.v /neg.out/ +/gate/ diff --git a/tests/aiger/gold/__ANDNOT__00000.aag b/tests/aiger/gold/__ANDNOT__00000.aag new file mode 100644 index 000000000..93f5c0044 --- /dev/null +++ b/tests/aiger/gold/__ANDNOT__00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +6 +6 5 2 +c +Generated by Yosys diff --git a/tests/aiger/gold/__AND__00000.aag b/tests/aiger/gold/__AND__00000.aag new file mode 100644 index 000000000..5b0148022 --- /dev/null +++ b/tests/aiger/gold/__AND__00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +6 +6 4 2 +c +Generated by Yosys diff --git a/tests/aiger/gold/__AOI3__00000.aag b/tests/aiger/gold/__AOI3__00000.aag new file mode 100644 index 000000000..a726927fe --- /dev/null +++ b/tests/aiger/gold/__AOI3__00000.aag @@ -0,0 +1,9 @@ +aag 5 3 0 1 2 +2 +4 +6 +10 +8 4 2 +10 9 7 +c +Generated by Yosys diff --git a/tests/aiger/gold/__AOI4__00000.aag b/tests/aiger/gold/__AOI4__00000.aag new file mode 100644 index 000000000..4044dc5a8 --- /dev/null +++ b/tests/aiger/gold/__AOI4__00000.aag @@ -0,0 +1,11 @@ +aag 7 4 0 1 3 +2 +4 +6 +8 +14 +10 4 2 +12 8 6 +14 13 11 +c +Generated by Yosys diff --git a/tests/aiger/gold/__BUF__00000.aag b/tests/aiger/gold/__BUF__00000.aag new file mode 100644 index 000000000..7a4cd3156 --- /dev/null +++ b/tests/aiger/gold/__BUF__00000.aag @@ -0,0 +1,5 @@ +aag 1 1 0 1 0 +2 +2 +c +Generated by Yosys diff --git a/tests/aiger/gold/__MUX__00000.aag b/tests/aiger/gold/__MUX__00000.aag new file mode 100644 index 000000000..4d1757a65 --- /dev/null +++ b/tests/aiger/gold/__MUX__00000.aag @@ -0,0 +1,10 @@ +aag 6 3 0 1 3 +2 +4 +6 +13 +8 7 2 +10 6 4 +12 11 9 +c +Generated by Yosys diff --git a/tests/aiger/gold/__NAND__00000.aag b/tests/aiger/gold/__NAND__00000.aag new file mode 100644 index 000000000..bc42187b1 --- /dev/null +++ b/tests/aiger/gold/__NAND__00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 4 2 +c +Generated by Yosys diff --git a/tests/aiger/gold/__NMUX__00000.aag b/tests/aiger/gold/__NMUX__00000.aag new file mode 100644 index 000000000..b939855f9 --- /dev/null +++ b/tests/aiger/gold/__NMUX__00000.aag @@ -0,0 +1,10 @@ +aag 6 3 0 1 3 +2 +4 +6 +12 +8 7 2 +10 6 4 +12 11 9 +c +Generated by Yosys diff --git a/tests/aiger/gold/__NOR__00000.aag b/tests/aiger/gold/__NOR__00000.aag new file mode 100644 index 000000000..30b1d6c95 --- /dev/null +++ b/tests/aiger/gold/__NOR__00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +6 +6 5 3 +c +Generated by Yosys diff --git a/tests/aiger/gold/__NOT__00000.aag b/tests/aiger/gold/__NOT__00000.aag new file mode 100644 index 000000000..0c9119cea --- /dev/null +++ b/tests/aiger/gold/__NOT__00000.aag @@ -0,0 +1,5 @@ +aag 1 1 0 1 0 +2 +3 +c +Generated by Yosys diff --git a/tests/aiger/gold/__OAI3__00000.aag b/tests/aiger/gold/__OAI3__00000.aag new file mode 100644 index 000000000..9f8af1f72 --- /dev/null +++ b/tests/aiger/gold/__OAI3__00000.aag @@ -0,0 +1,9 @@ +aag 5 3 0 1 2 +2 +4 +6 +11 +8 5 3 +10 9 6 +c +Generated by Yosys diff --git a/tests/aiger/gold/__OAI4__00000.aag b/tests/aiger/gold/__OAI4__00000.aag new file mode 100644 index 000000000..871c05ba3 --- /dev/null +++ b/tests/aiger/gold/__OAI4__00000.aag @@ -0,0 +1,11 @@ +aag 7 4 0 1 3 +2 +4 +6 +8 +15 +10 5 3 +12 9 7 +14 13 11 +c +Generated by Yosys diff --git a/tests/aiger/gold/__ORNOT__00000.aag b/tests/aiger/gold/__ORNOT__00000.aag new file mode 100644 index 000000000..fc7263fce --- /dev/null +++ b/tests/aiger/gold/__ORNOT__00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 4 3 +c +Generated by Yosys diff --git a/tests/aiger/gold/__OR__00000.aag b/tests/aiger/gold/__OR__00000.aag new file mode 100644 index 000000000..d5e8085c2 --- /dev/null +++ b/tests/aiger/gold/__OR__00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 5 3 +c +Generated by Yosys diff --git a/tests/aiger/gold/__XNOR__00000.aag b/tests/aiger/gold/__XNOR__00000.aag new file mode 100644 index 000000000..18bb92393 --- /dev/null +++ b/tests/aiger/gold/__XNOR__00000.aag @@ -0,0 +1,9 @@ +aag 5 2 0 1 3 +2 +4 +11 +6 4 2 +8 5 3 +10 9 7 +c +Generated by Yosys diff --git a/tests/aiger/gold/__XOR__00000.aag b/tests/aiger/gold/__XOR__00000.aag new file mode 100644 index 000000000..ab4bc32ad --- /dev/null +++ b/tests/aiger/gold/__XOR__00000.aag @@ -0,0 +1,9 @@ +aag 5 2 0 1 3 +2 +4 +10 +6 4 2 +8 5 3 +10 9 7 +c +Generated by Yosys diff --git a/tests/aiger/gold/_add_00000.aag b/tests/aiger/gold/_add_00000.aag new file mode 100644 index 000000000..9f22bc0f3 --- /dev/null +++ b/tests/aiger/gold/_add_00000.aag @@ -0,0 +1,62 @@ +aag 51 4 0 8 47 +2 +4 +6 +8 +14 +30 +42 +54 +66 +78 +90 +102 +10 6 2 +12 7 3 +14 13 11 +16 6 2 +18 8 4 +20 9 5 +22 21 19 +24 22 16 +26 21 19 +28 27 11 +30 29 25 +32 21 16 +34 33 19 +36 35 22 +38 33 19 +40 38 27 +42 41 37 +44 35 21 +46 45 19 +48 47 22 +50 45 19 +52 50 27 +54 53 49 +56 47 21 +58 57 19 +60 59 22 +62 57 19 +64 62 27 +66 65 61 +68 59 21 +70 69 19 +72 71 22 +74 69 19 +76 74 27 +78 77 73 +80 71 21 +82 81 19 +84 83 22 +86 81 19 +88 86 27 +90 89 85 +92 83 21 +94 93 19 +96 95 22 +98 93 19 +100 98 27 +102 101 97 +c +Generated by Yosys diff --git a/tests/aiger/gold/_alu_00000.aag b/tests/aiger/gold/_alu_00000.aag new file mode 100644 index 000000000..3fdb09ea5 --- /dev/null +++ b/tests/aiger/gold/_alu_00000.aag @@ -0,0 +1,45 @@ +aag 33 5 0 9 28 +2 +4 +6 +8 +10 +27 +35 +36 +38 +40 +8 +48 +58 +66 +12 8 6 +14 9 7 +16 15 13 +18 16 2 +20 15 13 +22 21 3 +24 23 10 +26 25 19 +28 8 4 +30 9 5 +32 31 27 +34 33 29 +36 35 8 +38 23 19 +40 31 29 +42 38 10 +44 23 19 +46 45 11 +48 47 43 +50 40 27 +52 31 29 +54 25 19 +56 54 53 +58 57 51 +60 35 8 +62 33 29 +64 62 9 +66 65 61 +c +Generated by Yosys diff --git a/tests/aiger/gold/_and_00000.aag b/tests/aiger/gold/_and_00000.aag new file mode 100644 index 000000000..6d3bab8d3 --- /dev/null +++ b/tests/aiger/gold/_and_00000.aag @@ -0,0 +1,28 @@ +aag 17 11 0 8 6 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +34 +34 +24 14 2 +26 16 4 +28 18 6 +30 20 8 +32 22 10 +34 22 12 +c +Generated by Yosys diff --git a/tests/aiger/gold/_buf_00000.aag b/tests/aiger/gold/_buf_00000.aag new file mode 100644 index 000000000..d373a6a80 --- /dev/null +++ b/tests/aiger/gold/_buf_00000.aag @@ -0,0 +1,15 @@ +aag 6 6 0 6 0 +2 +4 +6 +8 +10 +12 +2 +4 +6 +8 +10 +12 +c +Generated by Yosys diff --git a/tests/aiger/gold/_eq_00000.aag b/tests/aiger/gold/_eq_00000.aag new file mode 100644 index 000000000..e3cbcd2fc --- /dev/null +++ b/tests/aiger/gold/_eq_00000.aag @@ -0,0 +1,46 @@ +aag 38 11 0 5 27 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +22 +76 +0 +0 +0 +0 +24 10 2 +26 11 3 +28 27 25 +30 12 4 +32 13 5 +34 33 31 +36 35 29 +38 14 6 +40 15 7 +42 41 39 +44 43 36 +46 16 8 +48 17 9 +50 49 47 +52 51 44 +54 18 8 +56 19 9 +58 57 55 +60 59 52 +62 20 8 +64 21 9 +66 65 63 +68 67 60 +70 22 8 +72 23 9 +74 73 71 +76 75 68 +c +Generated by Yosys diff --git a/tests/aiger/gold/_ge_00000.aag b/tests/aiger/gold/_ge_00000.aag new file mode 100644 index 000000000..8ccc44797 --- /dev/null +++ b/tests/aiger/gold/_ge_00000.aag @@ -0,0 +1,9 @@ +aag 3 2 0 3 1 +2 +4 +7 +0 +0 +6 4 3 +c +Generated by Yosys diff --git a/tests/aiger/gold/_gt_00000.aag b/tests/aiger/gold/_gt_00000.aag new file mode 100644 index 000000000..cc0905ea1 --- /dev/null +++ b/tests/aiger/gold/_gt_00000.aag @@ -0,0 +1,48 @@ +aag 43 10 0 2 33 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +86 +0 +22 20 7 +24 21 6 +26 25 23 +28 18 7 +30 16 7 +32 14 7 +34 12 7 +36 10 5 +38 9 2 +40 8 3 +42 41 38 +44 11 4 +46 45 43 +48 47 37 +50 13 6 +52 51 49 +54 53 35 +56 15 6 +58 57 55 +60 59 33 +62 17 6 +64 63 61 +66 65 31 +68 19 6 +70 69 67 +72 71 29 +74 73 25 +76 75 23 +78 77 26 +80 25 23 +82 75 23 +84 82 81 +86 85 79 +c +Generated by Yosys diff --git a/tests/aiger/gold/_le_00000.aag b/tests/aiger/gold/_le_00000.aag new file mode 100644 index 000000000..75a138267 --- /dev/null +++ b/tests/aiger/gold/_le_00000.aag @@ -0,0 +1,52 @@ +aag 47 12 0 2 35 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +22 +24 +94 +0 +26 25 8 +28 24 9 +30 29 27 +32 23 8 +34 21 8 +36 19 8 +38 17 8 +40 15 6 +42 13 4 +44 11 2 +46 12 5 +48 47 44 +50 49 43 +52 14 7 +54 53 51 +56 55 41 +58 16 9 +60 59 57 +62 61 39 +64 18 9 +66 65 63 +68 67 37 +70 20 9 +72 71 69 +74 73 35 +76 22 9 +78 77 75 +80 79 33 +82 81 29 +84 83 27 +86 85 30 +88 29 27 +90 83 27 +92 90 89 +94 93 87 +c +Generated by Yosys diff --git a/tests/aiger/gold/_logic_and_00000.aag b/tests/aiger/gold/_logic_and_00000.aag new file mode 100644 index 000000000..d68c6fc34 --- /dev/null +++ b/tests/aiger/gold/_logic_and_00000.aag @@ -0,0 +1,30 @@ +aag 21 11 0 6 10 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +22 +42 +0 +0 +0 +0 +0 +24 5 3 +26 24 7 +28 26 9 +30 28 11 +32 30 13 +34 17 15 +36 34 19 +38 36 21 +40 38 23 +42 41 33 +c +Generated by Yosys diff --git a/tests/aiger/gold/_logic_not_00000.aag b/tests/aiger/gold/_logic_not_00000.aag new file mode 100644 index 000000000..7798b23e9 --- /dev/null +++ b/tests/aiger/gold/_logic_not_00000.aag @@ -0,0 +1,15 @@ +aag 7 4 0 5 3 +2 +4 +6 +8 +14 +0 +0 +0 +0 +10 5 3 +12 10 7 +14 12 9 +c +Generated by Yosys diff --git a/tests/aiger/gold/_logic_or_00000.aag b/tests/aiger/gold/_logic_or_00000.aag new file mode 100644 index 000000000..12b3364d4 --- /dev/null +++ b/tests/aiger/gold/_logic_or_00000.aag @@ -0,0 +1,29 @@ +aag 21 11 0 5 10 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +22 +43 +0 +0 +0 +0 +24 5 3 +26 24 7 +28 26 9 +30 28 11 +32 30 13 +34 17 15 +36 34 19 +38 36 21 +40 38 23 +42 40 32 +c +Generated by Yosys diff --git a/tests/aiger/gold/_lt_00000.aag b/tests/aiger/gold/_lt_00000.aag new file mode 100644 index 000000000..2169b4a53 --- /dev/null +++ b/tests/aiger/gold/_lt_00000.aag @@ -0,0 +1,43 @@ +aag 34 9 0 6 25 +2 +4 +6 +8 +10 +12 +14 +16 +18 +68 +0 +0 +0 +0 +0 +20 19 10 +22 18 11 +24 23 21 +26 19 8 +28 17 6 +30 15 4 +32 12 3 +34 13 2 +36 35 32 +38 14 5 +40 39 37 +42 41 31 +44 16 7 +46 45 43 +48 47 29 +50 18 9 +52 51 49 +54 53 27 +56 55 23 +58 57 21 +60 59 24 +62 23 21 +64 57 21 +66 64 63 +68 67 61 +c +Generated by Yosys diff --git a/tests/aiger/gold/_mux_00000.aag b/tests/aiger/gold/_mux_00000.aag new file mode 100644 index 000000000..4d1757a65 --- /dev/null +++ b/tests/aiger/gold/_mux_00000.aag @@ -0,0 +1,10 @@ +aag 6 3 0 1 3 +2 +4 +6 +13 +8 7 2 +10 6 4 +12 11 9 +c +Generated by Yosys diff --git a/tests/aiger/gold/_ne_00000.aag b/tests/aiger/gold/_ne_00000.aag new file mode 100644 index 000000000..e4d894bde --- /dev/null +++ b/tests/aiger/gold/_ne_00000.aag @@ -0,0 +1,40 @@ +aag 29 10 0 8 19 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +59 +0 +0 +0 +0 +0 +0 +0 +22 12 2 +24 13 3 +26 25 23 +28 14 4 +30 15 5 +32 31 29 +34 33 27 +36 16 6 +38 17 7 +40 39 37 +42 41 34 +44 18 8 +46 19 9 +48 47 45 +50 49 42 +52 20 10 +54 21 11 +56 55 53 +58 57 50 +c +Generated by Yosys diff --git a/tests/aiger/gold/_not_00000.aag b/tests/aiger/gold/_not_00000.aag new file mode 100644 index 000000000..3c5ede656 --- /dev/null +++ b/tests/aiger/gold/_not_00000.aag @@ -0,0 +1,11 @@ +aag 6 6 0 2 0 +2 +4 +6 +8 +10 +12 +3 +5 +c +Generated by Yosys diff --git a/tests/aiger/gold/_or_00000.aag b/tests/aiger/gold/_or_00000.aag new file mode 100644 index 000000000..58714e461 --- /dev/null +++ b/tests/aiger/gold/_or_00000.aag @@ -0,0 +1,11 @@ +aag 6 4 0 2 2 +2 +4 +6 +8 +11 +13 +10 5 3 +12 7 3 +c +Generated by Yosys diff --git a/tests/aiger/gold/_pos_00000.aag b/tests/aiger/gold/_pos_00000.aag new file mode 100644 index 000000000..29a2dd61a --- /dev/null +++ b/tests/aiger/gold/_pos_00000.aag @@ -0,0 +1,9 @@ +aag 1 1 0 5 0 +2 +2 +2 +2 +2 +2 +c +Generated by Yosys diff --git a/tests/aiger/gold/_reduce_and_00000.aag b/tests/aiger/gold/_reduce_and_00000.aag new file mode 100644 index 000000000..06db9a1dd --- /dev/null +++ b/tests/aiger/gold/_reduce_and_00000.aag @@ -0,0 +1,7 @@ +aag 1 1 0 3 0 +2 +2 +0 +0 +c +Generated by Yosys diff --git a/tests/aiger/gold/_reduce_bool_00000.aag b/tests/aiger/gold/_reduce_bool_00000.aag new file mode 100644 index 000000000..48a1410c8 --- /dev/null +++ b/tests/aiger/gold/_reduce_bool_00000.aag @@ -0,0 +1,13 @@ +aag 7 4 0 3 3 +2 +4 +6 +8 +15 +0 +0 +10 5 3 +12 10 7 +14 12 9 +c +Generated by Yosys diff --git a/tests/aiger/gold/_reduce_or_00000.aag b/tests/aiger/gold/_reduce_or_00000.aag new file mode 100644 index 000000000..d5e8085c2 --- /dev/null +++ b/tests/aiger/gold/_reduce_or_00000.aag @@ -0,0 +1,7 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 5 3 +c +Generated by Yosys diff --git a/tests/aiger/gold/_reduce_xnor_00000.aag b/tests/aiger/gold/_reduce_xnor_00000.aag new file mode 100644 index 000000000..6ad6ac39e --- /dev/null +++ b/tests/aiger/gold/_reduce_xnor_00000.aag @@ -0,0 +1,30 @@ +aag 25 6 0 2 19 +2 +4 +6 +8 +10 +12 +51 +0 +14 4 2 +16 5 3 +18 17 15 +20 18 6 +22 17 15 +24 23 7 +26 25 21 +28 26 8 +30 25 21 +32 31 9 +34 33 29 +36 34 10 +38 33 29 +40 39 11 +42 41 37 +44 42 12 +46 41 37 +48 47 13 +50 49 45 +c +Generated by Yosys diff --git a/tests/aiger/gold/_reduce_xor_00000.aag b/tests/aiger/gold/_reduce_xor_00000.aag new file mode 100644 index 000000000..ab4bc32ad --- /dev/null +++ b/tests/aiger/gold/_reduce_xor_00000.aag @@ -0,0 +1,9 @@ +aag 5 2 0 1 3 +2 +4 +10 +6 4 2 +8 5 3 +10 9 7 +c +Generated by Yosys diff --git a/tests/aiger/gold/_sub_00000.aag b/tests/aiger/gold/_sub_00000.aag new file mode 100644 index 000000000..e9d976b32 --- /dev/null +++ b/tests/aiger/gold/_sub_00000.aag @@ -0,0 +1,20 @@ +aag 16 13 0 1 3 +2 +4 +6 +8 +10 +12 +14 +16 +18 +20 +22 +24 +26 +33 +28 17 2 +30 16 3 +32 31 29 +c +Generated by Yosys diff --git a/tests/aiger/gold/_xnor_00000.aag b/tests/aiger/gold/_xnor_00000.aag new file mode 100644 index 000000000..9dd097862 --- /dev/null +++ b/tests/aiger/gold/_xnor_00000.aag @@ -0,0 +1,17 @@ +aag 10 4 0 4 6 +2 +4 +6 +8 +15 +21 +21 +21 +10 6 2 +12 7 3 +14 13 11 +16 8 4 +18 9 5 +20 19 17 +c +Generated by Yosys diff --git a/tests/aiger/gold/_xor_00000.aag b/tests/aiger/gold/_xor_00000.aag new file mode 100644 index 000000000..453b8d0ee --- /dev/null +++ b/tests/aiger/gold/_xor_00000.aag @@ -0,0 +1,12 @@ +aag 8 5 0 1 3 +2 +4 +6 +8 +10 +16 +12 8 2 +14 9 3 +16 15 13 +c +Generated by Yosys diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index ca7339ff0..94d83ede4 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -e @@ -57,3 +58,13 @@ for y in *.ys; do echo "Running $y." ../../yosys -ql ${y%.*}.log $y done + +# compare aigmap with reference +# make gold with: rm gold/*; yosys --no-version -p "test_cell -aigmap -w gold/ -n 1 -s 1 all" +rm -rf gate; mkdir gate +../../yosys --no-version -p "test_cell -aigmap -w gate/ -n 1 -s 1 all" +( + set -o pipefail + diff --brief gold gate | tee aigmap.err +) +rm aigmap.err diff --git a/tests/alumacc/run-test.sh b/tests/alumacc/run-test.sh index e9698386e..2e3f5235c 100644 --- a/tests/alumacc/run-test.sh +++ b/tests/alumacc/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -e for x in *.ys; do echo "Running $x.." diff --git a/tests/arch/gowin/bug5688.ys b/tests/arch/gowin/bug5688.ys new file mode 100644 index 000000000..39019c4d6 --- /dev/null +++ b/tests/arch/gowin/bug5688.ys @@ -0,0 +1,31 @@ +read_verilog << EOT +`default_nettype none + +module top ( + input wire clk, + input wire [9:0] rd_addr, + output reg [15:0] rd_data, + input wire [9:0] wr_addr, + input wire [15:0] wr_data, + input wire wr_en +); + + (* ram_style = "block" *) reg [15:0] mem [0:1023]; + + // Read port — separate always block + always @(posedge clk) begin + rd_data <= mem[rd_addr]; + end + + // Write port — separate always block + always @(posedge clk) begin + if (wr_en) + mem[wr_addr] <= wr_data; + end + +endmodule + +EOT +synth_gowin -top top +splitnets +select -assert-any top/mem.0.0 %ci*:+DPX9B[ADA]:+DFF:+IBUF i:wr_en %i diff --git a/tests/arch/gowin/mul_gw1n.ys b/tests/arch/gowin/mul_gw1n.ys new file mode 100644 index 000000000..9b1748255 --- /dev/null +++ b/tests/arch/gowin/mul_gw1n.ys @@ -0,0 +1,53 @@ +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +# equivalence checking is somewhat slow (and missing simulation models) +synth_gowin -family gw1n +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT9X9 + + +# Make sure that DSPs are not inferred with -nodsp option +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +synth_gowin -family gw1n -nodsp +cd top # Constrain all select calls below inside the top module +select -assert-none t:MULT9X9 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +synth_gowin -family gw1n +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 + + +# We end up with two 18x18 multipliers +# 36x36 min width is 22 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:MULT18X18 diff --git a/tests/arch/gowin/mul_gw2a.ys b/tests/arch/gowin/mul_gw2a.ys new file mode 100644 index 000000000..895c580b7 --- /dev/null +++ b/tests/arch/gowin/mul_gw2a.ys @@ -0,0 +1,53 @@ +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +# equivalence checking is somewhat slow (and missing simulation models) +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT9X9 + + +# Make sure that DSPs are not inferred with -nodsp option +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 +hierarchy -top top +proc +synth_gowin -family gw2a -nodsp +cd top # Constrain all select calls below inside the top module +select -assert-none t:MULT9X9 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 + + +# We end up with two 18x18 multipliers +# 36x36 min width is 22 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_gowin -family gw2a +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:MULT18X18 diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh index 68f925b34..7602717d2 100755 --- a/tests/arch/run-test.sh +++ b/tests/arch/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -e diff --git a/tests/arch/xilinx/dsp_preadder_sub.ys b/tests/arch/xilinx/dsp_preadder_sub.ys new file mode 100644 index 000000000..0e23ac373 --- /dev/null +++ b/tests/arch/xilinx/dsp_preadder_sub.ys @@ -0,0 +1,29 @@ +read_verilog < /dev/null && pwd ) + +pytest -v -m "not smt and not rkt" "$SCRIPT_DIR" "$@" diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index e4c78a1fb..aa7500f8b 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -74,7 +74,8 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) @pytest.mark.rkt -def test_rkt(cell, parameters, tmp_path, num_steps, rnd): +@pytest.mark.parametrize("use_assoc_list_helpers", [True, False]) +def test_rkt(cell, parameters, tmp_path, num_steps, rnd, use_assoc_list_helpers): import rkt_vcd rtlil_file = tmp_path / 'rtlil.il' @@ -83,8 +84,9 @@ def test_rkt(cell, parameters, tmp_path, num_steps, rnd): vcd_yosys_sim_file = tmp_path / 'yosys.vcd' cell.write_rtlil_file(rtlil_file, parameters) - yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {quote(rkt_file)}") - rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt")) + use_assoc_helpers_flag = '-assoc-list-helpers' if use_assoc_list_helpers else '' + yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {use_assoc_helpers_flag} {quote(rkt_file)}") + rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"), use_assoc_list_helpers=use_assoc_list_helpers) yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) def test_print_graph(tmp_path): diff --git a/tests/functional/test_smtbmc_witness_mismatch.py b/tests/functional/test_smtbmc_witness_mismatch.py new file mode 100644 index 000000000..f13620f1d --- /dev/null +++ b/tests/functional/test_smtbmc_witness_mismatch.py @@ -0,0 +1,190 @@ +import json +import shutil +import subprocess +from pathlib import Path + +import pytest + +base_path = Path(__file__).resolve().parent.parent.parent + +pytestmark = pytest.mark.skipif(shutil.which("z3") is None, reason="z3 not available") + +def run(cmd, **kwargs): + """Run a command and assert it succeeds.""" + status = subprocess.run(cmd, **kwargs) + assert status.returncode == 0, f"{cmd[0]} failed" + return status + + +def write_smt2(tmp_path, verilog_text): + """Write Verilog to temp and emit SMT2 via yosys.""" + vfile = tmp_path / "design.v" + smt2 = tmp_path / "design.smt2" + vfile.write_text(verilog_text) + run([base_path / "yosys", "-Q", "-p", + f"read_verilog {vfile}; prep -top top; write_smt2 {smt2}"]) + return smt2 + + +def witness_entries(smt2_path): + """Parse yosys-smt2-witness JSON records from an SMT2 file.""" + entries = [] + marker = "yosys-smt2-witness" + with open(smt2_path, "r") as f: + for line in f: + if marker not in line: + continue + payload = line.split(marker, 1)[1].strip() + entries.append(json.loads(payload)) + return entries + + +def find_entry(entries, entry_type): + """Return the first witness entry of the given type.""" + for entry in entries: + if entry.get("type") == entry_type: + return entry + return None + + +def write_yw(yw_path, signals, bits): + """Write a minimal Yosys witness file with one step of bits.""" + data = { + "format": "Yosys Witness Trace", + "clocks": [], + "signals": signals, + "steps": [{"bits": bits}], + } + yw_path.write_text(json.dumps(data)) + + +def run_smtbmc(smt2_path, yw_path): + """Run yosys-smtbmc on the SMT2 file with a witness trace.""" + cmd = [ + base_path / "yosys-smtbmc", + "-s", "z3", + "-m", "top", + "--check-witness", + "--yw", yw_path, + "-t", "1", + smt2_path, + ] + return subprocess.run(cmd, capture_output=True, text=True) + + +def assert_no_mismatch_message(result): + """Assert the mismatch error prefix is absent from outputs.""" + combined = (result.stderr or "") + (result.stdout or "") + assert "Yosys witness signal mismatch" not in combined + + +def assert_has_mismatch_message(result, msg): + """Assert the mismatch error prefix and substring are present.""" + combined = (result.stderr or "") + (result.stdout or "") + assert "Yosys witness signal mismatch" in combined + assert msg in combined + + +def test_missing_signal_path(tmp_path): + smt2 = write_smt2(tmp_path, "module top(input ok, output out); assign out = ok; endmodule") + yw_path = tmp_path / "trace.yw" + signals = [{"path": ["\\missing"], "offset": 0, "width": 1, "init_only": False}] + write_yw(yw_path, signals, "1") + result = run_smtbmc(smt2, yw_path) + assert result.returncode != 0 + assert_has_mismatch_message(result, "signal not found in design") + + +def test_width_mismatch(tmp_path): + smt2 = write_smt2(tmp_path, "module top(input ok, output out); assign out = ok; endmodule") + entries = witness_entries(smt2) + input_entry = find_entry(entries, "input") + assert input_entry is not None + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": input_entry["path"], + "offset": 0, + "width": 2, + "init_only": False, + }] + write_yw(yw_path, signals, "10") + result = run_smtbmc(smt2, yw_path) + assert result.returncode != 0 + assert_has_mismatch_message(result, "signal width/offset mismatch") + + +def test_memory_address_oob(tmp_path): + verilog = """ +module top(input ok, output [7:0] mem_out); + reg [7:0] mem [0:1]; + assign mem_out = mem[0] ^ {8{ok}}; +endmodule +""" + smt2 = write_smt2(tmp_path, verilog) + entries = witness_entries(smt2) + mem_entry = find_entry(entries, "mem") + assert mem_entry is not None + addr = mem_entry["size"] + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": mem_entry["path"] + [f"\\[{addr}]"], + "offset": 0, + "width": mem_entry["width"], + "init_only": False, + }] + bits = "0" * mem_entry["width"] + write_yw(yw_path, signals, bits) + result = run_smtbmc(smt2, yw_path) + assert result.returncode != 0 + assert_has_mismatch_message(result, "memory address out of bounds") + + +def test_allowed_extra_signal_in_design(tmp_path): + verilog = """ +module top(input ok, input extra, output [1:0] out); + assign out = {ok, extra}; +endmodule +""" + smt2 = write_smt2(tmp_path, verilog) + entries = witness_entries(smt2) + input_entry = find_entry(entries, "input") + assert input_entry is not None + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": input_entry["path"], + "offset": 0, + "width": input_entry["width"], + "init_only": False, + }] + bits = "0" * input_entry["width"] + write_yw(yw_path, signals, bits) + result = run_smtbmc(smt2, yw_path) + # With --check-witness and no assertions, smtbmc can still exit non-zero. + # Thus we don't check the result.returncode here and in the other success + # cases. + assert_no_mismatch_message(result) + + +def test_allowed_extra_memory_in_design(tmp_path): + verilog = """ +module top(input ok, output [7:0] out); + reg [7:0] mem0 [0:1]; + reg [7:0] mem1 [0:3]; + assign out = mem0[0] ^ mem1[0]; +endmodule +""" + smt2 = write_smt2(tmp_path, verilog) + entries = witness_entries(smt2) + input_entry = find_entry(entries, "input") + assert input_entry is not None + yw_path = tmp_path / "trace.yw" + signals = [{ + "path": input_entry["path"], + "offset": 0, + "width": input_entry["width"], + "init_only": False, + }] + bits = "1" * input_entry["width"] + write_yw(yw_path, signals, bits) + result = run_smtbmc(smt2, yw_path) + assert_no_mismatch_message(result) diff --git a/tests/gen-tests-makefile.sh b/tests/gen-tests-makefile.sh index e3308506b..a0fb23ac3 100755 --- a/tests/gen-tests-makefile.sh +++ b/tests/gen-tests-makefile.sh @@ -9,7 +9,7 @@ generate_target() { echo "all: $target_name" echo ".PHONY: $target_name" echo "$target_name:" - printf "\t@%s\n" "$test_command" + printf "\t@YOSYS_MAX_THREADS=4 %s\n" "$test_command" printf "\t@echo 'Passed %s'\n" "$target_name" } diff --git a/tests/hana/run-test.sh b/tests/hana/run-test.sh index 99be37f5e..8533e5544 100755 --- a/tests/hana/run-test.sh +++ b/tests/hana/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh OPTIND=1 seed="" # default to no seed specified diff --git a/tests/liberty/dff.lib.verilogsim.ok b/tests/liberty/dff.lib.verilogsim.ok index e560df539..5f991541f 100644 --- a/tests/liberty/dff.lib.verilogsim.ok +++ b/tests/liberty/dff.lib.verilogsim.ok @@ -5,8 +5,9 @@ module dff (D, CLK, Q); output Q; assign Q = IQ; // IQ always @(posedge CLK) begin - // "(D)" IQ <= D; + end + always @(posedge CLK) begin IQN <= ~(D); end endmodule diff --git a/tests/liberty/normal.lib.verilogsim.ok b/tests/liberty/normal.lib.verilogsim.ok index 92efbf8aa..9e8beb2e1 100644 --- a/tests/liberty/normal.lib.verilogsim.ok +++ b/tests/liberty/normal.lib.verilogsim.ok @@ -41,6 +41,7 @@ module imux2 (A, B, S, Y); endmodule module dff (D, CLK, RESET, PRESET, Q, QN); reg IQ, IQN; + wire IQ_clear, IQ_preset; input D; input CLK; input RESET; @@ -49,25 +50,30 @@ module dff (D, CLK, RESET, PRESET, Q, QN); assign Q = IQ; // "IQ" output QN; assign QN = IQN; // "IQN" - always @(posedge CLK, posedge RESET, posedge PRESET) begin - if ((RESET) && (PRESET)) begin + always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin + if (IQ_clear) begin IQ <= 0; - IQN <= 0; end - else if (RESET) begin - IQ <= 0; - IQN <= 1; - end - else if (PRESET) begin + else if (IQ_preset) begin IQ <= 1; - IQN <= 0; end else begin - // "D" IQ <= D; + end + end + always @(posedge CLK, posedge IQ_clear, posedge IQ_preset) begin + if (IQ_preset) begin + IQN <= 0; + end + else if (IQ_clear) begin + IQN <= 1; + end + else begin IQN <= ~(D); end end + assign IQ_clear = RESET; + assign IQ_preset = PRESET; endmodule module latch (D, G, Q, QN); reg IQ, IQN; diff --git a/tests/liberty/read_liberty.ys b/tests/liberty/read_liberty.ys new file mode 100644 index 000000000..7cbb0a19d --- /dev/null +++ b/tests/liberty/read_liberty.ys @@ -0,0 +1,9 @@ +read_liberty retention.lib +rename retention_cell retention_cell_lib +read_verilog retention.lib.verilogsim +proc +rename retention_cell retention_cell_vlog +async2sync +equiv_make retention_cell_lib retention_cell_vlog equiv +equiv_induct equiv +equiv_status -assert equiv diff --git a/tests/liberty/retention.lib b/tests/liberty/retention.lib new file mode 100644 index 000000000..d2f1aa325 --- /dev/null +++ b/tests/liberty/retention.lib @@ -0,0 +1,57 @@ +library (retention) { + delay_model : table_lookup; + voltage_unit : 1V; + current_unit : 1mA; + leakage_power_unit : 1nW; + time_unit : 1ns; + capacitive_load_unit (1, pf); + pulling_resistance_unit : 1kohm; + input_threshold_pct_rise : 50; + input_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + output_threshold_pct_fall : 50; + slew_lower_threshold_pct_rise : 30; + slew_upper_threshold_pct_rise : 70; + slew_upper_threshold_pct_fall : 70; + slew_lower_threshold_pct_fall : 30; + cell ("retention_cell") { + ff (Q1,QN1) { + clocked_on : "CK"; + next_state : "(D * !SE + SI * SE)"; + clear : "(((!B2B) * !Q2) + !RD)"; + preset : "((!B2B) * Q2)"; + clear_preset_var1 : "L"; + clear_preset_var2 : "H"; + } + latch (Q2,QN2) { + enable : "B1"; + data_in : "Q1"; + } + pin (B1) { + direction : input; + } + pin (B2B) { + direction : input; + } + pin (CK) { + clock : true; + direction : input; + } + pin (D) { + direction : input; + } + pin (Q) { + direction : output; + function : "Q1"; + } + pin (RD) { + direction : input; + } + pin (SE) { + direction : input; + } + pin (SI) { + direction : input; + } + } +} \ No newline at end of file diff --git a/tests/liberty/retention.lib.filtered.ok b/tests/liberty/retention.lib.filtered.ok new file mode 100644 index 000000000..0cfc7edfc --- /dev/null +++ b/tests/liberty/retention.lib.filtered.ok @@ -0,0 +1,42 @@ +library(retention) { + cell("retention_cell") { + ff(Q1, QN1) { + clocked_on : "CK" ; + next_state : "(D * !SE + SI * SE)" ; + clear : "(((!B2B) * !Q2) + !RD)" ; + preset : "((!B2B) * Q2)" ; + clear_preset_var1 : "L" ; + clear_preset_var2 : "H" ; + } + latch(Q2, QN2) { + enable : "B1" ; + data_in : "Q1" ; + } + pin(B1) { + direction : input ; + } + pin(B2B) { + direction : input ; + } + pin(CK) { + clock : true ; + direction : input ; + } + pin(D) { + direction : input ; + } + pin(Q) { + direction : output ; + function : "Q1" ; + } + pin(RD) { + direction : input ; + } + pin(SE) { + direction : input ; + } + pin(SI) { + direction : input ; + } + } +} diff --git a/tests/liberty/retention.lib.verilogsim.ok b/tests/liberty/retention.lib.verilogsim.ok new file mode 100644 index 000000000..f264e58cd --- /dev/null +++ b/tests/liberty/retention.lib.verilogsim.ok @@ -0,0 +1,44 @@ +module retention_cell (B1, B2B, CK, D, Q, RD, SE, SI); + reg Q1, QN1; + wire Q1_clear, Q1_preset; + reg Q2, QN2; + input B1; + input B2B; + input CK; + input D; + output Q; + assign Q = Q1; // "Q1" + input RD; + input SE; + input SI; + always @(posedge CK, posedge Q1_clear, posedge Q1_preset) begin + if (Q1_clear) begin + Q1 <= 0; + end + else if (Q1_preset) begin + Q1 <= 1; + end + else begin + Q1 <= ((D&(~SE))|(SI&SE)); + end + end + always @(posedge CK, posedge Q1_clear, posedge Q1_preset) begin + if (Q1_clear) begin + QN1 <= 1; + end + else if (Q1_preset) begin + QN1 <= 0; + end + else begin + QN1 <= ~(((D&(~SE))|(SI&SE))); + end + end + assign Q1_clear = (((~B2B)&(~Q2))|(~RD)); + assign Q1_preset = ((~B2B)&Q2); + always @* begin + if (B1) begin + Q2 <= Q1; + QN2 <= ~(Q1); + end + end +endmodule diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh index 5afdb727e..d5fb65e16 100755 --- a/tests/liberty/run-test.sh +++ b/tests/liberty/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -eo pipefail for x in *.lib; do diff --git a/tests/liberty/semicolextra.lib.verilogsim.ok b/tests/liberty/semicolextra.lib.verilogsim.ok index e3b14dbd2..1efbf6cf0 100644 --- a/tests/liberty/semicolextra.lib.verilogsim.ok +++ b/tests/liberty/semicolextra.lib.verilogsim.ok @@ -4,8 +4,9 @@ module DFF (D, CK, Q); input CK; output Q; always @(posedge CK) begin - // "D" IQ <= D; + end + always @(posedge CK) begin IQN <= ~(D); end endmodule diff --git a/tests/liberty/unquoted.lib.verilogsim.ok b/tests/liberty/unquoted.lib.verilogsim.ok index 2a2f1d173..f6b022194 100644 --- a/tests/liberty/unquoted.lib.verilogsim.ok +++ b/tests/liberty/unquoted.lib.verilogsim.ok @@ -5,8 +5,9 @@ module dff1 (D, CLK, Q); output Q; assign Q = IQ; // IQ always @(posedge CLK) begin - // !D IQ <= (~D); + end + always @(posedge CLK) begin IQN <= ~((~D)); end endmodule @@ -17,8 +18,9 @@ module dff2 (D, CLK, Q); output Q; assign Q = IQ; // "IQ" always @(posedge CLK) begin - // D ' IQ <= (~D); + end + always @(posedge CLK) begin IQN <= ~((~D)); end endmodule @@ -32,8 +34,9 @@ module dffe (D, EN, CLK, Q, QN); output QN; assign QN = IQN; // "IQN" always @(negedge CLK) begin - // ( D & EN ) | ( IQ & ! EN ) IQ <= ((D&EN)|(IQ&(~EN))); + end + always @(negedge CLK) begin IQN <= ~(((D&EN)|(IQ&(~EN)))); end endmodule diff --git a/tests/memfile/run-test.sh b/tests/memfile/run-test.sh index db0ec54ee..44c1e4821 100755 --- a/tests/memfile/run-test.sh +++ b/tests/memfile/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -e diff --git a/tests/memlib/run-test.sh b/tests/memlib/run-test.sh index 5f230a03e..9e95fb255 100755 --- a/tests/memlib/run-test.sh +++ b/tests/memlib/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -eu OPTIND=1 diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index 4f1da7ce7..8f83e11a1 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -e diff --git a/tests/opt/opt_balance_tree.ys b/tests/opt/opt_balance_tree.ys new file mode 100644 index 000000000..6f8b8b711 --- /dev/null +++ b/tests/opt/opt_balance_tree.ys @@ -0,0 +1,1246 @@ +# Test 1 +log -header "Simple AND chain" +log -push +design -reset +read_verilog <signed + + // Combine with unsigned offset + assign result = sum_full + $signed({6'b0, unsigned_offset}); +endmodule +EOF +check -assert + +# Check equivalence after opt_balance_tree +equiv_opt -assert opt_balance_tree +design -load postopt + +# Width reduction +equiv_opt -assert wreduce +design -load postopt + +design -reset +log -pop + + + +# Test 30 +log -header "Complex signedness with conditional sign extension" +log -push +design -reset +read_verilog < gate-level $_MUX_ +design -save gold +lut2mux +rename \top \gate +select -assert-count 3 gate/t:$_MUX_ +select -assert-count 0 gate/t:$mux +select -assert-count 0 gate/t:$lut + +# -word mode -> word-level $mux +design -copy-from gold -as top \top +select -none +select top +lut2mux -word +select -clear +rename \top \word +select -assert-count 3 word/t:$mux +select -assert-count 0 word/t:$_MUX_ +select -assert-count 0 gate/t:$lut + +# equivalence +equiv_make \gate \word equiv +hierarchy -top equiv +equiv_simple +equiv_induct +equiv_status -assert diff --git a/tests/techmap/module_not_derived.ys b/tests/techmap/module_not_derived.ys new file mode 100644 index 000000000..299e4b75b --- /dev/null +++ b/tests/techmap/module_not_derived.ys @@ -0,0 +1,31 @@ +# Test 1: internal cells from alumacc/techmap must not keep module_not_derived. +read_verilog < Y) = 453; + (D1 => Y) = 449; + (D2 => Y) = 488; + (D3 => Y) = 484; + (S0 => Y) = 422; + (S1 => Y) = 385; + endspecify + + assign Y = S1 ? (S0 ? D3 : D2) : + (S0 ? D1 : D0); + +endmodule + +EOF + +logger -expect error "Malformed design" 1 +abc_new -script abc_speed_gia_only.script -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 47b06d575..c9a12b66b 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -162,20 +162,24 @@ do cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi + touch ${bn}.iverilog compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \ "$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simcells.v + rm ${bn}.iverilog if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 test_passes() { "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" + touch ${bn}.iverilog compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \ "$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi "$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count} + rm ${bn}.iverilog test_count=$(( test_count + 1 )) } @@ -227,7 +231,9 @@ do else echo "${status_prefix}${did_firrtl}-> ERROR!" if $warn_iverilog_git; then - echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." + if [ -f ${bn}.out/${bn}.iverilog ]; then + echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." + fi fi $keeprunning || exit 1 fi diff --git a/tests/tools/rtlil-fuzz-grammar.json b/tests/tools/rtlil-fuzz-grammar.json new file mode 100644 index 000000000..c27b160f4 --- /dev/null +++ b/tests/tools/rtlil-fuzz-grammar.json @@ -0,0 +1,104 @@ +{ + "": [ + [ + "module \\test\n", + "", "", + "", + "", + "end\n" + ] + ], + "": [ [ " wire width ", "", " ", "", " ", "", "\n" ] ], + "": [ [ "1" ], [ "2" ], [ "3" ], [ "4" ], [ "32" ], [ "128" ] ], + "": [ [ "input ", "" ], [ "output ", "" ], [ "inout ", "" ], [] ], + "": [ + [ + " cell $not ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell $and ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\B_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\B_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell $or ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\B_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\B_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell $xor ", "", "\n", + " parameter \\A_SIGNED 0\n", + " parameter \\B_SIGNED 0\n", + " parameter \\A_WIDTH 0\n", + " parameter \\B_WIDTH 0\n", + " parameter \\Y_WIDTH 0\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell ", "", " ", "", "\n", + " connect \\A ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ], + [ + " cell ", "", " ", "", "\n", + " connect \\A ", "", "\n", + " connect \\B ", "", "\n", + " connect \\Y ", "", "\n", + " end\n" + ] + ], + "": [ [ "\\wire_a" ], [ "\\wire_b" ], [ "\\wire_c" ], [ "\\wire_d" ], [ "\\wire_e" ], [ "\\wire_f" ], [ "\\wire_g" ], [ "\\wire_h" ], [ "\\wire_i" ], [ "\\wire_j" ] ], + "": [ [ "\\cell_a" ], [ "\\cell_b" ], [ "\\cell_c" ], [ "\\cell_d" ], [ "\\cell_e" ], [ "\\cell_f" ], [ "\\cell_g" ], [ "\\cell_h" ], [ "\\cell_i" ], [ "\\cell_j" ] ], + "": [ [ "\\bb1" ], [ "\\bb2" ] ], + "": [ + [ "", " " ], + [ "{", "", " ", "", "}" ], + [ "" ], + [ "", "[", "", "]" ], + [ "", "[", "", ":", "", "]" ] + ], + "": [ + [ "0'", "" ], + [ "1'", "" ], + [ "2'", "" ], + [ "3'", "" ], + [ "4'", "" ], + [ "31'", "" ], + [ "32'", "" ], + [ "128'", "" ] + ], + "": [ [ "0" ], [ "1" ], [ "x" ], [ "z" ], [ "-" ], [ "m" ] ], + "": [ "0", "1", "2", "3", "31", "32" ], + "": [ "1", "2", "3", "4", "5", "6", "7", "8", "9", "10" ], + "": [ [ " connect ", "", " ", "", "\n" ] ], + + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", "" ] ], + "": [ [ ], [ "", " ", "" ] ] +} diff --git a/tests/unit/Makefile b/tests/unit/Makefile index b275d7f41..e8f76cba9 100644 --- a/tests/unit/Makefile +++ b/tests/unit/Makefile @@ -18,10 +18,11 @@ endif EXTRAFLAGS := -lyosys -pthread -OBJTEST := objtest -BINTEST := bintest +MAKEFILE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +OBJTEST := $(MAKEFILE_DIR)objtest +BINTEST := $(MAKEFILE_DIR)bintest -ALLTESTFILE := $(shell find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ') +ALLTESTFILE := $(shell cd $(MAKEFILE_DIR) && find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ') TESTDIRS := $(sort $(dir $(ALLTESTFILE))) TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o))) @@ -34,7 +35,7 @@ $(BINTEST)/%: $(OBJTEST)/%.o | prepare $(CXX) -L$(ROOTPATH) $(RPATH) $(LINKFLAGS) -o $@ $^ $(LIBS) \ $(GTEST_LDFLAGS) $(EXTRAFLAGS) -$(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc | prepare +$(OBJTEST)/%.o: $(MAKEFILE_DIR)/%.cc | prepare $(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $(GTEST_CXXFLAGS) $^ .PHONY: prepare run-tests clean diff --git a/tests/unit/kernel/modindexTest.cc b/tests/unit/kernel/modindexTest.cc new file mode 100644 index 000000000..1921c9a93 --- /dev/null +++ b/tests/unit/kernel/modindexTest.cc @@ -0,0 +1,47 @@ +#include + +#include "kernel/modtools.h" +#include "kernel/rtlil.h" + +YOSYS_NAMESPACE_BEGIN + +TEST(ModIndexSwapTest, has) +{ + Design* d = new Design; + Module* m = d->addModule("$m"); + Wire* o = m->addWire("$o", 2); + o->port_input = true; + Wire* i = m->addWire("$i", 2); + i->port_input = true; + m->fixup_ports(); + m->addNot("$not", i, o); + auto mi = ModIndex(m); + mi.reload_module(); + for (auto [sb, info] : mi.database) { + EXPECT_TRUE(mi.database.find(sb) != mi.database.end()); + } + m->swap_names(i, o); + for (auto [sb, info] : mi.database) { + EXPECT_TRUE(mi.database.find(sb) != mi.database.end()); + } +} + +TEST(ModIndexDeleteTest, has) +{ + if (log_files.empty()) log_files.emplace_back(stdout); + Design* d = new Design; + Module* m = d->addModule("$m"); + Wire* w = m->addWire("$w"); + Wire* o = m->addWire("$o"); + o->port_output = true; + m->fixup_ports(); + Cell* not_ = m->addNotGate("$not", w, o); + auto mi = ModIndex(m); + mi.reload_module(); + mi.dump_db(); + Wire* a = m->addWire("\\a"); + not_->setPort(ID::A, a); + EXPECT_TRUE(mi.ok()); +} + +YOSYS_NAMESPACE_END diff --git a/tests/unit/kernel/rtlilStringTest.cc b/tests/unit/kernel/rtlilStringTest.cc new file mode 100644 index 000000000..26b296dd4 --- /dev/null +++ b/tests/unit/kernel/rtlilStringTest.cc @@ -0,0 +1,61 @@ +#include + +#include "kernel/rtlil.h" +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +namespace RTLIL { + + TEST(RtlilStrTest, DesignToString) { + Design design; + Module *mod = design.addModule(ID(my_module)); + mod->addWire(ID(my_wire), 1); + + std::string design_str = design.to_rtlil_str(); + + EXPECT_NE(design_str.find("module \\my_module"), std::string::npos); + EXPECT_NE(design_str.find("end"), std::string::npos); + } + + TEST(RtlilStrTest, ModuleToString) { + Design design; + Module *mod = design.addModule(ID(test_mod)); + Wire *wire = mod->addWire(ID(clk), 1); + wire->port_input = true; + + std::string mod_str = mod->to_rtlil_str(); + + EXPECT_NE(mod_str.find("module \\test_mod"), std::string::npos); + EXPECT_NE(mod_str.find("wire"), std::string::npos); + EXPECT_NE(mod_str.find("\\clk"), std::string::npos); + EXPECT_NE(mod_str.find("input"), std::string::npos); + } + + TEST(RtlilStrTest, WireToString) { + Design design; + Module *mod = design.addModule(ID(m)); + Wire *wire = mod->addWire(ID(data), 8); + + std::string wire_str = wire->to_rtlil_str(); + + EXPECT_NE(wire_str.find("wire"), std::string::npos); + EXPECT_NE(wire_str.find("width 8"), std::string::npos); + EXPECT_NE(wire_str.find("\\data"), std::string::npos); + } + + TEST(RtlilStrTest, CellToString) { + Design design; + Module *mod = design.addModule(ID(m)); + Cell *cell = mod->addCell(ID(u1), ID(my_cell_type)); + + std::string cell_str = cell->to_rtlil_str(); + + EXPECT_NE(cell_str.find("cell"), std::string::npos); + EXPECT_NE(cell_str.find("\\my_cell_type"), std::string::npos); + EXPECT_NE(cell_str.find("\\u1"), std::string::npos); + } + +} + +YOSYS_NAMESPACE_END diff --git a/tests/unit/opt/optDffFindComplementaryPatternTest.cc b/tests/unit/opt/optDffFindComplementaryPatternTest.cc new file mode 100644 index 000000000..7a89da6cd --- /dev/null +++ b/tests/unit/opt/optDffFindComplementaryPatternTest.cc @@ -0,0 +1,179 @@ +#include +#include "kernel/pattern.h" + +YOSYS_NAMESPACE_BEGIN + +class FindComplementaryPatternVarTest : public ::testing::Test { +protected: + RTLIL::Design *design; + RTLIL::Module *module; + RTLIL::Wire *wire_a; + RTLIL::Wire *wire_b; + RTLIL::Wire *wire_c; + RTLIL::Wire *bus; + + void SetUp() override { + design = new RTLIL::Design; + module = design->addModule(ID(test_module)); + wire_a = module->addWire(ID(a)); + wire_b = module->addWire(ID(b)); + wire_c = module->addWire(ID(c)); + bus = module->addWire(ID(bus), 4); + } + + void TearDown() override { + delete design; + } + + RTLIL::SigBit bit(RTLIL::Wire *w, int offset = 0) { + return RTLIL::SigBit(w, offset); + } +}; + +TEST_F(FindComplementaryPatternVarTest, EmptyPatterns) { + pattern_t left, right; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, IdenticalSingleVar) { + pattern_t left, right; + left[bit(wire_a)] = true; + right[bit(wire_a)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, ComplementarySingleVar) { + pattern_t left, right; + left[bit(wire_a)] = true; + right[bit(wire_a)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_a)); +} + +TEST_F(FindComplementaryPatternVarTest, MissingKeyInRight) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, TwoVarsOneComplementary) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = true; + right[bit(wire_b)] = true; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_b)); +} + +TEST_F(FindComplementaryPatternVarTest, TwoVarsBothComplementary) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = false; + right[bit(wire_b)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, LeftSubsetOfRight) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + right[bit(wire_a)] = true; + right[bit(wire_b)] = true; + right[bit(wire_c)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_b)); +} + +TEST_F(FindComplementaryPatternVarTest, ThreeVarsAllSame) { + pattern_t left, right; + left[bit(wire_a)] = true; + left[bit(wire_b)] = false; + left[bit(wire_c)] = true; + right[bit(wire_a)] = true; + right[bit(wire_b)] = false; + right[bit(wire_c)] = true; + + auto result = find_complementary_pattern_var(left, right); + EXPECT_FALSE(result.has_value()); +} + +TEST_F(FindComplementaryPatternVarTest, PracticalPatternSimplification) { + pattern_t pattern1, pattern2; + pattern1[bit(bus, 0)] = true; + pattern1[bit(bus, 1)] = true; + pattern2[bit(bus, 0)] = true; + pattern2[bit(bus, 1)] = false; + + auto result = find_complementary_pattern_var(pattern1, pattern2); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(bus, 1)); + + // Swapped args + auto result2 = find_complementary_pattern_var(pattern2, pattern1); + ASSERT_TRUE(result2.has_value()); + EXPECT_EQ(result2.value(), bit(bus, 1)); +} + +TEST_F(FindComplementaryPatternVarTest, MuxTreeClockEnableDetection) { + pattern_t feedback_path1, feedback_path2; + feedback_path1[bit(wire_a)] = true; + feedback_path1[bit(wire_b)] = true; + feedback_path2[bit(wire_a)] = true; + feedback_path2[bit(wire_b)] = false; + + auto comp = find_complementary_pattern_var(feedback_path1, feedback_path2); + ASSERT_TRUE(comp.has_value()); + EXPECT_EQ(comp.value(), bit(wire_b)); + + pattern_t simplified = feedback_path1; + simplified.erase(comp.value()); + + EXPECT_EQ(simplified.size(), 1); + EXPECT_TRUE(simplified.count(bit(wire_a))); + EXPECT_TRUE(simplified[bit(wire_a)]); +} + +TEST_F(FindComplementaryPatternVarTest, AsymmetricPatterns) { + pattern_t left, right; + left[bit(wire_a)] = true; + right[bit(wire_a)] = false; + right[bit(wire_b)] = true; + right[bit(wire_c)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(wire_a)); +} + +TEST_F(FindComplementaryPatternVarTest, WireOffsetDistinction) { + pattern_t left, right; + left[bit(bus, 0)] = true; + left[bit(bus, 1)] = false; + right[bit(bus, 0)] = true; + right[bit(bus, 1)] = true; + right[bit(bus, 2)] = false; + + auto result = find_complementary_pattern_var(left, right); + ASSERT_TRUE(result.has_value()); + EXPECT_EQ(result.value(), bit(bus, 1)); +} + +YOSYS_NAMESPACE_END diff --git a/tests/various/.gitignore b/tests/various/.gitignore index e116179ae..9296a04c0 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -4,6 +4,8 @@ /plugin.so /plugin_search /plugin.so.dSYM +/ezcmdline_plugin.so +/ezcmdline_plugin.so.dSYM /temp /smtlib2_module.smt2 /smtlib2_module-filtered.smt2 diff --git a/tests/various/bug3515.v b/tests/various/bug3515.v new file mode 100644 index 000000000..220ae4ad6 --- /dev/null +++ b/tests/various/bug3515.v @@ -0,0 +1,26 @@ +// Triple AND GATE +module mod_74x08_3 ( + input A_1, + input B_1, + input A_2, + input B_2, + input A_3, + input B_3, + output Y_1, + output Y_2, + output Y_3); + +assign Y_1 = A_1 & B_1; +assign Y_2 = A_2 & B_2; +assign Y_3 = A_3 & B_3; + +endmodule + +// OR GATE +module mod_74x32_1 ( + input A_1, + input B_1, + output Y_1); + +assign Y_1 = A_1 | B_1; +endmodule diff --git a/tests/various/bug3515.ys b/tests/various/bug3515.ys new file mode 100644 index 000000000..783a75bb4 --- /dev/null +++ b/tests/various/bug3515.ys @@ -0,0 +1,31 @@ +# base case is able to map +read_verilog << EOF +module and_x3 ( + input a, b, c, d, + output reg y +); + +assign y = (a&b)&(c&d); +endmodule +EOF +hierarchy -top and_x3 +opt +extract -map ./bug3515.v +select -assert-count 1 t:mod_74x08_3 + +# more needles than haystacks; not able to map +design -reset +read_verilog << EOF +module mod_and_or ( + input a, b, c, d, + output reg y +); + +assign y = (a&b)|(c&d); +endmodule +EOF +hierarchy -top mod_and_or +opt +extract -map ./bug3515.v +select -assert-count 2 t:$and + diff --git a/tests/various/const_shift_empty_arg.ys b/tests/various/const_shift_empty_arg.ys new file mode 100644 index 000000000..4073e198d --- /dev/null +++ b/tests/various/const_shift_empty_arg.ys @@ -0,0 +1,49 @@ +# Regression test for #5684: const_shift_worker must not crash when arg1 is +# empty. + +read_json << EOF +{ + "modules": { + "sshl": { + "cells": { + "sshlCell": { + "connections": { + "A": [], + "B": [3], + "Y": [1] + }, + "parameters": { + "A_SIGNED": "1", + "A_WIDTH": "0", + "B_SIGNED": "0", + "B_WIDTH": "1", + "Y_WIDTH": "1" + }, + "port_directions": { + "A": "input", + "B": "input", + "Y": "output" + }, + "type": "$sshl" + } + }, + "ports": { + "A": { + "bits": [], + "direction": "input" + }, + "B": { + "bits": [3], + "direction": "input" + }, + "Y": { + "bits": [1], + "direction": "output" + } + } + } + } +} +EOF + +eval -set B 0 -show Y sshl diff --git a/tests/various/debugon.ys b/tests/various/debugon.ys new file mode 100644 index 000000000..a984a26bb --- /dev/null +++ b/tests/various/debugon.ys @@ -0,0 +1,14 @@ +# Test debug -on/-off modes + +design -reset + +read_verilog < exits 10 with v 1 +# - UNSAT: p cnf 1 2; clauses: "1 0" and "-1 0" -> exits 20 +set -e + +if [ "$#" -ne 1 ]; then + echo "usage: $0 " >&2 + exit 1 +fi + +awk ' +BEGIN { + vars = 0; + clauses = 0; + clause_count = 0; + clause_data = ""; + current = ""; +} +$1 == "c" { + next; +} +$1 == "p" && $2 == "cnf" { + vars = $3; + clauses = $4; + next; +} +{ + for (i = 1; i <= NF; i++) { + lit = $i; + if (lit == 0) { + clause_count++; + if (clause_data != "") + clause_data = clause_data ";" current; + else + clause_data = current; + current = ""; + } else { + if (current == "") + current = lit; + else + current = current "," lit; + } + } +} +END { + if (vars == 1 && clause_count == 1 && clause_data == "1") { + print "s SATISFIABLE"; + print "v 1 0"; + exit 10; + } + if (vars == 1 && clause_count == 2 && clause_data == "1;-1") { + print "s UNSATISFIABLE"; + exit 20; + } + print "c unexpected CNF for dummy solver"; + print "c vars=" vars " header_clauses=" clauses " parsed_clauses=" clause_count " data=" clause_data; + exit 1; +} +' "$1" diff --git a/tests/various/ezcmdline_plugin.cc b/tests/various/ezcmdline_plugin.cc new file mode 100644 index 000000000..b775829b3 --- /dev/null +++ b/tests/various/ezcmdline_plugin.cc @@ -0,0 +1,53 @@ +#include "kernel/yosys.h" +#include "libs/ezsat/ezcmdline.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct EzCmdlineTestPass : public Pass { + EzCmdlineTestPass() : Pass("ezcmdline_test", "smoke-test ezCmdlineSAT") { } + void execute(std::vector args, RTLIL::Design *design) override + { + std::string cmd; + size_t argidx = 1; + + while (argidx < args.size()) { + if (args[argidx] == "-cmd" && argidx + 1 < args.size()) { + cmd = args[argidx + 1]; + argidx += 2; + continue; + } + break; + } + + extra_args(args, argidx, design); + + if (cmd.empty()) + log_error("Missing -cmd argument.\n"); + + ezCmdlineSAT sat(cmd); + sat.non_incremental(); + + // assume("A") adds a permanent CNF clause "A". + sat.assume(sat.VAR("A")); + + std::vector model_expressions; + std::vector model_values; + model_expressions.push_back(sat.VAR("A")); + + // Expect SAT with A=true. + if (!sat.solve(model_expressions, model_values)) + log_error("ezCmdlineSAT SAT case failed.\n"); + if (model_values.size() != 1 || !model_values[0]) + log_error("ezCmdlineSAT SAT model mismatch.\n"); + + // Passing NOT("A") here adds a temporary unit clause for this solve call, + // so the solver sees A && !A and must return UNSAT. + if (sat.solve(model_expressions, model_values, sat.NOT("A"))) + log_error("ezCmdlineSAT UNSAT case failed.\n"); + + log("ezcmdline_test passed!\n"); + } +} EzCmdlineTestPass; + +PRIVATE_NAMESPACE_END diff --git a/tests/various/ezcmdline_plugin.sh b/tests/various/ezcmdline_plugin.sh new file mode 100644 index 000000000..cad0475a8 --- /dev/null +++ b/tests/various/ezcmdline_plugin.sh @@ -0,0 +1,12 @@ +set -e + +DIR=$(cd "$(dirname "$0")" && pwd) +BASEDIR=$(cd "$DIR/../.." && pwd) +rm -f "$DIR/ezcmdline_plugin.so" +chmod +x "$DIR/ezcmdline_dummy_solver" +CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags) +DATDIR=$("$BASEDIR/yosys-config" --datdir) +DATDIR=${DATDIR//\//\\\/} +CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share} +"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" +"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!" diff --git a/tests/various/json_param_defaults.v b/tests/various/json_param_defaults.v new file mode 100644 index 000000000..7d3b94a68 --- /dev/null +++ b/tests/various/json_param_defaults.v @@ -0,0 +1,10 @@ +module json_param_defaults #( + parameter WIDTH = 8, + parameter SIGNED = 1 +) ( + input [WIDTH-1:0] a, + output [WIDTH-1:0] y +); + wire [WIDTH-1:0] y_int = a << SIGNED; + assign y = y_int; +endmodule diff --git a/tests/various/json_param_defaults.ys b/tests/various/json_param_defaults.ys new file mode 100644 index 000000000..45e312de2 --- /dev/null +++ b/tests/various/json_param_defaults.ys @@ -0,0 +1,8 @@ +! mkdir -p temp +read_verilog -sv json_param_defaults.v +write_json temp/json_param_defaults.json +design -reset +read_json temp/json_param_defaults.json +write_verilog -noattr -defaultparams temp/json_param_defaults.v +! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v +! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v diff --git a/tests/verific/mixed_flist.flist b/tests/verific/mixed_flist.flist new file mode 100644 index 000000000..d4edb8532 --- /dev/null +++ b/tests/verific/mixed_flist.flist @@ -0,0 +1,2 @@ +mixed_flist.sv +mixed_flist.vhd diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv new file mode 100644 index 000000000..28e073891 --- /dev/null +++ b/tests/verific/mixed_flist.sv @@ -0,0 +1,4 @@ +module sv_top(input logic a, output logic y); + // Instantiates VHDL entity to ensure mixed -f list is required + vhdl_mod u_vhdl(.a(a), .y(y)); +endmodule diff --git a/tests/verific/mixed_flist.vhd b/tests/verific/mixed_flist.vhd new file mode 100644 index 000000000..25a10f963 --- /dev/null +++ b/tests/verific/mixed_flist.vhd @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_mod is + port ( + a : in std_logic; + y : out std_logic + ); +end entity vhdl_mod; + +architecture rtl of vhdl_mod is +begin + y <= a; +end architecture rtl; diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys new file mode 100644 index 000000000..9f5fe607a --- /dev/null +++ b/tests/verific/mixed_flist.ys @@ -0,0 +1,3 @@ +verific -f -sv mixed_flist.flist +verific -import sv_top +select -assert-mod-count 1 sv_top diff --git a/tests/verific/run-test.sh b/tests/verific/run-test.sh index 2e340916d..1666ee1f9 100755 --- a/tests/verific/run-test.sh +++ b/tests/verific/run-test.sh @@ -2,4 +2,4 @@ set -eu source ../gen-tests-makefile.sh generate_mk --yosys-scripts --bash -sed -i '1i\export ASAN_OPTIONS=halt_on_error=0' run-test.mk +{ echo 'export ASAN_OPTIONS=halt_on_error=0'; cat run-test.mk; } > run-test.mk.tmp && mv run-test.mk.tmp run-test.mk diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore index b16ed0890..6a226989c 100644 --- a/tests/verilog/.gitignore +++ b/tests/verilog/.gitignore @@ -1,3 +1,4 @@ +/bug5572.v /const_arst.v /const_sr.v /doubleslash.v diff --git a/tests/verilog/bug5572.ys b/tests/verilog/bug5572.ys new file mode 100644 index 000000000..3044e3572 --- /dev/null +++ b/tests/verilog/bug5572.ys @@ -0,0 +1,15 @@ +read_rtlil << EOT +module \top + wire \sig + wire \val + process $2 + attribute \full_case 1 + switch \sig + end + end +end +EOT + +write_verilog bug5572.v +design -reset +read_verilog bug5572.v diff --git a/tests/verilog/genblk_wire.sv b/tests/verilog/genblk_wire.sv new file mode 100644 index 000000000..ef95fa98a --- /dev/null +++ b/tests/verilog/genblk_wire.sv @@ -0,0 +1,20 @@ +module gold(a, b); + output wire [1:0] a; + input wire [1:0] b; + genvar i; + for (i = 0; i < 2; i++) begin + wire x; + assign x = b[i]; + assign a[i] = x; + end +endmodule + +module gate(a, b); + output wire [1:0] a; + input wire [1:0] b; + genvar i; + for (i = 0; i < 2; i++) begin + assign x = b[i]; + assign a[i] = x; + end +endmodule diff --git a/tests/verilog/genblk_wire.ys b/tests/verilog/genblk_wire.ys new file mode 100644 index 000000000..582303760 --- /dev/null +++ b/tests/verilog/genblk_wire.ys @@ -0,0 +1,17 @@ +logger -expect warning "Identifier `\\genblk1[[]0[]]\.x' is implicitly declared." 1 +logger -expect warning "Identifier `\\genblk1[[]1[]]\.x' is implicitly declared." 1 +read_verilog -sv genblk_wire.sv +logger -check-expected + +select -assert-count 1 gate/genblk1[0].x +select -assert-count 1 gate/genblk1[1].x +select -assert-count 0 gate/genblk1[2].x + +select -assert-count 1 gold/genblk1[0].x +select -assert-count 1 gold/genblk1[1].x +select -assert-count 0 gold/genblk1[2].x + +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/xprop/run-test.sh b/tests/xprop/run-test.sh index 84b7c4ac4..303c0bb3b 100755 --- a/tests/xprop/run-test.sh +++ b/tests/xprop/run-test.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +source ../common-env.sh set -e python3 generate.py $@